diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-01-08 08:54:16 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-01-08 08:54:16 -0500 |
| commit | fbeced6135151cc70f83b95603589bcca53f3efc (patch) | |
| tree | cb8a877be1970b24d2eca0851fa5bfe5f5bca340 /tests/long/se | |
| parent | 25efbb5bdcc037826aac4ee2c9604dabb70e0ee5 (diff) | |
| download | gem5-fbeced6135151cc70f83b95603589bcca53f3efc.tar.xz | |
stats: update stats for previous six changes
Diffstat (limited to 'tests/long/se')
| -rw-r--r-- | tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt | 1190 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1162 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 16 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1402 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1134 | ||||
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1176 | ||||
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1368 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 1292 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1172 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt | 1110 |
10 files changed, 5513 insertions, 5509 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 650fe9ea1..3adbcac4f 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164568 # Number of seconds simulated -sim_ticks 164568389500 # Number of ticks simulated -final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164543 # Number of seconds simulated +sim_ticks 164543008000 # Number of ticks simulated +final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61098 # Simulator instruction rate (inst/s) -host_op_rate 64561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17638362 # Simulator tick rate (ticks/s) -host_mem_usage 233000 # Number of bytes of host memory used -host_seconds 9330.14 # Real time elapsed on the host -sim_insts 570052720 # Number of instructions simulated -sim_ops 602360926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1702080 # Number of bytes read from this memory -system.physmem.bytes_read::total 1749184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory -system.physmem.bytes_written::total 162368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 736 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26595 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 286228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10342691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10628919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 286228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 286228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 986629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 986629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 986629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 286228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10342691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11615548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27332 # Total number of read requests seen -system.physmem.writeReqs 2537 # Total number of write requests seen -system.physmem.cpureqs 29869 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1749184 # Total number of bytes read from memory -system.physmem.bytesWritten 162368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1749184 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() +host_inst_rate 153982 # Simulator instruction rate (inst/s) +host_op_rate 162709 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44446364 # Simulator tick rate (ticks/s) +host_mem_usage 244392 # Number of bytes of host memory used +host_seconds 3702.06 # Real time elapsed on the host +sim_insts 570051585 # Number of instructions simulated +sim_ops 602359791 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1700992 # Number of bytes read from this memory +system.physmem.bytes_read::total 1747904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162560 # Number of bytes written to this memory +system.physmem.bytes_written::total 162560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26578 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2540 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2540 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 285105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10337674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10622779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 285105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 285105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 987948 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 987948 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 987948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 285105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10337674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11610727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27312 # Total number of read requests seen +system.physmem.writeReqs 2540 # Total number of write requests seen +system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1747904 # Total number of bytes read from memory +system.physmem.bytesWritten 162560 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1747904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162560 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1706 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1733 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1745 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1741 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 157 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164568372500 # Total gap between requests +system.physmem.totGap 164542992000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27332 # Categorize read packet sizes +system.physmem.readPktSize::6 27312 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2537 # categorize write packet sizes +system.physmem.writePktSize::6 2540 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 785 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -145,9 +145,9 @@ system.physmem.wrQLenPdf::3 111 # Wh system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 953339495 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1657961495 # Sum of mem lat for all requests -system.physmem.totBusLat 109328000 # Total cycles spent in databus access -system.physmem.totBankLat 595294000 # Total cycles spent in bank access -system.physmem.avgQLat 34879.98 # Average queueing delay per request -system.physmem.avgBankLat 21780.11 # Average bank access latency per request +system.physmem.totQLat 954202972 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1658730972 # Sum of mem lat for all requests +system.physmem.totBusLat 109248000 # Total cycles spent in databus access +system.physmem.totBankLat 595280000 # Total cycles spent in bank access +system.physmem.avgQLat 34937.13 # Average queueing delay per request +system.physmem.avgBankLat 21795.55 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 60660.09 # Average memory access latency -system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 60732.68 # Average memory access latency +system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 6.05 # Average write queue length over time -system.physmem.readRowHits 17765 # Number of row buffer hits during reads -system.physmem.writeRowHits 1091 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes -system.physmem.avgGap 5509671.31 # Average gap between requests +system.physmem.avgWrQLen 7.51 # Average write queue length over time +system.physmem.readRowHits 17750 # Number of row buffer hits during reads +system.physmem.writeRowHits 1096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes +system.physmem.avgGap 5511958.73 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,141 +235,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329136780 # number of cpu cycles simulated +system.cpu.numCycles 329086017 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85146783 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 79928286 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2342158 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47212748 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46871026 # Number of BTB hits +system.cpu.BPredUnit.lookups 85130885 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 79914937 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2339051 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47115734 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46860934 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68501012 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119329476 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67084221 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755002 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328178875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1427305 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 879 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48288239 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129602885 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13082707 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119327277 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 198 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67069040 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 754631 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328130780 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198558186 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8890662 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9436402 2.88% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4398507 1.34% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5788329 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198528126 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20911347 6.37% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4965496 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14342607 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8889042 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9432606 2.87% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4398382 1.34% 79.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5787527 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60875647 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328178875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96199179 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4737184 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1561 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703240498 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5895 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10725676 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114043085 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694816428 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 328130780 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258689 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92913811 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96211222 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107901766 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20387668 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10716313 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4735353 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1507 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703148359 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5732 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10716313 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107108772 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14420824 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39598 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114018818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81826455 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694730633 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721301805 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230529005 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230528877 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 59350869 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20332423 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 690 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721206841 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230143140 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230143012 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93882616 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172202980 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80458110 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21583677 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28704390 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 679987725 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3320 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645601186 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1370428 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328178875 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 93789468 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1631 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1577 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170614097 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172186244 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80451329 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21497797 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28523197 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 679922328 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2842 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645571900 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1371428 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77382290 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193030922 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 138 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328130780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967423 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.726248 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68164684 20.77% 20.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28810425 8.78% 91.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14904242 4.54% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5586841 1.70% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6537919 1.99% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68155781 20.77% 20.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85368264 26.02% 46.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75828661 23.11% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40814489 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28806063 8.78% 91.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14910916 4.54% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5593541 1.70% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6461751 1.97% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2191314 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328178875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328130780 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2691247 71.35% 77.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 863918 22.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 217275 5.77% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2690091 71.47% 77.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 856746 22.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403371869 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403353378 62.48% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued @@ -398,279 +398,283 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165559477 25.64% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76663269 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165552451 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76659500 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645601186 # Type of FU issued -system.cpu.iq.rate 1.961498 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624523749 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645571900 # Type of FU issued +system.cpu.iq.rate 1.961712 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3764112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005831 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624410084 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757319559 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637543970 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649373276 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649335992 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30369655 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30371258 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23250160 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123060 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10236870 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23233651 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124604 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10230316 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12923 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32784 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12884 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 32539 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10725676 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 690728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32845 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16029 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1358556 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460812 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2819368 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641523461 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163490704 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4077725 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10716313 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 798788 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 92055 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 679928215 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 686727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172186244 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80451329 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1514 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 33028 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15856 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1355593 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460304 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2815897 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641504035 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163487420 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4067865 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3107 # number of nop insts executed -system.cpu.iew.exec_refs 239380202 # number of memory reference insts executed -system.cpu.iew.exec_branches 74672586 # Number of branches executed -system.cpu.iew.exec_stores 75889498 # Number of stores executed -system.cpu.iew.exec_rate 1.949109 # Inst execution rate -system.cpu.iew.wb_sent 638973087 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637563068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418509904 # num instructions producing a value -system.cpu.iew.wb_consumers 649810327 # num instructions consuming a value +system.cpu.iew.exec_nop 3045 # number of nop insts executed +system.cpu.iew.exec_refs 239375677 # number of memory reference insts executed +system.cpu.iew.exec_branches 74669000 # Number of branches executed +system.cpu.iew.exec_stores 75888257 # Number of stores executed +system.cpu.iew.exec_rate 1.949351 # Inst execution rate +system.cpu.iew.wb_sent 638951120 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637543986 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418515101 # num instructions producing a value +system.cpu.iew.wb_consumers 649819096 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937076 # insts written-back per cycle +system.cpu.iew.wb_rate 1.937317 # insts written-back per cycle system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77641136 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2340694 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317453199 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897480 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237382 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 77576557 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2337624 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317414467 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897708 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237617 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93244159 29.37% 29.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104350587 32.87% 62.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42987524 13.54% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8793922 2.77% 78.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25958876 8.18% 86.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12900336 4.06% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7627072 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1171824 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20418899 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93227454 29.37% 29.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104339541 32.87% 62.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42982023 13.54% 75.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8785495 2.77% 78.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25936003 8.17% 86.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12920810 4.07% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7630828 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1171764 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20420549 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317453199 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052771 # Number of instructions committed -system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 317414467 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570051636 # Number of instructions committed +system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174060 # Number of memory references committed -system.cpu.commit.loads 148952820 # Number of loads committed +system.cpu.commit.refs 219173606 # Number of memory references committed +system.cpu.commit.loads 148952593 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70892751 # Number of branches committed +system.cpu.commit.branches 70892524 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20418899 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20420549 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 977035801 # The number of ROB reads -system.cpu.rob.rob_writes 1370761733 # The number of ROB writes -system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 957905 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052720 # Number of Instructions Simulated -system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated -system.cpu.cpi 0.577380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577380 # CPI: Total CPI of All Threads -system.cpu.ipc 1.731963 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.731963 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204362065 # number of integer regfile reads -system.cpu.int_regfile_writes 663044095 # number of integer regfile writes +system.cpu.rob.rob_reads 976929705 # The number of ROB reads +system.cpu.rob.rob_writes 1370620821 # The number of ROB writes +system.cpu.timesIdled 41180 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 955237 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570051585 # Number of Instructions Simulated +system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated +system.cpu.cpi 0.577292 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577292 # CPI: Total CPI of All Threads +system.cpu.ipc 1.732227 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.732227 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204271897 # number of integer regfile reads +system.cpu.int_regfile_writes 663022837 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234776328 # number of misc regfile reads -system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 60 # number of replacements -system.cpu.icache.tagsinuse 685.359263 # Cycle average of tags in use -system.cpu.icache.total_refs 67083066 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81808.617073 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 234769906 # number of misc regfile reads +system.cpu.misc_regfile_writes 2656 # number of misc regfile writes +system.cpu.icache.replacements 58 # number of replacements +system.cpu.icache.tagsinuse 683.079303 # Cycle average of tags in use +system.cpu.icache.total_refs 67067899 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 817 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82090.451652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 685.359263 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.334648 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.334648 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67083066 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67083066 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67083066 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits -system.cpu.icache.overall_hits::total 67083066 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1155 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1155 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1155 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1155 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1155 # number of overall misses -system.cpu.icache.overall_misses::total 1155 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51421999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51421999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51421999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51421999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51421999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51421999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67084221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67084221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67084221 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67084221 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67084221 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67084221 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 683.079303 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.333535 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.333535 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67067899 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67067899 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67067899 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67067899 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67067899 # number of overall hits +system.cpu.icache.overall_hits::total 67067899 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses +system.cpu.icache.overall_misses::total 1141 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51270999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51270999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51270999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51270999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51270999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51270999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67069040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67069040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67069040 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67069040 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67069040 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67069040 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44521.211255 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44521.211255 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44521.211255 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44521.211255 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44935.143734 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44935.143734 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44935.143734 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44935.143734 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.555556 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 335 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 335 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 335 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 335 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 335 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38656999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38656999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38656999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38656999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38656999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38656999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 322 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 322 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 322 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 322 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 322 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39128499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39128499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39128499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39128499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39128499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39128499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47142.681707 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47142.681707 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47775.945055 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47775.945055 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47775.945055 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47775.945055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47775.945055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47775.945055 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2559 # number of replacements -system.cpu.l2cache.tagsinuse 22365.188888 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2562 # number of replacements +system.cpu.l2cache.tagsinuse 22345.080888 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517383 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24154 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.420179 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20763.498620 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 646.825199 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 954.865069 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633652 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019740 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.029140 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.682531 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 81 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 192805 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088160 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061308 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061308 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38041.822647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139474.739612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126010.355668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58459.975493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58459.975493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440681 # number of replacements -system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use -system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits -system.cpu.dcache.overall_hits::total 197562725 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses -system.cpu.dcache.overall_misses::total 3714801 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159649500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5159649500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250552202 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40250552202 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45410201702 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45410201702 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998901 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131514845 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131514845 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66043576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66043576 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1323 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1323 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 197558421 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197558421 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197558421 # number of overall hits +system.cpu.dcache.overall_hits::total 197558421 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40277017700 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 312000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 312000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45431972700 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45431972700 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45431972700 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45431972700 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131856643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131856643 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.944558 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.944558 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.925268 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.925268 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12224.127673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12224.127673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201274174 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201274174 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201274174 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201274174 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048604 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048604 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.014892 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.014892 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018461 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018461 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018461 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018461 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15081.875845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15081.875845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11937.627414 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 11937.627414 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15600 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15600 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12226.854880 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12226.854880 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 132982 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4828 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.543911 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks -system.cpu.dcache.writebacks::total 421636 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060484256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060484256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.143266 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.143266 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.631998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.631998 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 421606 # number of writebacks +system.cpu.dcache.writebacks::total 421606 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144292 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144292 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3126791 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3126791 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 20 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3271083 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3271083 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3271083 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3271083 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247164 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444670 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444670 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444670 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444670 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2876994000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2876994000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4061058256 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4061058256 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6938052256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6938052256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938052256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6938052256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14566.615698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14566.615698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16430.622000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16430.622000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 48597bbbd..5f24b4574 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026786 # Number of seconds simulated -sim_ticks 26786364500 # Number of ticks simulated -final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026773 # Number of seconds simulated +sim_ticks 26773408500 # Number of ticks simulated +final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55091 # Simulator instruction rate (inst/s) -host_op_rate 55487 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16288150 # Simulator tick rate (ticks/s) -host_mem_usage 365372 # Number of bytes of host memory used -host_seconds 1644.53 # Real time elapsed on the host -sim_insts 90599358 # Number of instructions simulated -sim_ops 91249911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory -system.physmem.bytes_read::total 992768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15512 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1689218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35373221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37062439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1689218 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1689218 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1689218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35373221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37062439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15512 # Total number of read requests seen +host_inst_rate 153523 # Simulator instruction rate (inst/s) +host_op_rate 154625 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45373007 # Simulator tick rate (ticks/s) +host_mem_usage 376436 # Number of bytes of host memory used +host_seconds 590.07 # Real time elapsed on the host +sim_insts 90589798 # Number of instructions simulated +sim_ops 91240351 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory +system.physmem.bytes_read::total 992576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15509 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1680473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35392729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37073203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1680473 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1680473 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1680473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35392729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37073203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15509 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15514 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 992768 # Total number of bytes read from memory +system.physmem.cpureqs 15512 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992576 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992768 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992576 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1014 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 964 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 877 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 976 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 936 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1011 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 930 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 933 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1021 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 976 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26786186500 # Total gap between requests +system.physmem.totGap 26773229500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15512 # Categorize read packet sizes +system.physmem.readPktSize::6 15509 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,12 +95,12 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 2 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 45051479 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests -system.physmem.totBusLat 62048000 # Total cycles spent in databus access -system.physmem.totBankLat 172004000 # Total cycles spent in bank access -system.physmem.avgQLat 2904.30 # Average queueing delay per request -system.physmem.avgBankLat 11088.45 # Average bank access latency per request +system.physmem.totQLat 45602981 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 279992981 # Sum of mem lat for all requests +system.physmem.totBusLat 62036000 # Total cycles spent in databus access +system.physmem.totBankLat 172354000 # Total cycles spent in bank access +system.physmem.avgQLat 2940.42 # Average queueing delay per request +system.physmem.avgBankLat 11113.16 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 17992.75 # Average memory access latency -system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 18053.58 # Average memory access latency +system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15087 # Number of row buffer hits during reads +system.physmem.readRowHits 15086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1726804.18 # Average gap between requests +system.physmem.avgGap 1726302.76 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,142 +228,142 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53572730 # number of cpu cycles simulated +system.cpu.numCycles 53546818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26681190 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22001511 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 842165 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11371976 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11281654 # Number of BTB hits +system.cpu.BPredUnit.lookups 26672080 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21992542 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 842598 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11362388 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11268059 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 70167 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11338226 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24008993 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4747196 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11262084 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13843627 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 330314 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53334178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.412341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215312 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1666559 3.12% 71.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2918525 5.47% 76.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1512890 2.84% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090822 2.04% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29363698 55.06% 55.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3375400 6.33% 61.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2026423 3.80% 65.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1553443 2.91% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1668565 3.13% 71.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2920644 5.48% 76.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1511002 2.83% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1091875 2.05% 81.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9823128 18.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4441470 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126048465 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42747 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3892391 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 53334178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498108 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.386304 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16944806 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9096910 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22405465 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1004110 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3882887 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4441553 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8682 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125956281 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42689 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3882887 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18731656 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3549082 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 155235 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21520684 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5494634 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123060237 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29470902 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5524793 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2121904 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1282766 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118150173 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10438 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105160593 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79722 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 429079 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4593412 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1240 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143474506 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536032151 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536027496 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4655 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36060320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4617 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4615 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12531131 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29463379 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5514746 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2152870 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1249780 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118072720 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8484 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105142122 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 71988 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26643181 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65222929 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 266 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53334178 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.971384 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.909777 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4978396 9.33% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2962958 5.55% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2475458 4.64% 98.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 518730 0.97% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15298443 28.68% 28.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11631181 21.81% 50.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8279084 15.52% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6786399 12.72% 78.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4950529 9.28% 88.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2953624 5.54% 93.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2464815 4.62% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 526374 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 443729 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53334178 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340422 51.49% 58.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275350 41.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 44991 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 339313 51.37% 58.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 276174 41.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74420683 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74410825 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10970 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -385,294 +385,294 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 146 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 182 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25610261 24.35% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5118329 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25604346 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5115650 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105160593 # Type of FU issued -system.cpu.iq.rate 1.962950 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1049 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 331 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105821300 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 443954 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105142122 # Type of FU issued +system.cpu.iq.rate 1.963555 # Inst issue rate +system.cpu.iq.fu_busy_cnt 660505 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006282 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264350195 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144728935 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102671361 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 720 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1005 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105802266 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 442877 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6895024 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7123 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6272 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 778037 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6889413 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6770 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6285 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 769902 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31249 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 27948 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3892391 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66339 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6977 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6272 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446356 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445453 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891809 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104181304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25288567 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 979289 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3882887 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 927098 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127053 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118093920 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309711 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29463379 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5514746 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4596 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66094 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6965 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6285 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446526 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446132 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892658 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104164248 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25284832 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 977874 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12695 # number of nop insts executed -system.cpu.iew.exec_refs 30349931 # number of memory reference insts executed -system.cpu.iew.exec_branches 21325057 # Number of branches executed -system.cpu.iew.exec_stores 5061364 # Number of stores executed -system.cpu.iew.exec_rate 1.944670 # Inst execution rate -system.cpu.iew.wb_sent 102965645 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102686542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62242061 # num instructions producing a value -system.cpu.iew.wb_consumers 104289210 # num instructions consuming a value +system.cpu.iew.exec_nop 12716 # number of nop insts executed +system.cpu.iew.exec_refs 30343472 # number of memory reference insts executed +system.cpu.iew.exec_branches 21324084 # Number of branches executed +system.cpu.iew.exec_stores 5058640 # Number of stores executed +system.cpu.iew.exec_rate 1.945293 # Inst execution rate +system.cpu.iew.wb_sent 102950061 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102671670 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62244850 # num instructions producing a value +system.cpu.iew.wb_consumers 104302213 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.916769 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596822 # average fanout of values written-back +system.cpu.iew.wb_rate 1.917419 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596774 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26913567 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833602 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49467817 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.844887 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541636 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 26843909 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 834006 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49451291 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.845310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541193 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19986876 40.40% 40.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13133000 26.55% 66.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4163273 8.42% 75.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3434953 6.94% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533681 3.10% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 739386 1.49% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 948988 1.92% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 248747 0.50% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5278913 10.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19963736 40.37% 40.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13137085 26.57% 66.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4166734 8.43% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3433201 6.94% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1540600 3.12% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 738938 1.49% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 946959 1.91% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 248344 0.50% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275694 10.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49467817 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611967 # Number of instructions committed -system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 49451291 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90602407 # Number of instructions committed +system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322634 # Number of memory references committed -system.cpu.commit.loads 22575878 # Number of loads committed +system.cpu.commit.refs 27318810 # Number of memory references committed +system.cpu.commit.loads 22573966 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18734216 # Number of branches committed +system.cpu.commit.branches 18732304 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. +system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5278913 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275694 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162359257 # The number of ROB reads -system.cpu.rob.rob_writes 240263976 # The number of ROB writes -system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599358 # Number of Instructions Simulated -system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated -system.cpu.cpi 0.591315 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.591315 # CPI: Total CPI of All Threads -system.cpu.ipc 1.691147 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.691147 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495578845 # number of integer regfile reads -system.cpu.int_regfile_writes 120555497 # number of integer regfile writes -system.cpu.fp_regfile_reads 176 # number of floating regfile reads -system.cpu.fp_regfile_writes 427 # number of floating regfile writes -system.cpu.misc_regfile_reads 29099412 # number of misc regfile reads -system.cpu.misc_regfile_writes 11608 # number of misc regfile writes -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 632.599736 # Cycle average of tags in use -system.cpu.icache.total_refs 13840965 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 735 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18831.244898 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 162266732 # The number of ROB reads +system.cpu.rob.rob_writes 240096387 # The number of ROB writes +system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 212640 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90589798 # Number of Instructions Simulated +system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated +system.cpu.cpi 0.591091 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.591091 # CPI: Total CPI of All Threads +system.cpu.ipc 1.691787 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.691787 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495496065 # number of integer regfile reads +system.cpu.int_regfile_writes 120529637 # number of integer regfile writes +system.cpu.fp_regfile_reads 153 # number of floating regfile reads +system.cpu.fp_regfile_writes 387 # number of floating regfile writes +system.cpu.misc_regfile_reads 29090556 # number of misc regfile reads +system.cpu.misc_regfile_writes 7784 # number of misc regfile writes +system.cpu.icache.replacements 5 # number of replacements +system.cpu.icache.tagsinuse 628.046446 # Cycle average of tags in use +system.cpu.icache.total_refs 13842647 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 730 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18962.530137 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 632.599736 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.308887 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.308887 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13840965 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13840965 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13840965 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits -system.cpu.icache.overall_hits::total 13840965 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses -system.cpu.icache.overall_misses::total 984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 628.046446 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306663 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306663 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13842647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13842647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13842647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13842647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13842647 # number of overall hits +system.cpu.icache.overall_hits::total 13842647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 979 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 979 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 979 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 979 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 979 # number of overall misses +system.cpu.icache.overall_misses::total 979 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47680999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47680999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47680999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47680999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47680999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47680999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13843626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13843626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13843626 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13843626 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13843626 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13843626 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48703.778345 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48703.778345 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48703.778345 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48703.778345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48703.778345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48703.778345 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1057 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 132.125000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36763999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36763999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36763999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36763999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36763999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36763999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 736 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 736 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 736 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 736 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 736 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36881499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36881499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36881499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36881499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36881499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36881499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49748.307172 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49748.307172 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50110.732337 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50110.732337 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50110.732337 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50110.732337 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50110.732337 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50110.732337 # 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average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28984.037348 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28984.037348 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943495 # number of replacements -system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use -system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits -system.cpu.dcache.overall_hits::total 28133775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses -system.cpu.dcache.overall_misses::total 1370806 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943481 # number of replacements +system.cpu.dcache.tagsinuse 3674.468837 # Cycle average of tags in use +system.cpu.dcache.total_refs 28144290 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947577 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.701322 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7935444000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3674.468837 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.897087 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.897087 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23599200 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23599200 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4537276 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4537276 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28136476 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28136476 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28136476 # number of overall hits +system.cpu.dcache.overall_hits::total 28136476 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173036 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173036 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 197705 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 197705 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1370741 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1370741 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1370741 # number of overall misses +system.cpu.dcache.overall_misses::total 1370741 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13886322000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13886322000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5375913921 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5375913921 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19262235921 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19262235921 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19262235921 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19262235921 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24772236 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24772236 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29507217 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29507217 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29507217 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29507217 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047353 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047353 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041754 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041754 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046454 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046454 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046454 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046454 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.933363 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.933363 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27191.593136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27191.593136 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29214.285714 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29214.285714 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14052.425601 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14052.425601 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 132657 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23814 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.570547 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks -system.cpu.dcache.writebacks::total 942892 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks +system.cpu.dcache.writebacks::total 942884 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268972 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 268972 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154186 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154186 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 423158 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423158 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423158 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423158 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904064 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904064 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43519 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43519 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947583 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947583 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947583 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947583 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9987518000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9987518000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 958248463 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 958248463 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945766463 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10945766463 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945766463 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10945766463 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036495 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036495 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009191 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009191 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032114 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032114 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11047.357267 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11047.357267 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22019.082768 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22019.082768 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 0c883f6c5..80c453da2 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.065983 # Nu sim_ticks 65982862500 # Number of ticks simulated final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39069 # Simulator instruction rate (inst/s) -host_op_rate 68794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16316772 # Simulator tick rate (ticks/s) -host_mem_usage 376348 # Number of bytes of host memory used -host_seconds 4043.87 # Real time elapsed on the host +host_inst_rate 97221 # Simulator instruction rate (inst/s) +host_op_rate 171190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40603649 # Simulator tick rate (ticks/s) +host_mem_usage 385836 # Number of bytes of host memory used +host_seconds 1625.05 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory @@ -270,7 +270,7 @@ system.cpu.iq.iqNonSpecInstsAdded 1679 # Nu system.cpu.iq.iqInstsIssued 302165189 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 115128 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 36987116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 54145851 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 54145843 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 131886743 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.291096 # Number of insts issued each cycle @@ -363,7 +363,7 @@ system.cpu.iq.fu_busy_cnt 1958055 # FU system.cpu.iq.fu_busy_rate 0.006480 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 738289800 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 352827074 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 299525455 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 299525457 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 863 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses @@ -404,7 +404,7 @@ system.cpu.iew.exec_branches 30888175 # Nu system.cpu.iew.exec_stores 33015298 # Number of stores executed system.cpu.iew.exec_rate 2.277456 # Inst execution rate system.cpu.iew.wb_sent 299954363 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 299525609 # cumulative count of insts written-back +system.cpu.iew.wb_count 299525611 # cumulative count of insts written-back system.cpu.iew.wb_producers 219474385 # num instructions producing a value system.cpu.iew.wb_consumers 297941322 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index fe6fd5ff5..28e0cf940 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.206007 # Number of seconds simulated -sim_ticks 206006891000 # Number of ticks simulated -final_tick 206006891000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.199845 # Number of seconds simulated +sim_ticks 199845137000 # Number of ticks simulated +final_tick 199845137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48397 # Simulator instruction rate (inst/s) -host_op_rate 54519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19589283 # Simulator tick rate (ticks/s) -host_mem_usage 261836 # Number of bytes of host memory used -host_seconds 10516.31 # Real time elapsed on the host -sim_insts 508955198 # Number of instructions simulated -sim_ops 573341758 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9272640 # Number of bytes read from this memory -system.physmem.bytes_read::total 9488896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6250240 # Number of bytes written to this memory -system.physmem.bytes_written::total 6250240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144885 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148264 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97660 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97660 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1049751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45011310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46061061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1049751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1049751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30339956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30339956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30339956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1049751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45011310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 76401017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148265 # Total number of read requests seen -system.physmem.writeReqs 97660 # Total number of write requests seen -system.physmem.cpureqs 245934 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9488896 # Total number of bytes read from memory -system.physmem.bytesWritten 6250240 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9488896 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6250240 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9341 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8981 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9466 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9155 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 9694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8959 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9019 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8746 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5978 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6031 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6669 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6289 # Track writes on a per bank basis +host_inst_rate 125206 # Simulator instruction rate (inst/s) +host_op_rate 141162 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49524846 # Simulator tick rate (ticks/s) +host_mem_usage 271424 # Number of bytes of host memory used +host_seconds 4035.25 # Real time elapsed on the host +sim_insts 505237723 # Number of instructions simulated +sim_ops 569624283 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 216832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9264064 # Number of bytes read from this memory +system.physmem.bytes_read::total 9480896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6248064 # Number of bytes written to this memory +system.physmem.bytes_written::total 6248064 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3388 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144751 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148139 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97626 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97626 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1085000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46356214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47441214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1085000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1085000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31264529 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31264529 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31264529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1085000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46356214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78705743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148141 # Total number of read requests seen +system.physmem.writeReqs 97626 # Total number of write requests seen +system.physmem.cpureqs 245778 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9480896 # Total number of bytes read from memory +system.physmem.bytesWritten 6248064 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9480896 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6248064 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8810 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8975 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9245 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9113 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10253 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 9691 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8950 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9023 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8762 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5944 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6376 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5947 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6637 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6051 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6036 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6064 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5787 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 206006873500 # Total gap between requests +system.physmem.totGap 199845120000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148265 # Categorize read packet sizes +system.physmem.readPktSize::6 148141 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 97660 # categorize write packet sizes +system.physmem.writePktSize::6 97626 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 9 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1631933240 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4708845240 # Sum of mem lat for all requests -system.physmem.totBusLat 592780000 # Total cycles spent in databus access -system.physmem.totBankLat 2484132000 # Total cycles spent in bank access -system.physmem.avgQLat 11012.07 # Average queueing delay per request -system.physmem.avgBankLat 16762.59 # Average bank access latency per request +system.physmem.totQLat 1637260686 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4709936686 # Sum of mem lat for all requests +system.physmem.totBusLat 592324000 # Total cycles spent in databus access +system.physmem.totBankLat 2480352000 # Total cycles spent in bank access +system.physmem.avgQLat 11056.52 # Average queueing delay per request +system.physmem.avgBankLat 16749.97 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31774.66 # Average memory access latency -system.physmem.avgRdBW 46.06 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 30.34 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.06 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 30.34 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31806.49 # Average memory access latency +system.physmem.avgRdBW 47.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 31.26 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.44 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 31.26 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.48 # Data bus utilization in percentage +system.physmem.busUtil 0.49 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.58 # Average write queue length over time -system.physmem.readRowHits 128622 # Number of row buffer hits during reads -system.physmem.writeRowHits 35037 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.88 # Row buffer hit rate for writes -system.physmem.avgGap 837681.71 # Average gap between requests +system.physmem.avgWrQLen 8.64 # Average write queue length over time +system.physmem.readRowHits 128534 # Number of row buffer hits during reads +system.physmem.writeRowHits 35160 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.01 # Row buffer hit rate for writes +system.physmem.avgGap 813148.71 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,450 +235,450 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 412013783 # number of cpu cycles simulated +system.cpu.numCycles 399690275 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 182073557 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142374329 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7271583 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 93640941 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 88714986 # Number of BTB hits +system.cpu.BPredUnit.lookups 182820446 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 143128871 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7268870 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 92944153 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 87230072 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12682930 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115717 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 117168420 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 763090504 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182073557 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 101397916 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170904146 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35690489 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89173012 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 12684982 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116077 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 119371931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761680364 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182820446 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99915054 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170174199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35702256 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75350704 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 387 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 113064693 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2443926 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 404864320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.113664 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.961425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 616 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114527354 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2441016 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 392530086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.176527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.990721 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 233972788 57.79% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14182494 3.50% 61.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22907477 5.66% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746192 5.62% 72.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20892499 5.16% 77.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13088798 3.23% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13051042 3.22% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11993527 2.96% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52029503 12.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222368477 56.65% 56.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14183765 3.61% 60.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22901577 5.83% 66.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22747664 5.80% 71.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20903604 5.33% 77.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11591587 2.95% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13062137 3.33% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11992821 3.06% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52778454 13.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 404864320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.441911 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.852099 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127567795 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83214346 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 161081773 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5456100 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27544306 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26131693 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76746 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 833046476 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 293832 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27544306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135636368 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9592122 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57998215 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158294561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15798748 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 804356889 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3056071 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8809517 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 236 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 960228219 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3520047664 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3520046036 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1628 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200251 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288027968 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3037400 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3037395 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48984020 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170948465 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74181775 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27930048 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15662241 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 757938362 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4467556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 669004170 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1390745 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187223839 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479595431 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746429 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 404864320 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.652416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.728625 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 392530086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457405 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.905676 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129024913 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70885415 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158884550 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6176695 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27558513 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26126183 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76772 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825683046 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296199 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27558513 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135608190 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9588825 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46459719 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158300780 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15014059 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800754331 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1065 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3044118 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8771537 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 204 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954467105 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3501224581 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3501223353 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1228 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 288214814 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293021 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293019 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41499614 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170286842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73502565 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28542432 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15757224 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755181384 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775400 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665429696 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1394216 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187494219 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479993782 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797768 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 392530086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.695232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.736006 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145294997 35.89% 35.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75803785 18.72% 54.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69074812 17.06% 71.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53696610 13.26% 84.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30882442 7.63% 92.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16155264 3.99% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9314791 2.30% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3366855 0.83% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1274764 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 137153831 34.94% 34.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69768231 17.77% 52.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71497423 18.21% 70.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53360624 13.59% 84.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31181551 7.94% 92.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16101363 4.10% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8735003 2.23% 98.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2914770 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1817290 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 404864320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392530086 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 478550 4.99% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6548662 68.24% 73.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2569141 26.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481185 5.01% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6545421 68.20% 73.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2570325 26.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 449957502 67.26% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383513 0.06% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 114 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 154129801 23.04% 90.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 64533237 9.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447832117 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383268 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 86 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153411814 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63802408 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 669004170 # Type of FU issued -system.cpu.iq.rate 1.623742 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9596353 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014344 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1753859495 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 950436200 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 649651296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 358 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665429696 # Type of FU issued +system.cpu.iq.rate 1.664863 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9596931 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014422 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1734380418 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947258082 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646140584 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 274 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 678600390 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8560025 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 675026522 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 105 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8582869 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44175415 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 40342 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810510 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16577803 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44257287 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42197 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 811123 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16642088 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19533 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4090 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27544306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4979953 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372702 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 763965600 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1116680 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170948465 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74181775 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2978814 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218949 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11431 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810510 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4004049 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8346983 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659511571 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150841037 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9492599 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27558513 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4987467 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372691 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760516980 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1117257 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170286842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73502565 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286858 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219486 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11052 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 811123 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4340984 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4003792 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8344776 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 656001968 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150122200 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9427728 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559682 # number of nop insts executed -system.cpu.iew.exec_refs 214084743 # number of memory reference insts executed -system.cpu.iew.exec_branches 139192858 # Number of branches executed -system.cpu.iew.exec_stores 63243706 # Number of stores executed -system.cpu.iew.exec_rate 1.600703 # Inst execution rate -system.cpu.iew.wb_sent 654626894 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 649651312 # cumulative count of insts written-back -system.cpu.iew.wb_producers 375421754 # num instructions producing a value -system.cpu.iew.wb_consumers 646280118 # num instructions consuming a value +system.cpu.iew.exec_nop 1560196 # number of nop insts executed +system.cpu.iew.exec_refs 212633148 # number of memory reference insts executed +system.cpu.iew.exec_branches 138504923 # Number of branches executed +system.cpu.iew.exec_stores 62510948 # Number of stores executed +system.cpu.iew.exec_rate 1.641276 # Inst execution rate +system.cpu.iew.wb_sent 651119979 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646140600 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374813030 # num instructions producing a value +system.cpu.iew.wb_consumers 646558310 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.576771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.580896 # average fanout of values written-back +system.cpu.iew.wb_rate 1.616603 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579705 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189306245 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721127 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7197604 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 377320014 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.523072 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.207570 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 189575186 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7194795 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 364971573 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.564418 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233675 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 165631141 43.90% 43.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102377769 27.13% 71.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33965417 9.00% 80.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18834681 4.99% 85.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16120892 4.27% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7588494 2.01% 91.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6947007 1.84% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3071988 0.81% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22782625 6.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157304822 43.10% 43.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98491978 26.99% 70.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33807803 9.26% 79.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18748044 5.14% 84.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16202992 4.44% 88.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7453577 2.04% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6993904 1.92% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3174450 0.87% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22794003 6.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 377320014 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299082 # Number of instructions committed -system.cpu.commit.committedOps 574685642 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 364971573 # Number of insts commited each cycle +system.cpu.commit.committedInsts 506581607 # Number of instructions committed +system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377022 # Number of memory references committed -system.cpu.commit.loads 126773050 # Number of loads committed +system.cpu.commit.refs 182890032 # Number of memory references committed +system.cpu.commit.loads 126029555 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 122291796 # Number of branches committed +system.cpu.commit.branches 121548301 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701673 # Number of committed integer instructions. +system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22782625 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22794003 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1118522138 # The number of ROB reads -system.cpu.rob.rob_writes 1555649058 # The number of ROB writes -system.cpu.timesIdled 306506 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7149463 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955198 # Number of Instructions Simulated -system.cpu.committedOps 573341758 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955198 # Number of Instructions Simulated -system.cpu.cpi 0.809529 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.809529 # CPI: Total CPI of All Threads -system.cpu.ipc 1.235287 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.235287 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3078340491 # number of integer regfile reads -system.cpu.int_regfile_writes 757780607 # number of integer regfile writes +system.cpu.rob.rob_reads 1102713785 # The number of ROB reads +system.cpu.rob.rob_writes 1548767048 # The number of ROB writes +system.cpu.timesIdled 306858 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7160189 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 505237723 # Number of Instructions Simulated +system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated +system.cpu.cpi 0.791093 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.791093 # CPI: Total CPI of All Threads +system.cpu.ipc 1.264073 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.264073 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3059184222 # number of integer regfile reads +system.cpu.int_regfile_writes 752090779 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 213817535 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464074 # number of misc regfile writes -system.cpu.icache.replacements 15034 # number of replacements -system.cpu.icache.tagsinuse 1084.596639 # Cycle average of tags in use -system.cpu.icache.total_refs 113043631 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16888 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6693.725189 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 210880028 # number of misc regfile reads +system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes +system.cpu.icache.replacements 15058 # number of replacements +system.cpu.icache.tagsinuse 1101.681539 # Cycle average of tags in use +system.cpu.icache.total_refs 114506253 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16915 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6769.509489 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1084.596639 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.529588 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.529588 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 113043631 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113043631 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113043631 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113043631 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113043631 # number of overall hits -system.cpu.icache.overall_hits::total 113043631 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21062 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21062 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21062 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21062 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21062 # number of overall misses -system.cpu.icache.overall_misses::total 21062 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 460496000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 460496000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 460496000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 460496000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 460496000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 460496000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 113064693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 113064693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 113064693 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 113064693 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 113064693 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 113064693 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21863.830595 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21863.830595 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21863.830595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21863.830595 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1088 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1101.681539 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537930 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537930 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114506253 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114506253 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114506253 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114506253 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114506253 # number of overall hits +system.cpu.icache.overall_hits::total 114506253 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21101 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21101 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21101 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21101 # number of overall misses +system.cpu.icache.overall_misses::total 21101 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 452371500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 452371500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 452371500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 452371500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 452371500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 452371500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114527354 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114527354 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114527354 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114527354 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114527354 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114527354 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21438.391545 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21438.391545 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21438.391545 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21438.391545 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.700000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4099 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4099 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4099 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4099 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4099 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4099 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16963 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16963 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16963 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16963 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16963 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340828000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 340828000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340828000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 340828000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340828000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 340828000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20092.436479 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20092.436479 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4104 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4104 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4104 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4104 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4104 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4104 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16997 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16997 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16997 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16997 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16997 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16997 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339326500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 339326500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339326500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 339326500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339326500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 339326500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19963.905395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19963.905395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115524 # number of replacements -system.cpu.l2cache.tagsinuse 26913.844111 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1781016 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146770 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.134741 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 106794042500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 22881.724629 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 362.646179 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3669.473303 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.698295 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011067 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.111983 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.821345 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13496 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804094 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817590 # 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number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43623 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 47007 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101285 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101285 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3384 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144908 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148292 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3384 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144908 # number of overall misses -system.cpu.l2cache.overall_misses::total 148292 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188319500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2550766500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2739086000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5396872000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5396872000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 188319500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7947638500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8135958000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 188319500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7947638500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8135958000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16880 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45794.780145 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45544.114249 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10500.909091 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10500.909091 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.216217 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.216217 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42329.244615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42165.597125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42169.340864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42329.244615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42165.597125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42169.340864 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192383 # number of replacements -system.cpu.dcache.tagsinuse 4054.755183 # Cycle average of tags in use -system.cpu.dcache.total_refs 191684453 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196479 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 160.207119 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.755183 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989930 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989930 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136225611 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136225611 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50993519 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50993519 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233068 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233068 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2232036 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2232036 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187219130 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187219130 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187219130 # number of overall hits -system.cpu.dcache.overall_hits::total 187219130 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1694816 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1694816 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3245787 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3245787 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4940603 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4940603 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4940603 # number of overall misses -system.cpu.dcache.overall_misses::total 4940603 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25904626000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25904626000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58849421949 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58849421949 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 574000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 574000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84754047949 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84754047949 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84754047949 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84754047949 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137920427 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137920427 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1192376 # number of replacements +system.cpu.dcache.tagsinuse 4058.257289 # Cycle average of tags in use +system.cpu.dcache.total_refs 190193687 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196472 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.962088 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4128824000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4058.257289 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990785 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990785 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136223717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136223717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50992367 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50992367 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488803 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488803 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 187216084 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187216084 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187216084 # number of overall hits +system.cpu.dcache.overall_hits::total 187216084 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1697690 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1697690 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3246939 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3246939 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4944629 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4944629 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4944629 # number of overall misses +system.cpu.dcache.overall_misses::total 4944629 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26054770000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26054770000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58807860452 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58807860452 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 537000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 537000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84862630452 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84862630452 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84862630452 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84862630452 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137921407 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137921407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233106 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2233106 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232036 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2232036 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192159733 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192159733 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192159733 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192159733 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012288 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012288 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059842 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059842 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000017 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000017 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025711 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025711 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025711 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15284.624408 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15284.624408 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18131.017824 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18131.017824 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15105.263158 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15105.263158 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17154.595896 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17154.595896 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17486 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15854 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1635 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 605 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.694801 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26.204959 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488838 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488838 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 192160713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192160713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192160713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192160713 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012309 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012309 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059863 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059863 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025732 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025732 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025732 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025732 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15347.189416 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15347.189416 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18111.784808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18111.784808 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15342.857143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15342.857143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17162.588023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17162.588023 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16266 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14829 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1654 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 595 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.834341 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 24.922689 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110621 # number of writebacks -system.cpu.dcache.writebacks::total 1110621 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 846554 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 846554 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2897494 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2897494 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3744048 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3744048 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3744048 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3744048 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848262 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848262 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348293 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348293 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196555 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196555 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196555 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196555 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11478175000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11478175000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269727997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269727997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19747902997 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11474356500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8274514996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8274514996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19748871496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19748871496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19748871496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19748871496 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13531.403033 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13531.403033 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23743.595183 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23743.595183 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13527.810494 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13527.810494 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23753.520165 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23753.520165 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 3611ed5dd..3350826f2 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068267 # Number of seconds simulated -sim_ticks 68267465500 # Number of ticks simulated -final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068072 # Number of seconds simulated +sim_ticks 68071881000 # Number of ticks simulated +final_tick 68071881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47859 # Simulator instruction rate (inst/s) -host_op_rate 61184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11965597 # Simulator tick rate (ticks/s) -host_mem_usage 240720 # Number of bytes of host memory used -host_seconds 5705.31 # Real time elapsed on the host -sim_insts 273048375 # Number of instructions simulated -sim_ops 349076099 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 273088 # Number of bytes read from this memory -system.physmem.bytes_read::total 467008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4267 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7297 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2840592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4000266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6840857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2840592 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2840592 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2840592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4000266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6840857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7297 # Total number of read requests seen +host_inst_rate 138205 # Simulator instruction rate (inst/s) +host_op_rate 176689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34456552 # Simulator tick rate (ticks/s) +host_mem_usage 251760 # Number of bytes of host memory used +host_seconds 1975.59 # Real time elapsed on the host +sim_insts 273036725 # Number of instructions simulated +sim_ops 349064449 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory +system.physmem.bytes_read::total 466240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2846873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4002357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6849230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2846873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2846873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2846873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4002357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6849230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7286 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7297 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 467008 # Total number of bytes read from memory +system.physmem.cpureqs 7288 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 466240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 467008 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 466240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 514 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 577 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 359 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 557 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 360 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68267283000 # Total gap between requests +system.physmem.totGap 68071860500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7297 # Categorize read packet sizes +system.physmem.readPktSize::6 7286 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,13 +95,13 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 36802775 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 167840775 # Sum of mem lat for all requests -system.physmem.totBusLat 29188000 # Total cycles spent in databus access -system.physmem.totBankLat 101850000 # Total cycles spent in bank access -system.physmem.avgQLat 5043.55 # Average queueing delay per request -system.physmem.avgBankLat 13957.79 # Average bank access latency per request +system.physmem.totQLat 38841760 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 170087760 # Sum of mem lat for all requests +system.physmem.totBusLat 29144000 # Total cycles spent in databus access +system.physmem.totBankLat 102102000 # Total cycles spent in bank access +system.physmem.avgQLat 5331.01 # Average queueing delay per request +system.physmem.avgBankLat 14013.45 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23001.34 # Average memory access latency -system.physmem.avgRdBW 6.84 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23344.46 # Average memory access latency +system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.84 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6392 # Number of row buffer hits during reads +system.physmem.readRowHits 6372 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9355527.34 # Average gap between requests +system.physmem.avgGap 9342830.15 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,107 +228,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136534932 # number of cpu cycles simulated +system.cpu.numCycles 136143763 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 41739250 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21065104 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1640413 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 26027262 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 16735646 # Number of BTB hits +system.cpu.BPredUnit.lookups 41692065 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21046025 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1612310 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25558633 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 16675018 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 38860072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed -system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21559517 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37487913 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 519565 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136324281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6736046 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7190 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 38720751 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 316654874 # Number of instructions fetch has processed +system.cpu.fetch.Branches 41692065 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23411064 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70618145 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6665842 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21550456 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1364 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37376595 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 521732 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 135933121 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.990728 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456678 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66156808 48.53% 48.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4881557 3.58% 65.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4156543 3.05% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3204825 2.35% 71.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4146681 3.04% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65940392 48.51% 48.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6730475 4.95% 53.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5637804 4.15% 57.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5998950 4.41% 62.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4879102 3.59% 65.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4141679 3.05% 68.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3188425 2.35% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4149669 3.05% 74.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35266625 25.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136324281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16729556 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7269016 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69099 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401164000 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 213330 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5039795 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63595532 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393365758 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 431881387 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2329985497 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1257436080 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47296554 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103432229 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91356063 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4280154 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5359345 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 383896453 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25411 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373948163 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1224653 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136324281 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 135933121 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.306236 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325886 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45271721 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16691056 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66469199 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2527476 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4973669 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7265289 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69057 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 400237870 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 218381 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4973669 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50782794 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1926905 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 308736 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63418534 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14522483 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 392567341 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 52 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1667501 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10227766 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1022 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431145358 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2325492453 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1253893551 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1071598902 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46579165 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11899 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11898 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36419091 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103284417 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91190896 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4278404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5313371 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383399978 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22859 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373603209 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1225399 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 33612220 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 83720105 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 135933121 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.748434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.022451 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24852307 18.23% 18.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 23977307 17.59% 78.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15767707 11.57% 90.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8831817 6.48% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3361471 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24617806 18.11% 18.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19905628 14.64% 32.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20463769 15.05% 47.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18134866 13.34% 61.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23975475 17.64% 78.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15748338 11.59% 90.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8799560 6.47% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3376937 2.48% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 910742 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136324281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 135933121 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9041 0.05% 0.05% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available @@ -348,22 +348,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46185 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46127 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7671 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 470 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190051 1.07% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6041 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241741 1.36% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9330966 52.43% 55.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7960919 44.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7573 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 401 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 189986 1.07% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6027 0.03% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241589 1.36% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9303270 52.42% 55.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7940124 44.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126153074 33.74% 33.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174128 0.58% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126062452 33.74% 33.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174186 0.58% 34.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued @@ -382,289 +382,295 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6786226 1.81% 36.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8470375 2.27% 38.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3426412 0.92% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600673 0.43% 39.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20911148 5.59% 45.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7171927 1.92% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134560 1.91% 49.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101505429 27.14% 76.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88438925 23.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6778330 1.81% 36.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8468082 2.27% 38.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426363 0.92% 39.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600385 0.43% 39.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20905129 5.60% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7170133 1.92% 47.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133112 1.91% 49.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101416985 27.15% 76.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88292763 23.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373948163 # Type of FU issued -system.cpu.iq.rate 2.738846 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653530497 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130436942 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118161488 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262975786 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128770067 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11107823 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373603209 # Type of FU issued +system.cpu.iq.rate 2.744182 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17748829 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047507 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 652552700 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 286781782 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249670215 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249561067 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130267469 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118091463 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262665125 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128686913 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11143467 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8781151 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 113920 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14326 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8978150 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8635669 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 113833 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14304 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8815313 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 176383 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1158 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 179767 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1150 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5039795 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 951526 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 345 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 384 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14326 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1283309 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 356464 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1639773 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370071311 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100289689 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3876852 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4973669 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 290169 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 43007 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383424336 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 947805 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103284417 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91190896 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11825 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 376 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14304 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1257323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 355165 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1612488 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 369752091 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100205261 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3851118 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1594 # number of nop insts executed -system.cpu.iew.exec_refs 187642898 # number of memory reference insts executed -system.cpu.iew.exec_branches 38279004 # Number of branches executed -system.cpu.iew.exec_stores 87353209 # Number of stores executed -system.cpu.iew.exec_rate 2.710451 # Inst execution rate -system.cpu.iew.wb_sent 368702519 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368038571 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182991065 # num instructions producing a value -system.cpu.iew.wb_consumers 363891400 # num instructions consuming a value +system.cpu.iew.exec_nop 1499 # number of nop insts executed +system.cpu.iew.exec_refs 187415465 # number of memory reference insts executed +system.cpu.iew.exec_branches 38269539 # Number of branches executed +system.cpu.iew.exec_stores 87210204 # Number of stores executed +system.cpu.iew.exec_rate 2.715894 # Inst execution rate +system.cpu.iew.wb_sent 368418252 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 367761678 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182872307 # num instructions producing a value +system.cpu.iew.wb_consumers 363527613 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.695563 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502873 # average fanout of values written-back +system.cpu.iew.wb_rate 2.701275 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503049 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34846819 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24450 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1571698 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131284486 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.658933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.660928 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 34359338 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1543637 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130959452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.665444 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.660816 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34526115 26.30% 26.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28464962 21.68% 47.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13313072 10.14% 58.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11375196 8.66% 66.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13798040 10.51% 77.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7398451 5.64% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3831320 2.92% 85.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3930958 2.99% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14646372 11.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34245793 26.15% 26.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28403736 21.69% 47.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13297993 10.15% 57.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11400251 8.71% 66.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13789663 10.53% 77.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7417902 5.66% 82.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3851196 2.94% 85.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3914096 2.99% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14638822 11.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131284486 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273048987 # Number of instructions committed -system.cpu.commit.committedOps 349076711 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130959452 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037337 # Number of instructions committed +system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177028991 # Number of memory references committed -system.cpu.commit.loads 94651078 # Number of loads committed +system.cpu.commit.refs 177024331 # Number of memory references committed +system.cpu.commit.loads 94648748 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36549040 # Number of branches committed +system.cpu.commit.branches 36546710 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279593931 # Number of committed integer instructions. +system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14646372 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14638822 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 500559121 # The number of ROB reads -system.cpu.rob.rob_writes 772890927 # The number of ROB writes -system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 210651 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048375 # Number of Instructions Simulated -system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated -system.cpu.cpi 0.500039 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500039 # CPI: Total CPI of All Threads -system.cpu.ipc 1.999843 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.999843 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769305779 # number of integer regfile reads -system.cpu.int_regfile_writes 232713829 # number of integer regfile writes -system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads -system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes -system.cpu.misc_regfile_reads 567370356 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes -system.cpu.icache.replacements 13908 # number of replacements -system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use -system.cpu.icache.total_refs 37470862 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15795 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2372.324280 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 499742506 # The number of ROB reads +system.cpu.rob.rob_writes 771826211 # The number of ROB writes +system.cpu.timesIdled 6299 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 210642 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273036725 # Number of Instructions Simulated +system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated +system.cpu.cpi 0.498628 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.498628 # CPI: Total CPI of All Threads +system.cpu.ipc 2.005503 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.005503 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1767787991 # number of integer regfile reads +system.cpu.int_regfile_writes 232574551 # number of integer regfile writes +system.cpu.fp_regfile_reads 188239368 # number of floating regfile reads +system.cpu.fp_regfile_writes 132566541 # number of floating regfile writes +system.cpu.misc_regfile_reads 566998882 # number of misc regfile reads +system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes +system.cpu.icache.replacements 13918 # number of replacements +system.cpu.icache.tagsinuse 1846.260886 # Cycle average of tags in use +system.cpu.icache.total_refs 37359528 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15804 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2363.928626 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1849.811927 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.903228 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.903228 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37470862 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37470862 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37470862 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits -system.cpu.icache.overall_hits::total 37470862 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17050 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17050 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17050 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17050 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17050 # number of overall misses -system.cpu.icache.overall_misses::total 17050 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 356620497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 356620497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 356620497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 356620497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 356620497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 356620497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37487912 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37487912 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37487912 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37487912 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37487912 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37487912 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20916.158182 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20916.158182 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1846.260886 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.901495 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.901495 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37359528 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37359528 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37359528 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37359528 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37359528 # number of overall hits +system.cpu.icache.overall_hits::total 37359528 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17066 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17066 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17066 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17066 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17066 # number of overall misses +system.cpu.icache.overall_misses::total 17066 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 359194498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 359194498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 359194498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 359194498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 359194498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 359194498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37376594 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37376594 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37376594 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37376594 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37376594 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37376594 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21047.374780 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21047.374780 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21047.374780 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21047.374780 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 550 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.947368 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1255 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1255 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1255 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1255 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1255 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1255 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15795 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15795 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15795 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15795 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 291702997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 291702997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 291702997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 291702997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 291702997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 291702997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18468.059323 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18468.059323 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1259 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1259 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1259 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1259 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1259 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1259 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15807 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15807 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15807 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15807 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15807 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15807 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293030998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 293030998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293030998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 293030998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293030998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 293030998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000423 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18538.052635 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18538.052635 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3959.582108 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5412 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.432003 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3947.622015 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13172 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.440163 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 367.644751 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2774.541575 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 817.395782 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011220 # 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mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993959 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993959 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356894 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356894 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36563.581380 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37980.273288 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37024.345511 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33736.643547 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33736.643547 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1414 # number of replacements -system.cpu.dcache.tagsinuse 3122.405384 # Cycle average of tags in use -system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1413 # number of replacements +system.cpu.dcache.tagsinuse 3109.588822 # Cycle average of tags in use +system.cpu.dcache.total_refs 170749767 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37038.995011 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3122.405384 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits -system.cpu.dcache.overall_hits::total 170846791 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3109.588822 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.759177 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.759177 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88696383 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88696383 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031533 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031533 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 170727916 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170727916 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170727916 # number of overall hits +system.cpu.dcache.overall_hits::total 170727916 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4041 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4041 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21132 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21132 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses -system.cpu.dcache.overall_misses::total 25149 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164690500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25173 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25173 # number of overall misses +system.cpu.dcache.overall_misses::total 25173 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 164980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 164980000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 832721164 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 832721164 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 996644664 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 996644664 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 996644664 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 996644664 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 997701164 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 997701164 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 997701164 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 997701164 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88700424 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88700424 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 170753089 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170753089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170753089 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170753089 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000183 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40826.528087 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40826.528087 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39405.695817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39405.695817 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39629.594179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39629.594179 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39633.780797 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39633.780797 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13427 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 430 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.225581 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks -system.cpu.dcache.writebacks::total 1040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks +system.cpu.dcache.writebacks::total 1039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2244 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2244 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18317 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18317 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211724000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211724000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211724000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211724000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20561 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20561 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20561 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20561 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1797 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1797 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2815 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2815 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80314500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 80314500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 132089500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 132089500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212404000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212404000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212404000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212404000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -844,14 +858,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44693.656093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44693.656093 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46923.445826 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46923.445826 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 4f910c5cd..3f51a9ebc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.624868 # Number of seconds simulated -sim_ticks 624867585500 # Number of ticks simulated -final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.625047 # Number of seconds simulated +sim_ticks 625047295000 # Number of ticks simulated +final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53257 # Simulator instruction rate (inst/s) -host_op_rate 72528 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24038469 # Simulator tick rate (ticks/s) -host_mem_usage 255596 # Number of bytes of host memory used -host_seconds 25994.48 # Real time elapsed on the host -sim_insts 1384379060 # Number of instructions simulated -sim_ops 1885333812 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242752 # Number of bytes read from this memory +host_inst_rate 94484 # Simulator instruction rate (inst/s) +host_op_rate 128674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42659692 # Simulator tick rate (ticks/s) +host_mem_usage 264788 # Number of bytes of host memory used +host_seconds 14651.94 # Real time elapsed on the host +sim_insts 1384370590 # Number of instructions simulated +sim_ops 1885325342 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155456 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2431 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472543 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 248987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48398657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48647644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248987 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248987 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6769869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6769869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6769869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48398657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55417514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 248711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48384947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48633657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6767923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6767923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6767923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48384947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55401580 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 474974 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545402 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 545412 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 30398336 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4330 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29545 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29734 # Track reads on a per bank basis +system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4340 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29731 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29790 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29857 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29627 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29624 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29606 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 4108 # Tr system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 624867514500 # Total gap between requests +system.physmem.totGap 625047219500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4330 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4340 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests -system.physmem.totBusLat 1899312000 # Total cycles spent in databus access -system.physmem.totBankLat 12874638000 # Total cycles spent in bank access -system.physmem.avgQLat 6984.13 # Average queueing delay per request -system.physmem.avgBankLat 27114.32 # Average bank access latency per request +system.physmem.totQLat 3340611483 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 18115671483 # Sum of mem lat for all requests +system.physmem.totBusLat 1899232000 # Total cycles spent in databus access +system.physmem.totBankLat 12875828000 # Total cycles spent in bank access +system.physmem.avgQLat 7035.71 # Average queueing delay per request +system.physmem.avgBankLat 27117.97 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38098.44 # Average memory access latency -system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 38153.68 # Average memory access latency +system.physmem.avgRdBW 48.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.63 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 17.43 # Average write queue length over time -system.physmem.readRowHits 249202 # Number of row buffer hits during reads -system.physmem.writeRowHits 48033 # Number of row buffer hits during writes -system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads +system.physmem.avgWrQLen 17.44 # Average write queue length over time +system.physmem.readRowHits 249146 # Number of row buffer hits during reads +system.physmem.writeRowHits 48036 # Number of row buffer hits during writes +system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes -system.physmem.avgGap 1154869.43 # Average gap between requests +system.physmem.avgGap 1155201.56 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,107 +235,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1249735172 # number of cpu cycles simulated +system.cpu.numCycles 1250094591 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 439117025 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 350578524 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 30630316 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 248764319 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 227490785 # Number of BTB hits +system.cpu.BPredUnit.lookups 438808047 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 349805436 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 30625316 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 249957064 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 227370417 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed -system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 52357585 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2806128 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 279728002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 600743262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 158308312 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133148695 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11515 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 333206369 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10414827 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1215386936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.589820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.189306 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 72457573 5.96% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42599927 3.51% 75.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31039765 2.55% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31697654 2.61% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614688205 50.58% 50.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42445352 3.49% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95116159 7.83% 61.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55675580 4.58% 66.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 72776602 5.99% 72.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42276531 3.48% 75.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31131234 2.56% 78.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31565180 2.60% 81.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 229712093 18.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44615078 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3041090435 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27022 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 127217578 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 972715984 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 490205592 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36288460 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40771047 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2804297042 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 31006 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2436370950 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13311855 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1215386936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.351020 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.829826 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 402796361 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 106301870 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561862491 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16807396 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 127618818 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44638184 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12819 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3046676123 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 127618818 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 438124604 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 35349497 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 425259 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 541326873 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72541885 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2975830632 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4806802 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56918075 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2945274289 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14167459331 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13596684512 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570774819 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 952134199 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23805 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 21281 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 197120926 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 972834043 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 492760757 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36385181 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 42690468 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2809386355 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28039 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2437787250 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13304140 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 911537771 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2374413817 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6655 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1215386936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.005770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875210 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132635579 10.92% 87.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 93723777 7.71% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37883178 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12361449 1.02% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 379434397 31.22% 31.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183109361 15.07% 46.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 202931100 16.70% 62.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 170113731 14.00% 76.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132526126 10.90% 87.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 93839529 7.72% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37911750 3.12% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12465689 1.03% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3055253 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1215386936 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 714674 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24388 0.03% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available @@ -363,322 +363,322 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55143304 62.90% 63.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31782308 36.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55116913 62.89% 63.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31779800 36.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1107294192 45.45% 45.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11224034 0.46% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502357 0.23% 46.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23404551 0.96% 47.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838357967 34.41% 81.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442336083 18.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1108876695 45.49% 45.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11224297 0.46% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502220 0.23% 46.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23416324 0.96% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838276108 34.39% 81.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442239839 18.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2436370950 # Type of FU issued -system.cpu.iq.rate 1.949510 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82717236 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56437909 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2460715459 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63320089 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84361835 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2437787250 # Type of FU issued +system.cpu.iq.rate 1.950082 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87635775 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035949 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6069393440 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3638225906 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2254362609 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122507911 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82793715 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56449336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2462106345 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63316680 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84343916 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341327109 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8250 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1428808 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 213208601 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341446862 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7743 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429272 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 215765460 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 221 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 127217578 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1558593 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2526 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1428808 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32521161 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1512713 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34033874 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2362219907 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792646926 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 74151043 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 127618818 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13752826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1562574 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2809426795 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1398231 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 972834043 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 492760757 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18053 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1558945 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1429272 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32529008 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1513965 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 34042973 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2363631235 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792642751 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 74156015 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12429 # number of nop insts executed -system.cpu.iew.exec_refs 1216288233 # number of memory reference insts executed -system.cpu.iew.exec_branches 322226431 # Number of branches executed -system.cpu.iew.exec_stores 423641307 # Number of stores executed -system.cpu.iew.exec_rate 1.890176 # Inst execution rate -system.cpu.iew.wb_sent 2335115057 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2309436326 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347701281 # num instructions producing a value -system.cpu.iew.wb_consumers 2523709653 # num instructions consuming a value +system.cpu.iew.exec_nop 12401 # number of nop insts executed +system.cpu.iew.exec_refs 1216279993 # number of memory reference insts executed +system.cpu.iew.exec_branches 322475744 # Number of branches executed +system.cpu.iew.exec_stores 423637242 # Number of stores executed +system.cpu.iew.exec_rate 1.890762 # Inst execution rate +system.cpu.iew.wb_sent 2336496726 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2310811945 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347866502 # num instructions producing a value +system.cpu.iew.wb_consumers 2524860722 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.847941 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534016 # average fanout of values written-back +system.cpu.iew.wb_rate 1.848510 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533838 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 918995782 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23078 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30617997 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1087855788 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.733083 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398277 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 924090552 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 30613261 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1087768118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.733215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398367 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 447553397 41.14% 41.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288592120 26.53% 67.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95115403 8.74% 76.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70228058 6.46% 82.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46464545 4.27% 87.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22184894 2.04% 89.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15849617 1.46% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10984656 1.01% 91.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90883098 8.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 447474994 41.14% 41.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288616071 26.53% 67.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95091930 8.74% 76.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70192926 6.45% 82.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46475898 4.27% 87.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22197093 2.04% 89.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15849951 1.46% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10985154 1.01% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884101 8.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1087855788 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390076 # Number of instructions committed -system.cpu.commit.committedOps 1885344828 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1087768118 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384381606 # Number of instructions committed +system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385866 # Number of memory references committed -system.cpu.commit.loads 631388875 # Number of loads committed +system.cpu.commit.refs 908382478 # Number of memory references committed +system.cpu.commit.loads 631387181 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299636089 # Number of branches committed +system.cpu.commit.branches 299634395 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705643 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90883098 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3801294955 # The number of ROB reads -system.cpu.rob.rob_writes 5735909866 # The number of ROB writes -system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379060 # Number of Instructions Simulated -system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated -system.cpu.cpi 0.902741 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.902741 # CPI: Total CPI of All Threads -system.cpu.ipc 1.107738 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.107738 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11770471325 # number of integer regfile reads -system.cpu.int_regfile_writes 2224868034 # number of integer regfile writes -system.cpu.fp_regfile_reads 68796296 # number of floating regfile reads -system.cpu.fp_regfile_writes 49549961 # number of floating regfile writes -system.cpu.misc_regfile_reads 1363964167 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776290 # number of misc regfile writes -system.cpu.icache.replacements 22546 # number of replacements -system.cpu.icache.tagsinuse 1642.542137 # Cycle average of tags in use -system.cpu.icache.total_refs 333790581 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24232 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13774.784624 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3806292582 # The number of ROB reads +system.cpu.rob.rob_writes 5746483501 # The number of ROB writes +system.cpu.timesIdled 353075 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34707655 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384370590 # Number of Instructions Simulated +system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated +system.cpu.cpi 0.903006 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.903006 # CPI: Total CPI of All Threads +system.cpu.ipc 1.107413 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.107413 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11775193288 # number of integer regfile reads +system.cpu.int_regfile_writes 2227107160 # number of integer regfile writes +system.cpu.fp_regfile_reads 68795849 # number of floating regfile reads +system.cpu.fp_regfile_writes 49561296 # number of floating regfile writes +system.cpu.misc_regfile_reads 1363965830 # number of misc regfile reads +system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes +system.cpu.icache.replacements 22468 # number of replacements +system.cpu.icache.tagsinuse 1641.255803 # Cycle average of tags in use +system.cpu.icache.total_refs 333171598 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24150 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13795.925383 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1642.542137 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.802023 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.802023 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 333794637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 333794637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 333794637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits -system.cpu.icache.overall_hits::total 333794637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses -system.cpu.icache.overall_misses::total 30837 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1641.255803 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.801394 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.801394 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 333175666 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 333175666 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 333175666 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 333175666 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 333175666 # number of overall hits +system.cpu.icache.overall_hits::total 333175666 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 30702 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 30702 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 30702 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 30702 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 30702 # number of overall misses +system.cpu.icache.overall_misses::total 30702 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 468488500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 468488500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 468488500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 468488500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 468488500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 468488500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333206368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333206368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333206368 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333206368 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333206368 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333206368 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15259.217641 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15259.217641 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15259.217641 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15259.217641 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1109 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 34.793103 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39.607143 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2210 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2210 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2210 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2210 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2210 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2210 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28492 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28492 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28492 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28492 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28492 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28492 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 377164000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 377164000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 377164000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 377164000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 377164000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 377164000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13237.540362 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13237.540362 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13237.540362 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13237.540362 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13237.540362 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13237.540362 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442193 # number of replacements -system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks. +system.cpu.l2cache.replacements 442192 # number of replacements +system.cpu.l2cache.tagsinuse 32688.738823 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1109575 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.336548 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.336242 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1294.928331 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 48.758922 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31344.836948 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039518 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.956569 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997575 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21799 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1058077 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1079876 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96322 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96322 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1295.493946 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 49.994068 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31343.250808 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001526 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2393684509 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2393684509 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96251295 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23110733226 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23206984521 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96251295 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23110733226 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23206984521 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274674 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999309 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999309 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304239 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304239 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39625.893372 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50968.210980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50900.833732 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36226.780310 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36226.780310 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532987 # number of replacements -system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use -system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits -system.cpu.dcache.overall_hits::total 969986101 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses +system.cpu.dcache.replacements 1532939 # number of replacements +system.cpu.dcache.tagsinuse 4094.623683 # Cycle average of tags in use +system.cpu.dcache.total_refs 970042937 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537035 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.113109 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 332181000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.623683 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999664 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 693909081 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693909081 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276100966 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276100966 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 970010047 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 970010047 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 970010047 # number of overall hits +system.cpu.dcache.overall_hits::total 970010047 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953320 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953320 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 834712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 834712 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses -system.cpu.dcache.overall_misses::total 2787983 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369162000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 67369162000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954940470 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39954940470 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 107324102470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 107324102470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 107324102470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 107324102470 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2788032 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2788032 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2788032 # number of overall misses +system.cpu.dcache.overall_misses::total 2788032 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 67394089000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 67394089000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39986185470 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39986185470 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 171500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 107380274470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 107380274470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 107380274470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 107380274470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695862401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695862401 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 972798079 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972798079 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972798079 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972798079 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34502.328855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34502.328855 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47904.169905 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47904.169905 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38514.720947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38514.720947 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2182 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 795 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 88 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.964286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9.034091 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks -system.cpu.dcache.writebacks::total 96322 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96308 # number of writebacks +system.cpu.dcache.writebacks::total 96308 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488800 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488800 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757854 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 757854 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1246654 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1246654 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1246654 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1246654 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464520 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464520 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76858 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76858 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541378 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541378 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541378 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541378 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37907812500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37907812500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3481886500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3481886500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41389699000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41389699000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41389699000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41389699000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25884.120736 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25884.120736 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45302.850712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45302.850712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 3a52f894e..145d86740 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026292 # Number of seconds simulated -sim_ticks 26292466000 # Number of ticks simulated -final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026275 # Number of seconds simulated +sim_ticks 26275145500 # Number of ticks simulated +final_tick 26275145500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43892 # Simulator instruction rate (inst/s) -host_op_rate 62284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16271073 # Simulator tick rate (ticks/s) -host_mem_usage 263196 # Number of bytes of host memory used -host_seconds 1615.90 # Real time elapsed on the host -sim_insts 70925094 # Number of instructions simulated -sim_ops 100644341 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11350476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302110574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 313461050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11350476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11350476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 204330472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 204330472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 204330472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11350476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302110574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 517791522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128777 # Total number of read requests seen -system.physmem.writeReqs 83943 # Total number of write requests seen -system.physmem.cpureqs 213018 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241664 # Total number of bytes read from memory -system.physmem.bytesWritten 5372352 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372352 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 298 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8167 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8037 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8195 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8177 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8060 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8008 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7983 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5171 # Track writes on a per bank basis +host_inst_rate 119366 # Simulator instruction rate (inst/s) +host_op_rate 169395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44231565 # Simulator tick rate (ticks/s) +host_mem_usage 271872 # Number of bytes of host memory used +host_seconds 594.04 # Real time elapsed on the host +sim_insts 70907629 # Number of instructions simulated +sim_ops 100626876 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128759 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11345779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302280495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 313626275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11345779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11345779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 204474910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 204474910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 204474910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11345779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302280495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 518101184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128759 # Total number of read requests seen +system.physmem.writeReqs 83947 # Total number of write requests seen +system.physmem.cpureqs 213029 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8240576 # Total number of bytes read from memory +system.physmem.bytesWritten 5372608 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8240576 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372608 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 323 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8094 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7897 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7989 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8151 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8058 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7986 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7982 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5173 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5231 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5234 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5372 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5371 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5150 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26292447500 # Total gap between requests +system.physmem.totGap 26275013500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128777 # Categorize read packet sizes +system.physmem.readPktSize::6 128759 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83943 # categorize write packet sizes +system.physmem.writePktSize::6 83947 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,13 +102,13 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 298 # categorize neither packet sizes +system.physmem.neitherpktsize::6 323 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,11 +138,11 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -154,44 +154,44 @@ system.physmem.wrQLenPdf::12 3650 # Wh system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4868163034 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests -system.physmem.totBusLat 515096000 # Total cycles spent in databus access -system.physmem.totBankLat 1373176000 # Total cycles spent in bank access -system.physmem.avgQLat 37803.93 # Average queueing delay per request -system.physmem.avgBankLat 10663.46 # Average bank access latency per request +system.physmem.totQLat 4891352059 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6777204059 # Sum of mem lat for all requests +system.physmem.totBusLat 515028000 # Total cycles spent in databus access +system.physmem.totBankLat 1370824000 # Total cycles spent in bank access +system.physmem.avgQLat 37989.02 # Average queueing delay per request +system.physmem.avgBankLat 10646.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52467.38 # Average memory access latency -system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 204.33 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52635.62 # Average memory access latency +system.physmem.avgRdBW 313.63 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 204.47 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 313.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 204.47 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.26 # Average read queue length over time -system.physmem.avgWrQLen 9.45 # Average write queue length over time -system.physmem.readRowHits 118938 # Number of row buffer hits during reads -system.physmem.writeRowHits 27082 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.34 # Average write queue length over time +system.physmem.readRowHits 118922 # Number of row buffer hits during reads +system.physmem.writeRowHits 27176 # Number of row buffer hits during writes system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.26 # Row buffer hit rate for writes -system.physmem.avgGap 123601.20 # Average gap between requests +system.physmem.writeRowHitRate 32.37 # Row buffer hit rate for writes +system.physmem.avgGap 123527.37 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,455 +235,455 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 52584933 # number of cpu cycles simulated +system.cpu.numCycles 52550292 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16605622 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12744819 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 601134 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10608037 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7769778 # Number of BTB hits +system.cpu.BPredUnit.lookups 16626972 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12763144 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 604576 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10780847 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7773827 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1825491 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 113784 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12554350 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85230964 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16626972 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9599318 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21200413 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2370934 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10497631 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11689041 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 183016 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 45992800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.594519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335814 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1463280 3.18% 70.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1379331 3.00% 73.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 959670 2.08% 75.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1190775 2.59% 78.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24812491 53.95% 53.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2139973 4.65% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1966955 4.28% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2042614 4.44% 67.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1467231 3.19% 70.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1381601 3.00% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 958651 2.08% 75.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1187660 2.58% 78.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10035624 21.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3326611 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104659 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116720432 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 360894 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19086496 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29582757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22430841 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3912004 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4391398 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111440700 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41006 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107204361 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269260 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 45992800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316401 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.621893 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14631573 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8854890 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19476912 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1392472 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1636953 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3331046 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104815 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116877182 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363170 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1636953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16335988 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2535467 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 864548 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19115469 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5504375 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114992065 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17001 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4650627 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 317 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115303250 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529787373 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529782097 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5276 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 16170578 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20502 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20496 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13002691 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29626313 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22450124 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3876856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4338192 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111565223 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36031 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107269202 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 275818 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10829565 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25919062 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2245 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 45992800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.332304 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990217 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5412181 11.75% 84.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3900032 8.47% 92.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1833850 3.98% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 869462 1.89% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10779099 23.44% 23.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8049451 17.50% 40.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7422892 16.14% 57.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7126081 15.49% 72.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5395767 11.73% 84.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3928809 8.54% 92.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1841047 4.00% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 874903 1.90% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 574751 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 45992800 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1351687 54.87% 59.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1001007 40.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 114108 4.61% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1356583 54.78% 59.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1005840 40.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56616683 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91709 0.09% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 161 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28875176 26.93% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21620625 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56641700 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91676 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 165 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28901726 26.94% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21633928 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107204361 # Type of FU issued -system.cpu.iq.rate 2.038690 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 696 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 107269202 # Type of FU issued +system.cpu.iq.rate 2.041267 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2476532 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023087 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263283068 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122458972 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105581252 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 486 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 768 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109667441 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2181528 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 109745491 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2188417 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2272156 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6578 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29396 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1871610 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2319205 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6776 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29966 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1894386 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 28 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 493 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 503 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1617500 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6480 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5483 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29396 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 390184 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 182395 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 572579 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106179962 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28578383 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1024399 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1636953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1044060 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45930 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111611011 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 291580 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29626313 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22450124 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20111 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6644 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5462 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29966 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393316 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181236 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 574552 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106238160 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28602099 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1031042 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9804 # number of nop insts executed -system.cpu.iew.exec_refs 49916161 # number of memory reference insts executed -system.cpu.iew.exec_branches 14598129 # Number of branches executed -system.cpu.iew.exec_stores 21337778 # Number of stores executed -system.cpu.iew.exec_rate 2.019209 # Inst execution rate -system.cpu.iew.wb_sent 105751543 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105534073 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53248858 # num instructions producing a value -system.cpu.iew.wb_consumers 103476528 # num instructions consuming a value +system.cpu.iew.exec_nop 9757 # number of nop insts executed +system.cpu.iew.exec_refs 49948126 # number of memory reference insts executed +system.cpu.iew.exec_branches 14604066 # Number of branches executed +system.cpu.iew.exec_stores 21346027 # Number of stores executed +system.cpu.iew.exec_rate 2.021647 # Inst execution rate +system.cpu.iew.wb_sent 105801461 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105581404 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53258894 # num instructions producing a value +system.cpu.iew.wb_consumers 103486689 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.006926 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514598 # average fanout of values written-back +system.cpu.iew.wb_rate 2.009150 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514645 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 10979497 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 501718 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44355847 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.268752 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.766108 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1877627 4.23% 79.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1953879 4.40% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 688656 1.55% 85.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 567495 1.28% 86.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15312059 34.52% 34.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11621987 26.20% 60.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3450685 7.78% 68.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2867250 6.46% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1878784 4.24% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1958737 4.42% 83.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685559 1.55% 85.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 561142 1.27% 86.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6019644 13.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70930646 # Number of instructions committed -system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44355847 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70913181 # Number of instructions committed +system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869832 # Number of memory references committed -system.cpu.commit.loads 27310601 # Number of loads committed +system.cpu.commit.refs 47862846 # Number of memory references committed +system.cpu.commit.loads 27307108 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744998 # Number of branches committed +system.cpu.commit.branches 13741505 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486751 # Number of committed integer instructions. +system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6019644 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149890856 # The number of ROB reads -system.cpu.rob.rob_writes 224611140 # The number of ROB writes -system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70925094 # Number of Instructions Simulated -system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated -system.cpu.cpi 0.741415 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.741415 # CPI: Total CPI of All Threads -system.cpu.ipc 1.348772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.348772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511431338 # number of integer regfile reads -system.cpu.int_regfile_writes 103318196 # number of integer regfile writes -system.cpu.fp_regfile_reads 686 # number of floating regfile reads -system.cpu.fp_regfile_writes 582 # number of floating regfile writes -system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads -system.cpu.misc_regfile_writes 38826 # number of misc regfile writes -system.cpu.icache.replacements 30543 # number of replacements -system.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use -system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 149922829 # The number of ROB reads +system.cpu.rob.rob_writes 224870236 # The number of ROB writes +system.cpu.timesIdled 74082 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6557492 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70907629 # Number of Instructions Simulated +system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated +system.cpu.cpi 0.741109 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.741109 # CPI: Total CPI of All Threads +system.cpu.ipc 1.349329 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.349329 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511669135 # number of integer regfile reads +system.cpu.int_regfile_writes 103349973 # number of integer regfile writes +system.cpu.fp_regfile_reads 690 # number of floating regfile reads +system.cpu.fp_regfile_writes 602 # number of floating regfile writes +system.cpu.misc_regfile_reads 49186281 # number of misc regfile reads +system.cpu.misc_regfile_writes 31840 # number of misc regfile writes +system.cpu.icache.replacements 29504 # number of replacements +system.cpu.icache.tagsinuse 1815.541660 # Cycle average of tags in use +system.cpu.icache.total_refs 11653533 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 31535 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 369.542825 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11635567 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11635567 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits -system.cpu.icache.overall_hits::total 11635567 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses -system.cpu.icache.overall_misses::total 36658 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 709083999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 709083999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11672225 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11672225 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11672225 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11672225 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11672225 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11672225 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19343.226554 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19343.226554 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1815.541660 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.886495 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.886495 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11653539 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11653539 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11653539 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11653539 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11653539 # number of overall hits +system.cpu.icache.overall_hits::total 11653539 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35502 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35502 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35502 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35502 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35502 # number of overall misses +system.cpu.icache.overall_misses::total 35502 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 704211999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 704211999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 704211999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 704211999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 704211999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 704211999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11689041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11689041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11689041 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11689041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11689041 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11689041 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003037 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003037 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003037 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003037 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003037 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003037 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19835.840206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19835.840206 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19835.840206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19835.840206 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 96.590909 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580605499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 580605499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580605499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 580605499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580605499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 580605499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3638 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3638 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3638 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3638 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3638 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3638 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31864 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31864 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31864 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31864 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31864 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31864 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 575585499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 575585499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 575585499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 575585499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 575585499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 575585499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002726 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002726 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002726 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18063.818071 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18063.818071 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18063.818071 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18063.818071 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18063.818071 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18063.818071 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95650 # number of replacements -system.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use -system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 95629 # number of replacements +system.cpu.l2cache.tagsinuse 30144.051156 # Cycle average of tags in use +system.cpu.l2cache.total_refs 89024 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 126742 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.702403 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.820340 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.042099 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.057268 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.919707 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27693 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33453 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 61146 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129052 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8421267207 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.940063 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.940063 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955360 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955360 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.661158 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45065.060892 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.512575 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8227454893 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8443777804 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394097 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305382 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.949853 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.949853 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955504 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955504 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.148557 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66982.456844 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66982.456844 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158306 # number of replacements -system.cpu.dcache.tagsinuse 4072.986678 # Cycle average of tags in use -system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.986678 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits -system.cpu.dcache.overall_hits::total 44303188 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses -system.cpu.dcache.overall_misses::total 1709363 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670086500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4670086500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 124709259481 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 124709259481 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 124709259481 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 124709259481 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 158352 # number of replacements +system.cpu.dcache.tagsinuse 4073.285602 # Cycle average of tags in use +system.cpu.dcache.total_refs 44355767 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162448 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.045941 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 278219000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4073.285602 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994454 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994454 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26058145 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26058145 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18265070 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18265070 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15998 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44323215 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44323215 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44323215 # number of overall hits +system.cpu.dcache.overall_hits::total 44323215 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124984 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124984 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1584831 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1584831 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1709815 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1709815 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1709815 # number of overall misses +system.cpu.dcache.overall_misses::total 1709815 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4634379500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4634379500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 120528782979 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 120528782979 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 848000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 848000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 125163162479 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 125163162479 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 125163162479 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 125163162479 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26183129 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26183129 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.307299 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.307299 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72956.568898 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72956.568898 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16039 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16039 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46033030 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46033030 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46033030 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46033030 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004773 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004773 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002556 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002556 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037143 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037143 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037143 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037143 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37079.782212 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37079.782212 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76051.505163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76051.505163 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20682.926829 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20682.926829 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73202.751455 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73202.751455 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3167 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 649 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.784173 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 43.266667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks -system.cpu.dcache.writebacks::total 129052 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060279000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060279000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313871492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10313871492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313871492 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129085 # number of writebacks +system.cpu.dcache.writebacks::total 129085 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69523 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69523 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1477505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1547028 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1547028 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1547028 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1547028 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55461 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55461 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107326 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107326 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162787 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162787 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162787 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162787 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2049044000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2049044000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8282203488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8282203488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10331247488 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10331247488 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10331247488 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10331247488 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36945.673536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36945.673536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77168.658927 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77168.658927 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 95290563f..dd9ca10a0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.506577 # Number of seconds simulated -sim_ticks 506577346000 # Number of ticks simulated -final_tick 506577346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.506354 # Number of seconds simulated +sim_ticks 506353996500 # Number of ticks simulated +final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78526 # Simulator instruction rate (inst/s) -host_op_rate 87602 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25754624 # Simulator tick rate (ticks/s) -host_mem_usage 525748 # Number of bytes of host memory used -host_seconds 19669.37 # Real time elapsed on the host -sim_insts 1544563048 # Number of instructions simulated -sim_ops 1723073860 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143709504 # Number of bytes read from this memory -system.physmem.bytes_read::total 143757376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70427136 # Number of bytes written to this memory -system.physmem.bytes_written::total 70427136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245461 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246209 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100424 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100424 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283687190 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 283781691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94501 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94501 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 139025435 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 139025435 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 139025435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283687190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 422807126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246209 # Total number of read requests seen -system.physmem.writeReqs 1100424 # Total number of write requests seen -system.physmem.cpureqs 3346633 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143757376 # Total number of bytes read from memory -system.physmem.bytesWritten 70427136 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143757376 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70427136 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 648 # Number of read reqs serviced by write Q +host_inst_rate 136322 # Simulator instruction rate (inst/s) +host_op_rate 152077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44690362 # Simulator tick rate (ticks/s) +host_mem_usage 507940 # Number of bytes of host memory used +host_seconds 11330.27 # Real time elapsed on the host +sim_insts 1544563023 # Number of instructions simulated +sim_ops 1723073835 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143771904 # Number of bytes read from this memory +system.physmem.bytes_read::total 143819904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70451968 # Number of bytes written to this memory +system.physmem.bytes_written::total 70451968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246436 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2247186 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100812 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100812 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283935557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 284030352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 139135799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 139135799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 139135799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283935557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 423166152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2247186 # Total number of read requests seen +system.physmem.writeReqs 1100812 # Total number of write requests seen +system.physmem.cpureqs 3347998 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143819904 # Total number of bytes read from memory +system.physmem.bytesWritten 70451968 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143819904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70451968 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 672 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139859 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 143718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 137951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140151 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141411 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 141047 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 141131 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 139616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 136994 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 141023 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 138860 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 140030 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 70316 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 68829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 67740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68489 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 68246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 68330 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 68656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 68488 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 67093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70319 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69051 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68913 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139825 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 143804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141798 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 137923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140335 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 141349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 139500 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 137255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 141125 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 138862 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 139997 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69198 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 70413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69591 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 68873 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 67768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68429 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 68697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68477 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 68286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 68308 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 68629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 68528 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 67273 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70384 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68935 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 506577272500 # Total gap between requests +system.physmem.totGap 506353933500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246209 # Categorize read packet sizes +system.physmem.readPktSize::6 2247186 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1100424 # categorize write packet sizes +system.physmem.writePktSize::6 1100812 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1577632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 445457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 156427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 66028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1577555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 446581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 156376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 65982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 27034566792 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102738360792 # Sum of mem lat for all requests -system.physmem.totBusLat 8982244000 # Total cycles spent in databus access -system.physmem.totBankLat 66721550000 # Total cycles spent in bank access -system.physmem.avgQLat 12039.11 # Average queueing delay per request -system.physmem.avgBankLat 29712.64 # Average bank access latency per request +system.physmem.totQLat 27009597750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102747541750 # Sum of mem lat for all requests +system.physmem.totBusLat 8986056000 # Total cycles spent in databus access +system.physmem.totBankLat 66751888000 # Total cycles spent in bank access +system.physmem.avgQLat 12022.89 # Average queueing delay per request +system.physmem.avgBankLat 29713.54 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45751.76 # Average memory access latency -system.physmem.avgRdBW 283.78 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 139.03 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 283.78 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 139.03 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 45736.44 # Average memory access latency +system.physmem.avgRdBW 284.03 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 139.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 284.03 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 139.14 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.64 # Data bus utilization in percentage system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 10.83 # Average write queue length over time -system.physmem.readRowHits 914455 # Number of row buffer hits during reads -system.physmem.writeRowHits 188951 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads +system.physmem.avgWrQLen 11.52 # Average write queue length over time +system.physmem.readRowHits 914505 # Number of row buffer hits during reads +system.physmem.writeRowHits 189005 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes -system.physmem.avgGap 151369.23 # Average gap between requests +system.physmem.avgGap 151240.81 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,140 +235,140 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1013154693 # number of cpu cycles simulated +system.cpu.numCycles 1012707994 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 302078234 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248282516 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 15228940 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 174133457 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 160366522 # Number of BTB hits +system.cpu.BPredUnit.lookups 301930111 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248173247 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 15201095 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 171785530 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 160276899 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 17581353 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 196 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 296396923 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2177678223 # Number of instructions fetch has processed -system.cpu.fetch.Branches 302078234 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 177947875 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433295900 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 86556891 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 152970163 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 65 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 286931136 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5530103 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 951710373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.532755 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215871 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 17551988 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed +system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 177828887 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433076308 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 86433742 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 153009166 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 286734480 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5522368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 951217236 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.532975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216056 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 518414544 54.47% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25023553 2.63% 57.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39078902 4.11% 61.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48295865 5.07% 66.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42590853 4.48% 70.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46358394 4.87% 75.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38409844 4.04% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18541861 1.95% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174996557 18.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 518141000 54.47% 54.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25031243 2.63% 57.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39020791 4.10% 61.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48260411 5.07% 66.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 42551008 4.47% 70.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46329866 4.87% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38408585 4.04% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18543654 1.95% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174930678 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 951710373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298156 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.149403 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327700398 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 131274030 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403657963 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20031323 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69046659 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46033752 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2358943633 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2468 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69046659 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 350846153 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61254563 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16168 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 399028257 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71518573 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2298097948 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 126905 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5030989 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58378290 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 21 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2273047323 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10612493947 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10612490107 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3840 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 566727353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 579 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158294547 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 623264205 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220545745 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86083879 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71111807 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2197176983 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 617 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016362984 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3976433 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 469561245 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1109303126 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 442 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 951710373 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.118673 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906088 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 951217236 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.298141 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.149522 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327471231 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 131306156 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403441377 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20045518 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68952954 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46012127 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2358019040 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68952954 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 350612417 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61250936 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16584 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 398830274 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71554071 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2297211554 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 127534 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5036199 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58405264 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2272168650 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10608574023 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10608571065 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2958 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 565848720 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 852 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158388501 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 623121269 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220470896 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86042540 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70771050 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2196546407 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 888 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016009796 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3969588 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 468927262 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1107841980 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 718 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 951217236 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.119400 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 271681104 28.55% 28.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151029292 15.87% 44.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160860951 16.90% 61.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119423719 12.55% 73.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124040655 13.03% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73844505 7.76% 94.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38423887 4.04% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9837914 1.03% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2568346 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 271448438 28.54% 28.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 150881497 15.86% 44.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160823100 16.91% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119315575 12.54% 73.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124031902 13.04% 86.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73881034 7.77% 94.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38429694 4.04% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9823536 1.03% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2582460 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 951710373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 951217236 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 884251 3.71% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5803 0.02% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18260912 76.52% 80.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4713024 19.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 875964 3.67% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5764 0.02% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18242361 76.45% 80.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4736544 19.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1235730188 61.29% 61.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925294 0.05% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235492979 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925544 0.05% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued @@ -390,164 +390,164 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 40 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 27 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 13 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 586669934 29.10% 90.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193037461 9.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 586540633 29.09% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193050569 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016362984 # Type of FU issued -system.cpu.iq.rate 1.990183 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23863990 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011835 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5012276382 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2666928163 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1956898360 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 382 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 744 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2040226783 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 191 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64738379 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016009796 # Type of FU issued +system.cpu.iq.rate 1.990712 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23860633 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011836 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5011066759 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2665664471 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1956606463 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 290 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2039870285 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64705720 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 137337431 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 268034 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192473 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45698695 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 137194500 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 273797 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192943 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45623851 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3808296 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 3807412 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69046659 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27170871 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1494320 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2197177695 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6112052 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 623264205 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220545745 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 552 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 473344 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 89494 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192473 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8164015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9611639 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17775654 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986719031 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573114745 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29643953 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68952954 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27155997 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1495704 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2196547422 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6100181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 623121269 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220470896 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 826 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 473871 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 90052 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192943 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8142096 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9608050 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17750146 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986410888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573023734 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29598908 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 95 # number of nop insts executed -system.cpu.iew.exec_refs 763276448 # number of memory reference insts executed -system.cpu.iew.exec_branches 238352176 # Number of branches executed -system.cpu.iew.exec_stores 190161703 # Number of stores executed -system.cpu.iew.exec_rate 1.960924 # Inst execution rate -system.cpu.iew.wb_sent 1965347769 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1956898514 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295796153 # num instructions producing a value -system.cpu.iew.wb_consumers 2060480328 # num instructions consuming a value +system.cpu.iew.exec_nop 127 # number of nop insts executed +system.cpu.iew.exec_refs 763190345 # number of memory reference insts executed +system.cpu.iew.exec_branches 238305534 # Number of branches executed +system.cpu.iew.exec_stores 190166611 # Number of stores executed +system.cpu.iew.exec_rate 1.961484 # Inst execution rate +system.cpu.iew.wb_sent 1965043499 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1956606576 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295701772 # num instructions producing a value +system.cpu.iew.wb_consumers 2060221208 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.931490 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628881 # average fanout of values written-back +system.cpu.iew.wb_rate 1.932054 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628914 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 474201695 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 175 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15228277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882663714 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.952130 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.732822 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 473572340 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15200427 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882264282 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.953013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.733344 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 395325741 44.79% 44.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192113195 21.77% 66.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72479892 8.21% 74.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35250909 3.99% 78.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18971392 2.15% 80.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30754959 3.48% 84.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20068273 2.27% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11416653 1.29% 87.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106282700 12.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 395036396 44.78% 44.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 191994213 21.76% 66.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72477507 8.21% 74.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35260039 4.00% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18947912 2.15% 80.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30765236 3.49% 84.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20067867 2.27% 86.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11401417 1.29% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106313695 12.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882663714 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563066 # Number of instructions committed -system.cpu.commit.committedOps 1723073878 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 882264282 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563041 # Number of instructions committed +system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773824 # Number of memory references committed -system.cpu.commit.loads 485926774 # Number of loads committed +system.cpu.commit.refs 660773814 # Number of memory references committed +system.cpu.commit.loads 485926769 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462431 # Number of branches committed +system.cpu.commit.branches 213462426 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941861 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106282700 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106313695 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2973655988 # The number of ROB reads -system.cpu.rob.rob_writes 4463745378 # The number of ROB writes -system.cpu.timesIdled 1007703 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61444320 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563048 # Number of Instructions Simulated -system.cpu.committedOps 1723073860 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563048 # Number of Instructions Simulated -system.cpu.cpi 0.655949 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.655949 # CPI: Total CPI of All Threads -system.cpu.ipc 1.524509 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.524509 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9950552971 # number of integer regfile reads -system.cpu.int_regfile_writes 1936868290 # number of integer regfile writes -system.cpu.fp_regfile_reads 164 # number of floating regfile reads -system.cpu.fp_regfile_writes 170 # number of floating regfile writes -system.cpu.misc_regfile_reads 737621516 # number of misc regfile reads -system.cpu.misc_regfile_writes 134 # number of misc regfile writes +system.cpu.rob.rob_reads 2972596181 # The number of ROB reads +system.cpu.rob.rob_writes 4462393115 # The number of ROB writes +system.cpu.timesIdled 1008109 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61490758 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563023 # Number of Instructions Simulated +system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated +system.cpu.cpi 0.655660 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.655660 # CPI: Total CPI of All Threads +system.cpu.ipc 1.525181 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.525181 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9949148949 # number of integer regfile reads +system.cpu.int_regfile_writes 1936492974 # number of integer regfile writes +system.cpu.fp_regfile_reads 113 # number of floating regfile reads +system.cpu.fp_regfile_writes 115 # number of floating regfile writes +system.cpu.misc_regfile_reads 737540247 # number of misc regfile reads +system.cpu.misc_regfile_writes 124 # number of misc regfile writes system.cpu.icache.replacements 23 # number of replacements -system.cpu.icache.tagsinuse 625.920238 # Cycle average of tags in use -system.cpu.icache.total_refs 286929961 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 368331.143774 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 625.185145 # Cycle average of tags in use +system.cpu.icache.total_refs 286733320 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 778 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 368551.825193 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.920238 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305625 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305625 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 286929961 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286929961 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286929961 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286929961 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286929961 # number of overall hits -system.cpu.icache.overall_hits::total 286929961 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1175 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1175 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1175 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1175 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1175 # number of overall misses -system.cpu.icache.overall_misses::total 1175 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61332500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61332500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61332500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61332500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61332500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61332500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286931136 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286931136 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286931136 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286931136 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286931136 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286931136 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 625.185145 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305266 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305266 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 286733320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 286733320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 286733320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 286733320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 286733320 # number of overall hits +system.cpu.icache.overall_hits::total 286733320 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1160 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1160 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1160 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1160 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1160 # number of overall misses +system.cpu.icache.overall_misses::total 1160 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59910000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59910000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59910000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59910000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59910000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59910000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 286734480 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 286734480 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 286734480 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 286734480 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 286734480 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 286734480 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52197.872340 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52197.872340 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52197.872340 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52197.872340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52197.872340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52197.872340 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51646.551724 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51646.551724 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51646.551724 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51646.551724 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -556,120 +556,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 69 system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 748 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419071 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1419819 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826390 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 826390 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 748 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2245461 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2246209 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 748 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2245461 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2246209 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32066173 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80158804465 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80190870638 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48314626333 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48314626333 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32066173 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128473430798 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 128505496971 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32066173 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128473430798 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 128505496971 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184107 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184186 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233868 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233868 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233926 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42869.215241 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56486.817407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56479.643277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58464.679308 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58464.679308 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42869.215241 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57214.723746 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57209.946613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42869.215241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57214.723746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57209.946613 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 750 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1420496 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826690 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826690 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 750 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2246436 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2247186 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 750 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2246436 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2247186 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32919184 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80176207714 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80209126898 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48315790009 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48315790009 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32919184 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128491997723 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 128524916907 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32919184 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128491997723 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 128524916907 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184166 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184245 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436614 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436614 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.234003 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.234003 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43892.245333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56472.219477 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56465.577445 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58444.870519 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58444.870519 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9597327 # number of replacements -system.cpu.dcache.tagsinuse 4087.938249 # Cycle average of tags in use -system.cpu.dcache.total_refs 656067317 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9601423 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.330217 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9598379 # number of replacements +system.cpu.dcache.tagsinuse 4087.934747 # Cycle average of tags in use +system.cpu.dcache.total_refs 656008169 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9602475 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.316571 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 3424422000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.938249 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998032 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998032 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 489013498 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489013498 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167053663 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167053663 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 90 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 90 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 66 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 66 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656067161 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656067161 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656067161 # number of overall hits -system.cpu.dcache.overall_hits::total 656067161 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11472935 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11472935 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5532384 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5532384 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 4087.934747 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 488954223 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 488954223 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167053823 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167053823 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 656008046 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656008046 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656008046 # number of overall hits +system.cpu.dcache.overall_hits::total 656008046 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11476242 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11476242 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5532224 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5532224 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17005319 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17005319 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17005319 # number of overall misses -system.cpu.dcache.overall_misses::total 17005319 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 299507112500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 299507112500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 217112545758 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 217112545758 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 516619658258 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 516619658258 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 516619658258 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 516619658258 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500486433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500486433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17008466 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17008466 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17008466 # number of overall misses +system.cpu.dcache.overall_misses::total 17008466 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 299283762000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 299283762000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 216949721927 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 216949721927 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 516233483927 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 516233483927 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 516233483927 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 516233483927 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500430465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500430465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 93 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 93 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 66 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 66 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673072480 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673072480 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673072480 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673072480 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022924 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022924 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032056 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032056 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032258 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.032258 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025265 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025265 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025265 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025265 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26105.535550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26105.535550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39243.940001 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39243.940001 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30379.886332 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30379.886332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30379.886332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30379.886332 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19797443 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 993226 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1172557 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.883992 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15.388594 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 673016512 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673016512 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673016512 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673016512 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032055 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032055 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025272 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025272 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025272 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025272 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26078.550975 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26078.550975 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39215.643099 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39215.643099 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30351.560448 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30351.560448 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19781174 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 987477 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1172505 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64541 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.870865 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.299995 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781738 # number of writebacks -system.cpu.dcache.writebacks::total 3781738 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3765084 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3765084 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638812 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3638812 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781550 # number of writebacks +system.cpu.dcache.writebacks::total 3781550 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767179 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3767179 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638811 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3638811 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7403896 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7403896 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7403896 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7403896 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707851 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707851 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893572 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893572 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601423 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601423 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601423 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601423 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170518232500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 170518232500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71841286448 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71841286448 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242359518948 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 242359518948 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242359518948 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 242359518948 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22122.668497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22122.668497 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37939.558912 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37939.558912 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.041617 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.041617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.041617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.041617 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 7405990 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7405990 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7405990 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7405990 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709063 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7709063 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893413 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893413 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602476 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602476 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602476 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602476 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170550521000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 170550521000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71842126604 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71842126604 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242392647604 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 242392647604 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242392647604 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 242392647604 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22123.378808 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22123.378808 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37943.188625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37943.188625 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 9ba7feff2..8c8f70dab 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074245 # Number of seconds simulated -sim_ticks 74245032000 # Number of ticks simulated -final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074149 # Number of seconds simulated +sim_ticks 74148853000 # Number of ticks simulated +final_tick 74148853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44193 # Simulator instruction rate (inst/s) -host_op_rate 48386 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19039219 # Simulator tick rate (ticks/s) -host_mem_usage 236076 # Number of bytes of host memory used -host_seconds 3899.58 # Real time elapsed on the host -sim_insts 172333441 # Number of instructions simulated -sim_ops 188686923 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory -system.physmem.bytes_read::total 242688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131008 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2047 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3792 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1764536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1504208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3268744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1764536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1764536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1764536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1504208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3268744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3793 # Total number of read requests seen +host_inst_rate 112590 # Simulator instruction rate (inst/s) +host_op_rate 123276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48451809 # Simulator tick rate (ticks/s) +host_mem_usage 247684 # Number of bytes of host memory used +host_seconds 1530.36 # Real time elapsed on the host +sim_insts 172303021 # Number of instructions simulated +sim_ops 188656503 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 131648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111744 # Number of bytes read from this memory +system.physmem.bytes_read::total 243392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131648 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2057 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3803 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1775456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1507023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3282478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1775456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1775456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1775456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1507023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3282478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3804 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3795 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 242688 # Total number of bytes read from memory +system.physmem.cpureqs 3804 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 243392 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 242688 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 243392 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 191 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 190 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 235 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 242 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 243 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 179 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 239 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74245013500 # Total gap between requests +system.physmem.totGap 74148834500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3793 # Categorize read packet sizes +system.physmem.readPktSize::6 3804 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,14 +95,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 2 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 2791 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 12368785 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests -system.physmem.totBusLat 15172000 # Total cycles spent in databus access -system.physmem.totBankLat 58828000 # Total cycles spent in bank access -system.physmem.avgQLat 3260.95 # Average queueing delay per request -system.physmem.avgBankLat 15509.62 # Average bank access latency per request +system.physmem.totQLat 11954297 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86040297 # Sum of mem lat for all requests +system.physmem.totBusLat 15216000 # Total cycles spent in databus access +system.physmem.totBankLat 58870000 # Total cycles spent in bank access +system.physmem.avgQLat 3142.56 # Average queueing delay per request +system.physmem.avgBankLat 15475.81 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22770.57 # Average memory access latency -system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22618.37 # Average memory access latency +system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3295 # Number of row buffer hits during reads +system.physmem.readRowHits 3306 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads +system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19574219.22 # Average gap between requests +system.physmem.avgGap 19492332.94 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,143 +228,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148490065 # number of cpu cycles simulated +system.cpu.numCycles 148297707 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 94824011 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 74811084 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6283419 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 44691419 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 43068728 # Number of BTB hits +system.cpu.BPredUnit.lookups 94799058 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74801869 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6279291 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 44724397 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 43048437 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4355507 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 88338 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39650853 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380235632 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94799058 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47403944 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80363745 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27281096 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7190522 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5914 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36846162 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1830987 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148197153 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153253 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8658719 5.84% 69.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6556174 4.42% 73.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6250200 4.21% 77.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8011886 5.40% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68002614 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5258973 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10529156 7.10% 56.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10279296 6.94% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8665155 5.85% 69.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6547882 4.42% 73.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6243481 4.21% 77.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8012637 5.41% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24657959 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14343881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164426 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392938907 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 736414 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20843724 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43027461 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16443523 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5668310 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3691413 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329308816 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 54643 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249531465 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 795533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148197153 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.639248 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.564002 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45504222 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5859124 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74799977 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1201103 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20832727 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14326960 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164415 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392837219 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 734618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20832727 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50888432 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 722612 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 592441 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70554465 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4606476 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371355589 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 339881 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3653545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631848996 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581867929 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1564559444 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17308485 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 333804857 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25175 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25171 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13001756 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43004891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16418786 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5685881 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3634471 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329217927 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47188 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249444233 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 790071 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139538270 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362161071 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1972 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148197153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12554169 8.46% 92.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6514357 4.39% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4035019 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1109043 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56041941 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22617532 15.26% 53.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24819018 16.75% 69.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20330052 13.72% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12543560 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6522981 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4027974 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1111240 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182855 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148197153 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1162967 46.43% 85.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 373557 14.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 964308 38.46% 38.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5601 0.22% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1163168 46.39% 85.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 374037 14.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194943196 78.12% 78.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 980225 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194888705 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979440 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -383,295 +383,289 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33090 0.01% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164479 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254525 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76418 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465710 0.19% 78.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206458 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38372441 15.38% 94.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13962748 5.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33084 0.01% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164341 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254530 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76430 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465703 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38355599 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13947826 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249531465 # Type of FU issued -system.cpu.iq.rate 1.680459 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2189794 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1841578 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250160112 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1876275 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2013222 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249444233 # Type of FU issued +system.cpu.iq.rate 1.682051 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2507262 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010051 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646645921 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466634028 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237875698 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737031 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2187759 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841461 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250076224 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875271 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2007740 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13171893 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11381 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18785 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3792805 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13155407 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11336 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18867 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3774152 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 96 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 95 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20843724 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 209 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18785 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3890771 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3762289 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7653060 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 243027736 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36864796 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6503729 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20832727 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16956 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 865 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329282292 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 783571 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43004891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16418786 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24780 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 273 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18867 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3889474 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3759056 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7648530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242951850 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36852953 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6492383 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 16968 # number of nop insts executed -system.cpu.iew.exec_refs 50523279 # number of memory reference insts executed -system.cpu.iew.exec_branches 53444477 # Number of branches executed -system.cpu.iew.exec_stores 13658483 # Number of stores executed -system.cpu.iew.exec_rate 1.636660 # Inst execution rate -system.cpu.iew.wb_sent 240848315 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239789364 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148488630 # num instructions producing a value -system.cpu.iew.wb_consumers 267300896 # num instructions consuming a value +system.cpu.iew.exec_nop 17177 # number of nop insts executed +system.cpu.iew.exec_refs 50499895 # number of memory reference insts executed +system.cpu.iew.exec_branches 53421871 # Number of branches executed +system.cpu.iew.exec_stores 13646942 # Number of stores executed +system.cpu.iew.exec_rate 1.638271 # Inst execution rate +system.cpu.iew.wb_sent 240774594 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239717159 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148465347 # num instructions producing a value +system.cpu.iew.wb_consumers 267264848 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.614851 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555511 # average fanout of values written-back +system.cpu.iew.wb_rate 1.616459 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555499 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140679091 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51300 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6130085 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127544650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.479492 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.184685 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 140611386 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6125994 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127364426 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481347 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186226 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57798190 45.32% 45.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31737959 24.88% 70.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13785979 10.81% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7635406 5.99% 87.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4383857 3.44% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1319533 1.03% 91.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1705049 1.34% 92.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1307627 1.03% 93.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7871050 6.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57685030 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31666758 24.86% 70.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13788542 10.83% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7634444 5.99% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4378206 3.44% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321179 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1702157 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1312824 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7875286 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127544650 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347829 # Number of instructions committed -system.cpu.commit.committedOps 188701311 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 127364426 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172317409 # Number of instructions committed +system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506286 # Number of memory references committed -system.cpu.commit.loads 29855568 # Number of loads committed +system.cpu.commit.refs 42494118 # Number of memory references committed +system.cpu.commit.loads 29849484 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306395 # Number of branches committed +system.cpu.commit.branches 40300311 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130553 # Number of committed integer instructions. +system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7871050 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7875286 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 449048801 # The number of ROB reads -system.cpu.rob.rob_writes 679713725 # The number of ROB writes -system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333441 # Number of Instructions Simulated -system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated -system.cpu.cpi 0.861644 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861644 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160572 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160572 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079711901 # number of integer regfile reads -system.cpu.int_regfile_writes 384939818 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes -system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads -system.cpu.misc_regfile_writes 832204 # number of misc regfile writes -system.cpu.icache.replacements 2508 # number of replacements -system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use -system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 448766216 # The number of ROB reads +system.cpu.rob.rob_writes 679506166 # The number of ROB writes +system.cpu.timesIdled 2556 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 100554 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172303021 # Number of Instructions Simulated +system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated +system.cpu.cpi 0.860680 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.860680 # CPI: Total CPI of All Threads +system.cpu.ipc 1.161872 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.161872 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079384127 # number of integer regfile reads +system.cpu.int_regfile_writes 384869699 # number of integer regfile writes +system.cpu.fp_regfile_reads 2912697 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497246 # number of floating regfile writes +system.cpu.misc_regfile_reads 54493639 # number of misc regfile reads +system.cpu.misc_regfile_writes 820036 # number of misc regfile writes +system.cpu.icache.replacements 2375 # number of replacements +system.cpu.icache.tagsinuse 1350.215949 # Cycle average of tags in use +system.cpu.icache.total_refs 36840897 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4105 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8974.639951 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36854521 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36854521 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits -system.cpu.icache.overall_hits::total 36854521 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5340 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5340 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5340 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5340 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5340 # number of overall misses -system.cpu.icache.overall_misses::total 5340 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 158697499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 158697499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 158697499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 158697499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 158697499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 158697499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36859861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36859861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36859861 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36859861 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36859861 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36859861 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 604 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42946.296296 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47008.967523 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46021.912351 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46554.973822 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47008.967523 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46021.912351 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46554.973822 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,177 +674,169 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2058 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 666 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2724 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2058 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1746 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3804 # 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Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25238.680690 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.343364 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34391106 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34391106 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356535 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356535 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22466 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22466 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46747641 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46747641 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46747641 # number of overall hits +system.cpu.dcache.overall_hits::total 46747641 # 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number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 378028996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 378028996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 378028996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 378028996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34393010 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34393010 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22468 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22468 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46757297 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46757297 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46757297 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46757297 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44206.670168 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44206.670168 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37907.571723 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37907.571723 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39149.647473 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39149.647473 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 472 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.307692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1138 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1138 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6664 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6664 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7802 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7802 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7802 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7802 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1088 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1088 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1854 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1854 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1854 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1854 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36187000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36187000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47523998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 47523998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83710998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 83710998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83710998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 83710998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses @@ -859,14 +845,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47241.514360 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47241.514360 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43680.145221 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43680.145221 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 92132dbec..581804c2a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.082648 # Number of seconds simulated -sim_ticks 82648140000 # Number of ticks simulated -final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.082776 # Number of seconds simulated +sim_ticks 82776043000 # Number of ticks simulated +final_tick 82776043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31465 # Simulator instruction rate (inst/s) -host_op_rate 52738 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19690094 # Simulator tick rate (ticks/s) -host_mem_usage 268216 # Number of bytes of host memory used -host_seconds 4197.45 # Real time elapsed on the host +host_inst_rate 77695 # Simulator instruction rate (inst/s) +host_op_rate 130224 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48695604 # Simulator tick rate (ticks/s) +host_mem_usage 276624 # Number of bytes of host memory used +host_seconds 1699.87 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory -system.physmem.bytes_read::total 342144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5346 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2634397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1505370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4139766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2634397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2634397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2634397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1505370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4139766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5348 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124288 # Number of bytes read from this memory +system.physmem.bytes_read::total 342272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1942 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5348 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2633419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1501497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4134916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2633419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2633419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2633419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1501497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4134916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5350 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5502 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342144 # Total number of bytes read from memory +system.physmem.cpureqs 5531 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 342272 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342144 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 342272 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 181 # Reqs where no action is needed system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 308 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 307 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 305 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 436 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 435 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 297 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 82648109000 # Total gap between requests +system.physmem.totGap 82776014000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5348 # Categorize read packet sizes +system.physmem.readPktSize::6 5350 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,12 +95,12 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 154 # categorize neither packet sizes +system.physmem.neitherpktsize::6 181 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -164,266 +164,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16873822 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests -system.physmem.totBusLat 21392000 # Total cycles spent in databus access -system.physmem.totBankLat 84182000 # Total cycles spent in bank access -system.physmem.avgQLat 3155.16 # Average queueing delay per request -system.physmem.avgBankLat 15740.84 # Average bank access latency per request +system.physmem.totQLat 13963836 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 119601836 # Sum of mem lat for all requests +system.physmem.totBusLat 21400000 # Total cycles spent in databus access +system.physmem.totBankLat 84238000 # Total cycles spent in bank access +system.physmem.avgQLat 2610.06 # Average queueing delay per request +system.physmem.avgBankLat 15745.42 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22896.00 # Average memory access latency -system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22355.48 # Average memory access latency +system.physmem.avgRdBW 4.13 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.13 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4742 # Number of row buffer hits during reads +system.physmem.readRowHits 4744 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15454021.88 # Average gap between requests +system.physmem.avgGap 15472152.15 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 165296281 # number of cpu cycles simulated +system.cpu.numCycles 165552087 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits +system.cpu.BPredUnit.lookups 19937507 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 19937507 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2011224 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13844585 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13082184 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25823167 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 218797366 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19937507 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13082184 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 57543253 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17618129 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 66723129 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2032 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 86 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24434096 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 426892 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 165432321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.185723 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325531 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3450171 2.09% 73.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3573015 2.16% 75.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4309284 2.61% 78.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2725915 1.65% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33580712 20.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 109484552 66.18% 66.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3053467 1.85% 68.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2384541 1.44% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2897248 1.75% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3448185 2.08% 73.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3564782 2.15% 75.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4309445 2.60% 78.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2719256 1.64% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33570845 20.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 165175969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.120712 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.324235 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38701150 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56465114 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44698220 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9957565 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15353920 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 353610105 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 15353920 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46165738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14909579 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 165432321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.120430 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.321623 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38724148 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56736512 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44639960 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9991325 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15340376 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 353466965 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15340376 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46189093 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 15008557 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 23078 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46524421 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42199233 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 345243747 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 88 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17893684 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22177130 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 398936501 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 960723880 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 950976963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9746917 # Number of floating rename lookups +system.cpu.rename.RunCycles 46492003 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42379214 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 345094521 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18065019 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22190556 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 104 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 398767810 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 960056051 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 950296029 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9760022 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 139507897 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 139339206 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1674 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1664 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90390787 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 86672801 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31756377 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 57758664 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18775058 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 333623093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3362 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 267451276 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 258403 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111810012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 230098900 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2117 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 165175969 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.619190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505359 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 1663 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90597841 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 86592813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31744520 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 57837693 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18834679 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 333487648 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3580 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267379172 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 250437 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111676069 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 229742853 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2335 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 165432321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.616245 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.503217 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44964626 27.22% 27.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46539597 28.18% 55.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32801785 19.86% 75.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19824720 12.00% 87.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13230335 8.01% 95.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4791341 2.90% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2351721 1.42% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 529174 0.32% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 142670 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45038788 27.22% 27.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46767309 28.27% 55.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32846173 19.85% 75.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19795888 11.97% 87.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13207626 7.98% 95.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4774334 2.89% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2327149 1.41% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 533647 0.32% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 141407 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 165175969 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 165432321 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 137826 5.20% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2250902 84.86% 90.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 263908 9.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133618 5.04% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2250761 84.95% 90.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 265061 10.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1212134 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174151286 65.12% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1593879 0.60% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67229168 25.14% 91.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23264809 8.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174135882 65.13% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1593779 0.60% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67177367 25.12% 91.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23260010 8.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 267451276 # Type of FU issued -system.cpu.iq.rate 1.618011 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2652636 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 697648502 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 441157156 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260237459 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5341058 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4570848 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2570585 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266205797 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2685981 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19039823 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267379172 # Type of FU issued +system.cpu.iq.rate 1.615076 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2649440 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009909 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 697750591 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 440878444 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260170034 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5339951 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4579505 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2570780 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266131077 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2685401 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19003165 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30023215 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29490 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 296813 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11240660 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 29943227 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 28980 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 295958 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11228803 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49425 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49224 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15353920 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 582358 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 260686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 333626455 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 190123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 86672801 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31756377 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1654 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 146774 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 296813 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1177159 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 916050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2093209 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264577691 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66245889 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2873585 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15340376 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 584172 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 263019 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 333491228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 190803 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 86592813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31744520 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1661 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148723 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30980 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 295958 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1176359 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 917156 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2093515 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264503897 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66194002 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2875275 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 89117815 # number of memory reference insts executed -system.cpu.iew.exec_branches 14597039 # Number of branches executed -system.cpu.iew.exec_stores 22871926 # Number of stores executed -system.cpu.iew.exec_rate 1.600627 # Inst execution rate -system.cpu.iew.wb_sent 263630467 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 262808044 # cumulative count of insts written-back -system.cpu.iew.wb_producers 212084858 # num instructions producing a value -system.cpu.iew.wb_consumers 375096623 # num instructions consuming a value +system.cpu.iew.exec_refs 89062868 # number of memory reference insts executed +system.cpu.iew.exec_branches 14601707 # Number of branches executed +system.cpu.iew.exec_stores 22868866 # Number of stores executed +system.cpu.iew.exec_rate 1.597708 # Inst execution rate +system.cpu.iew.wb_sent 263570746 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 262740814 # cumulative count of insts written-back +system.cpu.iew.wb_producers 211979430 # num instructions producing a value +system.cpu.iew.wb_consumers 374947027 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.589921 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.565414 # average fanout of values written-back +system.cpu.iew.wb_rate 1.587058 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565358 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 112301239 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 112163051 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2011502 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822049 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.477506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.946000 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2011438 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150091945 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.474849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.942132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50722618 33.86% 33.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57116806 38.12% 71.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13820755 9.22% 81.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12019830 8.02% 89.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4145175 2.77% 91.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2956577 1.97% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1072909 0.72% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 994916 0.66% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6972463 4.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50831007 33.87% 33.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57256127 38.15% 72.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13834026 9.22% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12065346 8.04% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4152706 2.77% 92.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2955841 1.97% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1060436 0.71% 94.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1001549 0.67% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6934907 4.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822049 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 150091945 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362961 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -434,198 +434,198 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339551 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6972463 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6934907 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 476513786 # The number of ROB reads -system.cpu.rob.rob_writes 682717187 # The number of ROB writes -system.cpu.timesIdled 2881 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 120312 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 476683050 # The number of ROB reads +system.cpu.rob.rob_writes 682427429 # The number of ROB writes +system.cpu.timesIdled 2933 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 119766 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362961 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.251570 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.251570 # CPI: Total CPI of All Threads -system.cpu.ipc 0.798997 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.798997 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 562635091 # number of integer regfile reads -system.cpu.int_regfile_writes 298739906 # number of integer regfile writes -system.cpu.fp_regfile_reads 3520410 # number of floating regfile reads -system.cpu.fp_regfile_writes 2230055 # number of floating regfile writes -system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads +system.cpu.cpi 1.253506 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.253506 # CPI: Total CPI of All Threads +system.cpu.ipc 0.797762 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.797762 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 562448945 # number of integer regfile reads +system.cpu.int_regfile_writes 298656184 # number of integer regfile writes +system.cpu.fp_regfile_reads 3520617 # number of floating regfile reads +system.cpu.fp_regfile_writes 2230281 # number of floating regfile writes +system.cpu.misc_regfile_reads 136958061 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4732 # number of replacements -system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use -system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. +system.cpu.icache.replacements 4787 # number of replacements +system.cpu.icache.tagsinuse 1623.671048 # Cycle average of tags in use +system.cpu.icache.total_refs 24425061 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6754 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3616.384513 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24437101 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24437101 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits -system.cpu.icache.overall_hits::total 24437101 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses -system.cpu.icache.overall_misses::total 8952 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1623.671048 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.792808 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.792808 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24425061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24425061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24425061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24425061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24425061 # number of overall hits +system.cpu.icache.overall_hits::total 24425061 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9035 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9035 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9035 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9035 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9035 # number of overall misses +system.cpu.icache.overall_misses::total 9035 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 258546498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 258546498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 258546498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 258546498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 258546498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 258546498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24434096 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24434096 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24434096 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24434096 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24434096 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24434096 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000370 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000370 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000370 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000370 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000370 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000370 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28616.103818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28616.103818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28616.103818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28616.103818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28616.103818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28616.103818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 770 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2099 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 197636498 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197636498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 197636498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197636498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 197636498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000284 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000284 # 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Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2513.899297 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3380 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3793 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.891115 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6755 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1979 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8734 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.504219 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.932039 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.528813 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995533 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.995533 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.507685 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.981341 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.504219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.982314 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.612549 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.504219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.982314 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.612549 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46104.374633 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54480.468750 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 46953.034301 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43307.371795 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43307.371795 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46104.374633 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 45514.403292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 45890 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46104.374633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 45514.403292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 45890 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,116 +634,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3402 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 386 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3788 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 154 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 154 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3406 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532247 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3406 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1944 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5350 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3406 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1944 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 177837092 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114067502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63769590 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 177837092 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.504219 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.528813 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995533 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30553.201282 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33490.165003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32803.287037 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33240.577944 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33490.165003 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32803.287037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33240.577944 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 55 # number of replacements -system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use -system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. +system.cpu.dcache.replacements 54 # number of replacements +system.cpu.dcache.tagsinuse 1408.542073 # Cycle average of tags in use +system.cpu.dcache.total_refs 67546144 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1977 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34165.980779 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113724000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113724000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 47032742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 47032742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 67548473 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67548473 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67548473 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67548473 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44958.536585 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44958.536585 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43943.967982 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43943.967982 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44267.808486 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44267.808486 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44267.808486 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44267.808486 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -752,48 +752,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 407 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 407 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 409 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 409 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 409 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 409 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1747 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1747 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2160 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2160 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2160 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2160 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73250500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73250500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 94942500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 94942500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 94942500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 94942500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52523.002421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52523.002421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41929.307384 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41929.307384 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43954.861111 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43954.861111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43954.861111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43954.861111 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |