diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se')
210 files changed, 14137 insertions, 9320 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 6c1c0e974..b932d7fd7 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 30b31a527..26d645fed 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:21 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index b5662ac02..1a8f04561 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.274500 # Nu sim_ticks 274500333500 # Number of ticks simulated final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113367 # Simulator instruction rate (inst/s) -host_tick_rate 51705325 # Simulator tick rate (ticks/s) -host_mem_usage 207980 # Number of bytes of host memory used -host_seconds 5308.94 # Real time elapsed on the host +host_inst_rate 160535 # Simulator instruction rate (inst/s) +host_op_rate 160535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73218214 # Simulator tick rate (ticks/s) +host_mem_usage 209892 # Number of bytes of host memory used +host_seconds 3749.07 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5894016 # Number of bytes read from this memory system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory system.physmem.bytes_written 3798080 # Number of bytes written to this memory @@ -69,9 +71,10 @@ system.cpu.comNops 36304520 # Nu system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed system.cpu.comInts 349039879 # Number of Integer instructions committed system.cpu.comFloats 24 # Number of Floating Point instructions committed -system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads @@ -125,26 +128,39 @@ system.cpu.icache.total_refs 27985205 # To system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits -system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits -system.cpu.icache.overall_hits 27985205 # number of overall hits -system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses -system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 728.259897 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355596 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355596 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27985205 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27985205 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27985205 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27985205 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27985205 # number of overall hits +system.cpu.icache.overall_hits::total 27985205 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses +system.cpu.icache.overall_misses::total 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56646500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56646500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56646500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56646500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56646500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56646500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27986224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27986224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27986224 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27986224 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27986224 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27986224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55590.284593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45774000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45774000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45774000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45774000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45774000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45774000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.842105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use @@ -181,32 +200,49 @@ system.cpu.dcache.total_refs 152394244 # To system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits -system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 152394244 # number of overall hits -system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses -system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1571119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.126386 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38273735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38273735 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152394244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152394244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152394244 # number of overall hits +system.cpu.dcache.overall_hits::total 152394244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1177586 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1177586 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1571119 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1571119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1571119 # number of overall misses +system.cpu.dcache.overall_misses::total 1571119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150453500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8150453500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25245531000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25245531000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33395984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33395984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33395984500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33395984500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029849 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20710.978495 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21438.375626 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked @@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408188 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 408188 # number of writebacks +system.cpu.dcache.writebacks::total 408188 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923423 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 923423 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115724 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115724 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115724 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115724 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466740000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466740000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9028878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028878000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9028878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.647849 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73797 # number of replacements system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use @@ -248,36 +292,72 @@ system.cpu.l2cache.total_refs 445688 # To system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364156 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92094 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16056.957351 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 28.224139 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1609.913702 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.490019 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000861 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.049131 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.540011 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 170051 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 170051 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4764594000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4809363000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44769000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4764594000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4809363000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201215 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202070 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 408188 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 408188 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254180 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254180 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154879 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236348 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200351 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200351 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked @@ -286,30 +366,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59345 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59345 # number of writebacks +system.cpu.l2cache.writebacks::total 59345 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60075 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653580500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3687925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653580500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3687925500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154879 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index cc9b0c683..d5e06addc 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ad1c408b1..e473c70fd 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:26 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 8681db468..6a8942beb 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.144450 # Nu sim_ticks 144450185500 # Number of ticks simulated final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205040 # Simulator instruction rate (inst/s) -host_tick_rate 52370107 # Simulator tick rate (ticks/s) -host_mem_usage 208620 # Number of bytes of host memory used -host_seconds 2758.26 # Real time elapsed on the host +host_inst_rate 270959 # Simulator instruction rate (inst/s) +host_op_rate 270959 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69206896 # Simulator tick rate (ticks/s) +host_mem_usage 211048 # Number of bytes of host memory used +host_seconds 2087.22 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated +sim_ops 565552443 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5936768 # Number of bytes read from this memory system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory system.physmem.bytes_written 3797120 # Number of bytes written to this memory @@ -272,6 +274,7 @@ system.cpu.iew.wb_rate 2.107953 # in system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions +system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted @@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle -system.cpu.commit.count 601856963 # Number of instructions committed +system.cpu.commit.committedInsts 601856963 # Number of instructions committed +system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed system.cpu.commit.loads 114514042 # Number of loads committed @@ -308,6 +312,7 @@ system.cpu.rob.rob_writes 1385724156 # Th system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated +system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads @@ -325,26 +330,39 @@ system.cpu.icache.total_refs 70951127 # To system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 801.236568 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.391229 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 70951127 # number of ReadReq hits -system.cpu.icache.demand_hits 70951127 # number of demand (read+write) hits -system.cpu.icache.overall_hits 70951127 # number of overall hits -system.cpu.icache.ReadReq_misses 1272 # number of ReadReq misses -system.cpu.icache.demand_misses 1272 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 45919500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 45919500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 70952399 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 70952399 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36100.235849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36100.235849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36100.235849 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 801.236568 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.391229 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.391229 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 70951127 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70951127 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70951127 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70951127 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70951127 # number of overall hits +system.cpu.icache.overall_hits::total 70951127 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1272 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1272 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1272 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1272 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1272 # number of overall misses +system.cpu.icache.overall_misses::total 1272 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45919500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45919500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45919500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45919500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45919500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45919500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70952399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70952399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70952399 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70952399 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70952399 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70952399 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000018 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000018 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36100.235849 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 944 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 944 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 944 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33676000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35673.728814 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 944 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 944 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 944 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33676000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33676000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35673.728814 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 470690 # number of replacements system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use @@ -381,34 +402,53 @@ system.cpu.dcache.total_refs 151212527 # To system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4093.940031 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 113064898 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38147626 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 151212524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 151212524 # number of overall hits -system.cpu.dcache.ReadReq_misses 732041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1303695 # number of WriteReq misses -system.cpu.dcache.demand_misses 2035736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2035736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 31416273219 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 113796939 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153248260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153248260 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.033046 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013284 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013284 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16096.821080 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15059.304683 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15432.390653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15432.390653 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4093.940031 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999497 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999497 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 113064898 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113064898 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38147626 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38147626 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 151212524 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151212524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151212524 # number of overall hits +system.cpu.dcache.overall_hits::total 151212524 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 732041 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 732041 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1303695 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1303695 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2035736 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2035736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2035736 # number of overall misses +system.cpu.dcache.overall_misses::total 2035736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11783533000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11783533000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19632740219 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19632740219 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31416273219 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31416273219 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31416273219 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31416273219 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 113796939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 113796939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153248260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153248260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153248260 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153248260 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006433 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033046 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013284 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013284 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16096.821080 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15059.304683 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked @@ -417,32 +457,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345 system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423044 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 513277 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1560950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256022 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 474786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003098 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003098 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.994478 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.774715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 423044 # 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number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 256022 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 474786 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 474786 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 474786 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 474786 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1640072500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1640072500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3027658494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3027658494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4667730994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4667730994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4667730994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4667730994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001922 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7496.994478 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11825.774715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74463 # number of replacements system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use @@ -450,36 +498,72 @@ system.cpu.l2cache.total_refs 478021 # To system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1743.919943 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15917.792095 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053220 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485772 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186750 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423044 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 196218 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 382968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 382968 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32958 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92762 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92762 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1133680000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2065878500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3199558500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3199558500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219708 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 475730 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 475730 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.150008 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.233589 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194989 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194989 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34492.125008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34492.125008 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15917.792095 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 36.116254 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1707.803688 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.485772 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001102 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.538993 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 186750 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 186750 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 423044 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 423044 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 196218 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 196218 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 475730 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 944 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 474786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 475730 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.146340 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.233589 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.193388 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.193388 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34369.173729 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.560005 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34544.152565 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked @@ -488,30 +572,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59330 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32958 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92762 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92762 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1022345000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877543500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2899888500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2899888500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150008 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233589 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194989 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194989 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59330 # number of writebacks +system.cpu.l2cache.writebacks::total 59330 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32014 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32958 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91818 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91818 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92762 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29409000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 992936000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1022345000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1877543500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1877543500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2870479500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2899888500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29409000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2870479500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2899888500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.146340 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.233589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31153.601695 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.680640 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31394.948498 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 282141772..8be56150d 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout index 1dc402141..b88c15875 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:30 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index ad4f39b85..97a3f2734 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.300931 # Nu sim_ticks 300930958000 # Number of ticks simulated final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4527143 # Simulator instruction rate (inst/s) -host_tick_rate 2263589972 # Simulator tick rate (ticks/s) -host_mem_usage 198960 # Number of bytes of host memory used -host_seconds 132.94 # Real time elapsed on the host +host_inst_rate 5630967 # Simulator instruction rate (inst/s) +host_op_rate 5630966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2815505896 # Simulator tick rate (ticks/s) +host_mem_usage 200704 # Number of bytes of host memory used +host_seconds 106.88 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2782990928 # Number of bytes read from this memory system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory system.physmem.bytes_written 152669504 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 601861917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.committedInsts 601856964 # Number of instructions committed +system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses system.cpu.num_func_calls 2395217 # number of times a function call or return occured diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 0bc5277c7..83c88fa93 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index 36bd68fb7..dfe9fcdd2 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:31 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 4d7850adf..4b454bbcf 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.765623 # Nu sim_ticks 765623032000 # Number of ticks simulated final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2199350 # Simulator instruction rate (inst/s) -host_tick_rate 2797795440 # Simulator tick rate (ticks/s) -host_mem_usage 207676 # Number of bytes of host memory used -host_seconds 273.65 # Real time elapsed on the host +host_inst_rate 2698243 # Simulator instruction rate (inst/s) +host_op_rate 2698243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3432438217 # Simulator tick rate (ticks/s) +host_mem_usage 209572 # Number of bytes of host memory used +host_seconds 223.06 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5889984 # Number of bytes read from this memory system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory system.physmem.bytes_written 3797824 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 1531246064 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.committedInsts 601856964 # Number of instructions committed +system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses system.cpu.num_func_calls 2395217 # number of times a function call or return occured @@ -79,26 +82,39 @@ system.cpu.icache.total_refs 601861103 # To system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits -system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits -system.cpu.icache.overall_hits 601861103 # number of overall hits -system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.demand_misses 795 # number of demand (read+write) misses -system.cpu.icache.overall_misses 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 601861103 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 601861103 # number of overall hits +system.cpu.icache.overall_hits::total 601861103 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 795 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 795 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses +system.cpu.icache.overall_misses::total 795 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 601861898 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 795 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use @@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 153509968 # To system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits +system.cpu.dcache.overall_hits::total 153509968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses +system.cpu.dcache.overall_misses::total 455395 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408190 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks +system.cpu.dcache.writebacks::total 408190 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73734 # number of replacements system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use @@ -199,36 +232,72 @@ system.cpu.l2cache.total_refs 445709 # To system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364159 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92031 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.543931 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3123588000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4744272000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4785612000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41340000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4744272000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4785612000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456190 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,30 +306,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59341 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks +system.cpu.l2cache.writebacks::total 59341 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 2c3feadf1..c24180c55 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 316fa1ee5..c2143f70c 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:23 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:39:44 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index e05b6f985..e204ea2b2 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.177117 # Nu sim_ticks 177116942500 # Number of ticks simulated final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89657 # Simulator instruction rate (inst/s) -host_tick_rate 26362655 # Simulator tick rate (ticks/s) -host_mem_usage 256136 # Number of bytes of host memory used -host_seconds 6718.48 # Real time elapsed on the host -sim_insts 602359810 # Number of instructions simulated +host_inst_rate 193712 # Simulator instruction rate (inst/s) +host_op_rate 204690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60186856 # Simulator tick rate (ticks/s) +host_mem_usage 223404 # Number of bytes of host memory used +host_seconds 2942.78 # Real time elapsed on the host +sim_insts 570051603 # Number of instructions simulated +sim_ops 602359810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5833792 # Number of bytes read from this memory system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory system.physmem.bytes_written 3720320 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 570051654 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602359861 # The number of committed instructions system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle -system.cpu.commit.count 602359861 # Number of instructions committed +system.cpu.commit.committedInsts 570051654 # Number of instructions committed +system.cpu.commit.committedOps 602359861 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 219173611 # Number of memory references committed system.cpu.commit.loads 148952596 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 1023326216 # Th system.cpu.rob.rob_writes 1419524916 # The number of ROB writes system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359810 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated -system.cpu.cpi 0.588077 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.588077 # CPI: Total CPI of All Threads -system.cpu.ipc 1.700458 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.700458 # IPC: Total IPC of All Threads +system.cpu.committedInsts 570051603 # Number of Instructions Simulated +system.cpu.committedOps 602359810 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051603 # Number of Instructions Simulated +system.cpu.cpi 0.621407 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.621407 # CPI: Total CPI of All Threads +system.cpu.ipc 1.609252 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.609252 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads system.cpu.int_regfile_writes 676006750 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads @@ -335,26 +340,39 @@ system.cpu.icache.total_refs 74421550 # To system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 657.275674 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.320935 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 74421550 # number of ReadReq hits -system.cpu.icache.demand_hits 74421550 # number of demand (read+write) hits -system.cpu.icache.overall_hits 74421550 # number of overall hits -system.cpu.icache.ReadReq_misses 996 # number of ReadReq misses -system.cpu.icache.demand_misses 996 # number of demand (read+write) misses -system.cpu.icache.overall_misses 996 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34937500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34937500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 74422546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 74422546 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 74422546 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35077.811245 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35077.811245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35077.811245 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 657.275674 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.320935 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.320935 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 74421550 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 74421550 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 74421550 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 74421550 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 74421550 # number of overall hits +system.cpu.icache.overall_hits::total 74421550 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 996 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 996 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 996 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 996 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 996 # number of overall misses +system.cpu.icache.overall_misses::total 996 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34937500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34937500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34937500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34937500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34937500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34937500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 74422546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 74422546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 74422546 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 74422546 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 74422546 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 74422546 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000013 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000013 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000013 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35077.811245 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,27 +381,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 231 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 231 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 231 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 765 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 765 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 765 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 26235000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 26235000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 26235000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34294.117647 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 231 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 231 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 231 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 231 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 231 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 765 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 765 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 765 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 765 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 765 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 765 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26235000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26235000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26235000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26235000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26235000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26235000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34294.117647 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34294.117647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34294.117647 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 441200 # number of replacements system.cpu.dcache.tagsinuse 4094.750887 # Cycle average of tags in use @@ -391,40 +412,63 @@ system.cpu.dcache.total_refs 205785268 # To system.cpu.dcache.sampled_refs 445296 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 462.131409 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 87972000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.750887 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 137930344 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67852261 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 205782605 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 205782605 # number of overall hits -system.cpu.dcache.ReadReq_misses 248964 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1565270 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1814234 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1814234 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3282822000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 27026336525 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 201000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 30309158525 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30309158525 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 138179308 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1343 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 207596839 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 207596839 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001802 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.022549 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.006701 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008739 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008739 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13185.930496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17266.245775 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 22333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 16706.311603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 16706.311603 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.750887 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137930344 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137930344 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 67852261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 67852261 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1329 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1329 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 205782605 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 205782605 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 205782605 # number of overall hits +system.cpu.dcache.overall_hits::total 205782605 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 248964 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 248964 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1565270 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1565270 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 9 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 9 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1814234 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1814234 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1814234 # number of overall misses +system.cpu.dcache.overall_misses::total 1814234 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282822000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3282822000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27026336525 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27026336525 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 201000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30309158525 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30309158525 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30309158525 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30309158525 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 138179308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 138179308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1329 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1329 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 207596839 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 207596839 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 207596839 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 207596839 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001802 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022549 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.006701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008739 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008739 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13185.930496 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17266.245775 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -433,33 +477,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395250 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51046 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1317892 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1368938 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1368938 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197918 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247378 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1625205500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2544318027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4169523527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4169523527 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8211.509312 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.142684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 395250 # number of writebacks +system.cpu.dcache.writebacks::total 395250 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51046 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51046 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1317892 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1317892 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 9 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 9 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1368938 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1368938 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1368938 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1368938 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197918 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197918 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247378 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247378 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 445296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 445296 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 445296 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 445296 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1625205500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1625205500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2544318027 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2544318027 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4169523527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4169523527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4169523527 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4169523527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001432 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003564 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8211.509312 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10285.142684 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 72965 # number of replacements system.cpu.l2cache.tagsinuse 17807.300199 # Cycle average of tags in use @@ -467,36 +520,75 @@ system.cpu.l2cache.total_refs 421253 # To system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.760351 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1881.136315 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15926.163884 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057408 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486028 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165871 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395250 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 189027 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354898 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354898 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32808 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58355 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91163 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91163 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1126263500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2003081500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3129345000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3129345000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198679 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 395250 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247382 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 446061 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 446061 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165131 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235890 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204373 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204373 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34328.928920 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.790421 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34326.919913 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34326.919913 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15926.163884 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 35.771827 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1845.364487 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.486028 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001092 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.056316 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.543436 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 165841 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 165871 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 395250 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 395250 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 189027 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 189027 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 354868 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 354898 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 354868 # number of overall hits +system.cpu.l2cache.overall_hits::total 354898 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 735 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32073 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 32808 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 58355 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 58355 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 735 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 90428 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 91163 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 735 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 90428 # number of overall misses +system.cpu.l2cache.overall_misses::total 91163 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25238000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101025500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1126263500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2003081500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2003081500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25238000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3104107000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3129345000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25238000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3104107000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3129345000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 765 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 197914 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 198679 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 395250 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 395250 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247382 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247382 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 765 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 445296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 446061 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 765 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 445296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 446061 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960784 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162055 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235890 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960784 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.203074 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960784 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.203074 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34337.414966 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.734450 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34325.790421 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -505,31 +597,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58130 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32798 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58355 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91153 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1019340000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822214500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2841554500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2841554500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165080 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235890 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204351 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.334106 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31226.364493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 58130 # number of writebacks +system.cpu.l2cache.writebacks::total 58130 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32798 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58355 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58355 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90419 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91153 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90419 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91153 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22853000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 996487000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1019340000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1822214500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1822214500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22853000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2818701500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2841554500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22853000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2818701500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2841554500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162010 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235890 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31134.877384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31078.062625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31226.364493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index 8c7671d34..35f1e8fcc 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index 95da0efca..d3f3c8cc8 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:36:54 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:43:07 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index f48dc3640..80be44c4e 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2998309 # Simulator instruction rate (inst/s) -host_tick_rate 1499211130 # Simulator tick rate (ticks/s) -host_mem_usage 210136 # Number of bytes of host memory used -host_seconds 200.90 # Real time elapsed on the host -sim_insts 602359851 # Number of instructions simulated +host_inst_rate 3224710 # Simulator instruction rate (inst/s) +host_op_rate 3407474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1703801368 # Simulator tick rate (ticks/s) +host_mem_usage 212692 # Number of bytes of host memory used +host_seconds 176.78 # Real time elapsed on the host +sim_insts 570051644 # Number of instructions simulated +sim_ops 602359851 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2680160157 # Number of bytes read from this memory system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory system.physmem.bytes_written 236359611 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 48 # Nu system.cpu.numCycles 602382741 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 602359851 # Number of instructions executed +system.cpu.committedInsts 570051644 # Number of instructions committed +system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 6a1e2b970..ce56af1f4 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index 589b03862..eee2e0cb2 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:40:26 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:45:54 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 3846f97fb..4b6f6b404 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1450316 # Simulator instruction rate (inst/s) -host_tick_rate 1924652930 # Simulator tick rate (ticks/s) -host_mem_usage 219100 # Number of bytes of host memory used -host_seconds 413.98 # Real time elapsed on the host -sim_insts 600398281 # Number of instructions simulated +host_inst_rate 1806630 # Simulator instruction rate (inst/s) +host_op_rate 1907867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2531848956 # Simulator tick rate (ticks/s) +host_mem_usage 221588 # Number of bytes of host memory used +host_seconds 314.70 # Real time elapsed on the host +sim_insts 568539343 # Number of instructions simulated +sim_ops 600398281 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5759488 # Number of bytes read from this memory system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory system.physmem.bytes_written 3704704 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 48 # Nu system.cpu.numCycles 1593525852 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 600398281 # Number of instructions executed +system.cpu.committedInsts 568539343 # Number of instructions committed +system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 570073892 # To system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits -system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits -system.cpu.icache.overall_hits 570073892 # number of overall hits -system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses -system.cpu.icache.demand_misses 643 # number of demand (read+write) misses -system.cpu.icache.overall_misses 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits +system.cpu.icache.overall_hits::total 570073892 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses +system.cpu.icache.overall_misses::total 643 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 216774473 # To system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 216771819 # number of overall hits -system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses -system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits +system.cpu.dcache.overall_hits::total 216771819 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses +system.cpu.dcache.overall_misses::total 437564 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 392392 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks +system.cpu.dcache.writebacks::total 392392 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71804 # number of replacements system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 411836 # To system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 348215 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 89992 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits 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misses +system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 31541 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 58451 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 58451 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 89376 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 89992 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 89376 # number of overall misses +system.cpu.l2cache.overall_misses::total 89992 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1608100000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1640132000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3039452000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3039452000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4647552000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4679584000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4647552000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4679584000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 57886 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks +system.cpu.l2cache.writebacks::total 57886 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index dcba73ec2..5612e55e7 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index a835cbd79..337dcecf7 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:17:40 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:12 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index e4d9fca07..3c7a99cbd 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.408816 # Nu sim_ticks 408816360000 # Number of ticks simulated final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175830 # Simulator instruction rate (inst/s) -host_tick_rate 51139829 # Simulator tick rate (ticks/s) -host_mem_usage 215728 # Number of bytes of host memory used -host_seconds 7994.10 # Real time elapsed on the host -sim_insts 1405604152 # Number of instructions simulated +host_inst_rate 218783 # Simulator instruction rate (inst/s) +host_op_rate 219472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63832966 # Simulator tick rate (ticks/s) +host_mem_usage 214000 # Number of bytes of host memory used +host_seconds 6404.47 # Real time elapsed on the host +sim_insts 1401188958 # Number of instructions simulated +sim_ops 1405604152 # Number of ops (including micro ops) simulated system.physmem.bytes_read 6021376 # Number of bytes read from this memory system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory system.physmem.bytes_written 3792448 # Number of bytes written to this memory @@ -237,7 +239,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions system.cpu.commit.commitSquashedInsts 179255835 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 5438120 # The number of times a branch was mispredicted @@ -258,7 +261,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 791834306 # Number of insts commited each cycle -system.cpu.commit.count 1489523295 # Number of instructions committed +system.cpu.commit.committedInsts 1485108101 # Number of instructions committed +system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed system.cpu.commit.loads 402512844 # Number of loads committed @@ -273,12 +277,13 @@ system.cpu.rob.rob_reads 2392297077 # Th system.cpu.rob.rob_writes 3363039880 # The number of ROB writes system.cpu.timesIdled 11286 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1405604152 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.581695 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.581695 # CPI: Total CPI of All Threads -system.cpu.ipc 1.719114 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.719114 # IPC: Total IPC of All Threads +system.cpu.committedInsts 1401188958 # Number of Instructions Simulated +system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated +system.cpu.cpi 0.583528 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.583528 # CPI: Total CPI of All Threads +system.cpu.ipc 1.713714 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.713714 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads system.cpu.int_regfile_writes 1303867666 # number of integer regfile writes system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads @@ -291,26 +296,39 @@ system.cpu.icache.total_refs 170772098 # To system.cpu.icache.sampled_refs 1298 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 131565.560863 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1031.400456 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.503614 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 170772098 # number of ReadReq hits -system.cpu.icache.demand_hits 170772098 # number of demand (read+write) hits -system.cpu.icache.overall_hits 170772098 # number of overall hits -system.cpu.icache.ReadReq_misses 1798 # number of ReadReq misses -system.cpu.icache.demand_misses 1798 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1798 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 62741500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 62741500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 62741500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 170773896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 170773896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 170773896 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000011 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000011 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34895.161290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34895.161290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34895.161290 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1031.400456 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.503614 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.503614 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 170772098 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170772098 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170772098 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170772098 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170772098 # number of overall hits +system.cpu.icache.overall_hits::total 170772098 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1798 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1798 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1798 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1798 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1798 # number of overall misses +system.cpu.icache.overall_misses::total 1798 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62741500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62741500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62741500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62741500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62741500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62741500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170773896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170773896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170773896 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170773896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170773896 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170773896 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34895.161290 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,27 +337,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 499 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 499 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 499 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45206000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45206000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45206000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34800.615858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 499 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 499 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 499 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 499 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 499 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 499 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1299 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1299 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1299 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1299 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45206000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45206000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45206000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45206000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45206000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45206000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34800.615858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 475353 # number of replacements system.cpu.dcache.tagsinuse 4095.165283 # Cycle average of tags in use @@ -347,38 +368,59 @@ system.cpu.dcache.total_refs 385593109 # To system.cpu.dcache.sampled_refs 479449 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 804.242180 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.165283 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 220654856 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 164936934 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 385591790 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 385591790 # number of overall hits -system.cpu.dcache.ReadReq_misses 815916 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1909882 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2725798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2725798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11966603000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 29861651909 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 268000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 41828254909 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 41828254909 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 221470772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 388317588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 388317588 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003684 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011447 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.007020 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.007020 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14666.464440 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15635.338680 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15345.324528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15345.324528 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4095.165283 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 220654856 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 220654856 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164936934 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164936934 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 385591790 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 385591790 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 385591790 # number of overall hits +system.cpu.dcache.overall_hits::total 385591790 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 815916 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 815916 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1909882 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1909882 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 2725798 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2725798 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2725798 # number of overall misses +system.cpu.dcache.overall_misses::total 2725798 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11966603000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11966603000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29861651909 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29861651909 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 268000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 268000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41828254909 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41828254909 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41828254909 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41828254909 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 221470772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 221470772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 388317588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 388317588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 388317588 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 388317588 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003684 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011447 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007020 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007020 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14666.464440 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15635.338680 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38285.714286 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -387,36 +429,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2153.846154 system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 426654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 603731 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1642625 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2246356 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2246356 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 212185 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 267257 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 479442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 479442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1589383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3625603341 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5214986841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5214986841 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000958 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001602 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001235 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001235 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7490.555412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13565.980839 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 426654 # number of writebacks +system.cpu.dcache.writebacks::total 426654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603731 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 603731 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642625 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2246356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2246356 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2246356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2246356 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3625603341 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3625603341 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 247000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 247000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5214986841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5214986841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5214986841 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5214986841 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7490.555412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13565.980839 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35285.714286 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 75859 # number of replacements system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use @@ -424,36 +476,75 @@ system.cpu.l2cache.total_refs 464590 # To system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2079.678027 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15735.123399 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.063467 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.480198 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 179822 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 426654 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 206842 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 386664 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 386664 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33662 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.226076 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.195703 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.195703 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.331769 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.951309 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34276.917435 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34276.917435 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15735.123399 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 94.212469 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1985.465558 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.480198 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.002875 # 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number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1299 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 212185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 213484 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 426654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 426654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 267264 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 267264 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1299 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 479449 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 480748 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1299 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 479449 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 480748 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983834 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.152622 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.226076 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983834 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.193568 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983834 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.193568 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34231.220657 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34028.640687 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34410.951309 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,30 +553,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59257 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33662 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60422 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94084 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94084 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1043686000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2935836500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2935836500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157679 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226076 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.195703 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.195703 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871962 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.588693 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59257 # number of writebacks +system.cpu.l2cache.writebacks::total 59257 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32384 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33662 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60422 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60422 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 92806 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 94084 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 92806 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 94084 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39610000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1004076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1043686000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1892150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1892150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39610000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2896226500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2935836500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39610000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2896226500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2935836500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.152622 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.226076 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30993.740219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.311265 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.588693 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini index b52495d06..12208533c 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout index d2df5cc09..dd6f18f54 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:18:03 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:17 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index afe2bae4f..317e75938 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.744764 # Nu sim_ticks 744764119000 # Number of ticks simulated final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3773289 # Simulator instruction rate (inst/s) -host_tick_rate 1886650577 # Simulator tick rate (ticks/s) -host_mem_usage 205844 # Number of bytes of host memory used -host_seconds 394.75 # Real time elapsed on the host -sim_insts 1489523295 # Number of instructions simulated +host_inst_rate 4631105 # Simulator instruction rate (inst/s) +host_op_rate 4644873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2322443893 # Simulator tick rate (ticks/s) +host_mem_usage 203508 # Number of bytes of host memory used +host_seconds 320.68 # Real time elapsed on the host +sim_insts 1485108101 # Number of instructions simulated +sim_ops 1489523295 # Number of ops (including micro ops) simulated system.physmem.bytes_read 7326269637 # Number of bytes read from this memory system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory system.physmem.bytes_written 614672063 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 49 # Nu system.cpu.numCycles 1489528239 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.committedInsts 1485108101 # Number of instructions committed +system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index ea98a23a1..8f915a65c 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index b26fb3f41..31dd55bac 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:19:05 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:19 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 059312926..91253ef89 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.064259 # Nu sim_ticks 2064258667000 # Number of ticks simulated final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1766930 # Simulator instruction rate (inst/s) -host_tick_rate 2448703239 # Simulator tick rate (ticks/s) -host_mem_usage 214556 # Number of bytes of host memory used -host_seconds 843.00 # Real time elapsed on the host -sim_insts 1489523295 # Number of instructions simulated +host_inst_rate 2132645 # Simulator instruction rate (inst/s) +host_op_rate 2138986 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2964317062 # Simulator tick rate (ticks/s) +host_mem_usage 212372 # Number of bytes of host memory used +host_seconds 696.37 # Real time elapsed on the host +sim_insts 1485108101 # Number of instructions simulated +sim_ops 1489523295 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5909952 # Number of bytes read from this memory system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory system.physmem.bytes_written 3778240 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 49 # Nu system.cpu.numCycles 4128517334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.committedInsts 1485108101 # Number of instructions committed +system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 1485111905 # To system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.442603 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits -system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1485111905 # number of overall hits -system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses -system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits +system.cpu.icache.overall_hits::total 1485111905 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses +system.cpu.icache.overall_misses::total 1107 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use @@ -102,38 +116,59 @@ system.cpu.dcache.total_refs 568907765 # To system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999811 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 166587088 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 568906446 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 568906446 # number of overall hits -system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 259728 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 453214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4019834000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 6156948000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 392000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 10176782000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 10176782000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22454.694692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits +system.cpu.dcache.overall_hits::total 568906446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses +system.cpu.dcache.overall_misses::total 453214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 407009 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 259728 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks +system.cpu.dcache.writebacks::total 407009 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74112 # number of replacements system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use @@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs 427085 # To system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057187 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.483685 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 199710 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 361985 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 361985 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32318 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60025 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92343 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92343 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1680536000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3121300000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4801836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4801836000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.203252 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits +system.cpu.l2cache.overall_hits::total 361985 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses +system.cpu.l2cache.overall_misses::total 92343 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1680536000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3121300000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3121300000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4744480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4801836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4744480000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4801836000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 453221 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 454328 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59035 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks +system.cpu.l2cache.writebacks::total 59035 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1103 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60025 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60025 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1103 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1103 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92343 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1248600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1292720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2401000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2401000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3693720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 3b035cefe..5b4602be4 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,12 +510,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 774f2864e..dd2c66002 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:08:06 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 1e4919244..db3272b03 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.586835 # Nu sim_ticks 586834596000 # Number of ticks simulated final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99458 # Simulator instruction rate (inst/s) -host_tick_rate 35994653 # Simulator tick rate (ticks/s) -host_mem_usage 253740 # Number of bytes of host memory used -host_seconds 16303.38 # Real time elapsed on the host -sim_insts 1621493982 # Number of instructions simulated +host_inst_rate 106927 # Simulator instruction rate (inst/s) +host_op_rate 197018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71302744 # Simulator tick rate (ticks/s) +host_mem_usage 220908 # Number of bytes of host memory used +host_seconds 8230.18 # Real time elapsed on the host +sim_insts 880025312 # Number of instructions simulated +sim_ops 1621493982 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5879616 # Number of bytes read from this memory system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory system.physmem.bytes_written 3743488 # Number of bytes written to this memory @@ -236,7 +238,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted @@ -257,7 +260,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle -system.cpu.commit.count 1621493982 # Number of instructions committed +system.cpu.commit.committedInsts 880025312 # Number of instructions committed +system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed system.cpu.commit.loads 419042125 # Number of loads committed @@ -272,12 +276,13 @@ system.cpu.rob.rob_reads 3082456564 # Th system.cpu.rob.rob_writes 3992764754 # The number of ROB writes system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1621493982 # Number of Instructions Simulated -system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.723820 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.723820 # CPI: Total CPI of All Threads -system.cpu.ipc 1.381560 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.381560 # IPC: Total IPC of All Threads +system.cpu.committedInsts 880025312 # Number of Instructions Simulated +system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated +system.cpu.cpi 1.333677 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.333677 # CPI: Total CPI of All Threads +system.cpu.ipc 0.749807 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.749807 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes system.cpu.fp_regfile_reads 12 # number of floating regfile reads @@ -288,26 +293,39 @@ system.cpu.icache.total_refs 136532946 # To system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 807.278486 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.394179 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 136532946 # number of ReadReq hits -system.cpu.icache.demand_hits 136532946 # number of demand (read+write) hits -system.cpu.icache.overall_hits 136532946 # number of overall hits -system.cpu.icache.ReadReq_misses 1228 # number of ReadReq misses -system.cpu.icache.demand_misses 1228 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43195500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43195500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43195500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 136534174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 136534174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 136534174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35175.488599 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35175.488599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35175.488599 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 807.278486 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.394179 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.394179 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 136532946 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 136532946 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 136532946 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 136532946 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 136532946 # number of overall hits +system.cpu.icache.overall_hits::total 136532946 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1228 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1228 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1228 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1228 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1228 # number of overall misses +system.cpu.icache.overall_misses::total 1228 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 43195500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 43195500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 43195500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 43195500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 43195500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 43195500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 136534174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 136534174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 136534174 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 136534174 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 136534174 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 136534174 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35175.488599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,27 +334,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 334 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 334 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 334 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 894 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 894 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 894 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 31569000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 31569000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 31569000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.080537 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 894 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 894 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 894 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 894 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 894 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 894 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31569000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31569000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31569000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31569000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31569000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31569000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35312.080537 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35312.080537 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35312.080537 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 459037 # number of replacements system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use @@ -344,32 +365,49 @@ system.cpu.dcache.total_refs 430357004 # To system.cpu.dcache.sampled_refs 463133 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 929.229841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 414463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.269422 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 242420503 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 187936501 # number of WriteReq hits -system.cpu.dcache.demand_hits 430357004 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 430357004 # number of overall hits -system.cpu.dcache.ReadReq_misses 217102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 249556 # number of WriteReq misses -system.cpu.dcache.demand_misses 466658 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 466658 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2192767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 3219007000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 5411774500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 5411774500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 242637605 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 430823662 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 430823662 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000895 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001326 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.001083 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.001083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10100.171809 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 12898.936511 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 11596.875013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 11596.875013 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.269422 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999577 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999577 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 242420503 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 242420503 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187936501 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187936501 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 430357004 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 430357004 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 430357004 # number of overall hits +system.cpu.dcache.overall_hits::total 430357004 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 217102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 217102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 249556 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 249556 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 466658 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 466658 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 466658 # number of overall misses +system.cpu.dcache.overall_misses::total 466658 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2192767500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2192767500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3219007000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3219007000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 5411774500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 5411774500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 5411774500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 5411774500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242637605 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242637605 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 430823662 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 430823662 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 430823662 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 430823662 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000895 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001326 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001083 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001083 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10100.171809 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12898.936511 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11596.875013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11596.875013 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,32 +416,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 409999 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3488 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 35 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3523 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3523 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213614 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249521 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1523998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2469759000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3993757500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3993757500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000880 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001075 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7134.356831 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9898.000569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 409999 # number of writebacks +system.cpu.dcache.writebacks::total 409999 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3488 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 35 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3523 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3523 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3523 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3523 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 213614 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 213614 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249521 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249521 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 463135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1523998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1523998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2469759000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2469759000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3993757500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3993757500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3993757500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3993757500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000880 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001326 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7134.356831 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9898.000569 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73601 # number of replacements system.cpu.l2cache.tagsinuse 17971.586292 # Cycle average of tags in use @@ -411,36 +457,75 @@ system.cpu.l2cache.total_refs 452847 # To system.cpu.l2cache.sampled_refs 89223 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 5.075451 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1981.498209 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15990.088083 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.060471 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487979 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181345 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 409999 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 190815 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 372160 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 372160 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33162 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91869 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91869 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1129684500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2008512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3138196500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3138196500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214507 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 409999 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464029 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464029 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154596 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235278 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197981 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197981 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34065.632350 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34212.478921 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34159.471639 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34159.471639 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15990.088083 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 59.987883 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1921.510326 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.487979 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001831 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.058640 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.548449 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 181342 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 181345 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 409999 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 409999 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 190815 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 190815 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 372157 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 372160 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 372157 # number of overall hits +system.cpu.l2cache.overall_hits::total 372160 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 891 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33162 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 58707 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 58707 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 891 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 90978 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 91869 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 891 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 90978 # number of overall misses +system.cpu.l2cache.overall_misses::total 91869 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30543500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1099141000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1129684500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2008512000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2008512000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30543500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3107653000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3138196500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30543500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3107653000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3138196500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 894 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 213613 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 214507 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 409999 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 409999 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 249522 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 249522 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 894 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 463135 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 464029 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 894 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 463135 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 464029 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996644 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151072 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235278 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996644 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.196439 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996644 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.196439 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34280.022447 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34059.713055 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34212.478921 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,30 +534,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58492 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33162 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91869 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91869 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1028173500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819949000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2848122500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2848122500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154596 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235278 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197981 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197981 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.568482 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.545080 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 58492 # number of writebacks +system.cpu.l2cache.writebacks::total 58492 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 891 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33162 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58707 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58707 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 891 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90978 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91869 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 891 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90978 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91869 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27674500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1000499000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028173500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1819949000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1819949000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27674500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2820448000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2848122500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27674500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2820448000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2848122500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151072 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235278 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.044893 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.036782 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.545080 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 393d71365..6904b6f42 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 3da3c7641..061803200 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:33:19 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:08:56 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 3a54bb2c8..2bdb7b9df 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.963993 # Nu sim_ticks 963992704000 # Number of ticks simulated final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2202720 # Simulator instruction rate (inst/s) -host_tick_rate 1309536712 # Simulator tick rate (ticks/s) -host_mem_usage 204800 # Number of bytes of host memory used -host_seconds 736.13 # Real time elapsed on the host -sim_insts 1621493983 # Number of instructions simulated +host_inst_rate 1632386 # Simulator instruction rate (inst/s) +host_op_rate 3007760 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1788140018 # Simulator tick rate (ticks/s) +host_mem_usage 210284 # Number of bytes of host memory used +host_seconds 539.10 # Real time elapsed on the host +sim_insts 880025313 # Number of instructions simulated +sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11334586825 # Number of bytes read from this memory system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory system.physmem.bytes_written 864451000 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 48 # Nu system.cpu.numCycles 1927985409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1621493983 # Number of instructions executed +system.cpu.committedInsts 880025313 # Number of instructions committed +system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index f841786ec..9097a5047 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index c3d33da65..527d3d172 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:37:10 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:11:10 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 8e512b7b9..308cb734c 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.803259 # Nu sim_ticks 1803258587000 # Number of ticks simulated final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1279975 # Simulator instruction rate (inst/s) -host_tick_rate 1423455894 # Simulator tick rate (ticks/s) -host_mem_usage 213784 # Number of bytes of host memory used -host_seconds 1266.82 # Real time elapsed on the host -sim_insts 1621493983 # Number of instructions simulated +host_inst_rate 972144 # Simulator instruction rate (inst/s) +host_op_rate 1791227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1992018099 # Simulator tick rate (ticks/s) +host_mem_usage 219200 # Number of bytes of host memory used +host_seconds 905.24 # Real time elapsed on the host +sim_insts 880025313 # Number of instructions simulated +sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5725952 # Number of bytes read from this memory system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory system.physmem.bytes_written 3712448 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 48 # Nu system.cpu.numCycles 3606517174 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1621493983 # Number of instructions executed +system.cpu.committedInsts 880025313 # Number of instructions committed +system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 1186516018 # To system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits -system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1186516018 # number of overall hits -system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses -system.cpu.icache.demand_misses 722 # number of demand (read+write) misses -system.cpu.icache.overall_misses 722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits +system.cpu.icache.overall_hits::total 1186516018 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses +system.cpu.icache.overall_misses::total 722 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40432000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40432000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40432000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40432000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40432000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40432000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use @@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 606786134 # To system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits -system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 606786134 # number of overall hits -system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses -system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.896939 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999731 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999731 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 606786134 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 606786134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 606786134 # number of overall hits +system.cpu.dcache.overall_hits::total 606786134 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses +system.cpu.dcache.overall_misses::total 442048 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4043270000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4043270000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5872734000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5872734000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9916004000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9916004000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9916004000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9916004000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 607228182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 607228182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 396372 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks +system.cpu.dcache.writebacks::total 396372 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3451292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3451292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5138568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5138568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8589860000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71208 # number of replacements system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use @@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs 423014 # To system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 353302 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 89468 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16187.723361 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 48.180025 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1821.019706 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.494010 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.055573 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.551054 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 166833 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 166833 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 396372 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 396372 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186469 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186469 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 353302 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 353302 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 353302 # number of overall hits +system.cpu.l2cache.overall_hits::total 353302 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 30493 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 31215 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 58253 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 58253 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 88746 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 89468 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 88746 # number of overall misses +system.cpu.l2cache.overall_misses::total 89468 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1585636000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1623180000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4614792000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4652336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4614792000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4652336000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 396372 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 396372 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 442048 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 442770 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58007 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks +system.cpu.l2cache.writebacks::total 58007 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30493 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58253 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58253 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 88746 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 89468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 88746 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 89468 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1219720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1248600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2330120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2330120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3549840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3578720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index cbe079647..ae17312a7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,14 +508,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 3ae44ae93..bc658a4d7 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:22 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:46:15 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 833e2ce53..0264f97d4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.033081 # Nu sim_ticks 33080570000 # Number of ticks simulated final_tick 33080570000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45520 # Simulator instruction rate (inst/s) -host_tick_rate 16502276 # Simulator tick rate (ticks/s) -host_mem_usage 388968 # Number of bytes of host memory used -host_seconds 2004.61 # Real time elapsed on the host -sim_insts 91249885 # Number of instructions simulated +host_inst_rate 183696 # Simulator instruction rate (inst/s) +host_op_rate 185015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67072888 # Simulator tick rate (ticks/s) +host_mem_usage 356156 # Number of bytes of host memory used +host_seconds 493.20 # Real time elapsed on the host +sim_insts 90599331 # Number of instructions simulated +sim_ops 91249885 # Number of ops (including micro ops) simulated system.physmem.bytes_read 997440 # Number of bytes read from this memory system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 90611940 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262494 # The number of committed instructions system.cpu.commit.commitSquashedInsts 26696996 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle -system.cpu.commit.count 91262494 # Number of instructions committed +system.cpu.commit.committedInsts 90611940 # Number of instructions committed +system.cpu.commit.committedOps 91262494 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 27322621 # Number of memory references committed system.cpu.commit.loads 22575872 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 175546960 # Th system.cpu.rob.rob_writes 239939856 # The number of ROB writes system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 91249885 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated -system.cpu.cpi 0.725055 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.725055 # CPI: Total CPI of All Threads -system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads +system.cpu.committedInsts 90599331 # Number of Instructions Simulated +system.cpu.committedOps 91249885 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599331 # Number of Instructions Simulated +system.cpu.cpi 0.730261 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.730261 # CPI: Total CPI of All Threads +system.cpu.ipc 1.369374 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.369374 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 496902735 # number of integer regfile reads system.cpu.int_regfile_writes 120936098 # number of integer regfile writes system.cpu.fp_regfile_reads 197 # number of floating regfile reads @@ -336,26 +341,39 @@ system.cpu.icache.total_refs 14743811 # To system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 20420.790859 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 611.587679 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 14743811 # number of ReadReq hits -system.cpu.icache.demand_hits 14743811 # number of demand (read+write) hits -system.cpu.icache.overall_hits 14743811 # number of overall hits -system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses -system.cpu.icache.demand_misses 916 # number of demand (read+write) misses -system.cpu.icache.overall_misses 916 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 14744727 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 14744727 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 14744727 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35344.978166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35344.978166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35344.978166 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 611.587679 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.298627 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.298627 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14743811 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14743811 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14743811 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14743811 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14743811 # number of overall hits +system.cpu.icache.overall_hits::total 14743811 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 916 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 916 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 916 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 916 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 916 # number of overall misses +system.cpu.icache.overall_misses::total 916 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32376000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32376000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32376000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32376000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32376000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32376000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14744727 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14744727 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14744727 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14744727 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14744727 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14744727 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000062 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000062 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000062 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35344.978166 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,27 +382,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 194 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 194 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 24887000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 24887000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 24887000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 194 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 194 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 194 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 194 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24887000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24887000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24887000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24887000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24887000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24887000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34469.529086 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 943456 # number of replacements system.cpu.dcache.tagsinuse 3558.808733 # Cycle average of tags in use @@ -392,40 +413,63 @@ system.cpu.dcache.total_refs 28819271 # To system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 30.414448 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3558.808733 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24247440 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 28806682 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 28806682 # number of overall hits -system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1165006 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5475545000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4498707428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 9974252428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9974252428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 25236707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 29971688 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 29971688 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 5534.951636 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 25598.799515 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 8561.545973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 8561.545973 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3558.808733 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.868850 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.868850 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 24247440 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24247440 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4559242 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4559242 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6797 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6797 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5792 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5792 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28806682 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28806682 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28806682 # number of overall hits +system.cpu.dcache.overall_hits::total 28806682 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 989267 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 989267 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 175739 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 175739 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1165006 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1165006 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1165006 # number of overall misses +system.cpu.dcache.overall_misses::total 1165006 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5475545000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5475545000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4498707428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4498707428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 124500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 124500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9974252428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9974252428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9974252428 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9974252428 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 25236707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 25236707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6804 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6804 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5792 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5792 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29971688 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29971688 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29971688 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29971688 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039200 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037115 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001029 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038870 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038870 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5534.951636 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25598.799515 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17785.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked @@ -434,33 +478,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942907 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 86240 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 131213 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 217453 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 217453 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 903027 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 44526 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2253076500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1081063056 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3334139556 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3334139556 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.026727 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.366123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 942907 # number of writebacks +system.cpu.dcache.writebacks::total 942907 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86240 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 86240 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131213 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 131213 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 217453 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 217453 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 217453 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 217453 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903027 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903027 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 44526 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 44526 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947553 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947553 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947553 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947553 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2253076500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2253076500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1081063056 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1081063056 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3334139556 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3334139556 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3334139556 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3334139556 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035782 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009404 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2495.026727 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24279.366123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 744 # number of replacements system.cpu.l2cache.tagsinuse 9229.669691 # Cycle average of tags in use @@ -468,36 +521,75 @@ system.cpu.l2cache.total_refs 1596774 # To system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 392.792276 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8836.877415 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942907 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 31267 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 932680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 932680 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1057 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 14538 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.317389 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34304.071818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34304.071818 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 8836.877415 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 199.760007 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 193.032269 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.269680 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.006096 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24071000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 36209000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 498763000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 498763000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24071000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 510901000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 534972000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24071000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 510901000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 534972000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 901748 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 902470 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942907 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942907 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 45805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 45805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947553 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948275 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947553 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948275 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.972299 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000394 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.317389 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.972299 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015717 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.972299 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015717 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.173789 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34191.549296 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34307.538864 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -506,31 +598,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 32 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1047 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15585 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 32560500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 484338000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 484338000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001160 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016435 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016435 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks +system.cpu.l2cache.writebacks::total 32 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 701 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 346 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1047 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14884 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14884 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15585 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21793500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10767000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32560500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451777500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451777500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21793500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 484338000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21793500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 484338000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000384 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.317389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31089.158345 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31118.497110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31075.629385 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 67a5d19a5..75c90b82c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index 902784594..f67da13a2 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:47:31 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:51:19 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 66ab48bd5..393a58e49 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.054241 # Nu sim_ticks 54240666000 # Number of ticks simulated final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2777644 # Simulator instruction rate (inst/s) -host_tick_rate 1651027932 # Simulator tick rate (ticks/s) -host_mem_usage 342980 # Number of bytes of host memory used -host_seconds 32.85 # Real time elapsed on the host -sim_insts 91252969 # Number of instructions simulated +host_inst_rate 3177444 # Simulator instruction rate (inst/s) +host_op_rate 3200257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1902228216 # Simulator tick rate (ticks/s) +host_mem_usage 345536 # Number of bytes of host memory used +host_seconds 28.51 # Real time elapsed on the host +sim_insts 90602415 # Number of instructions simulated +sim_ops 91252969 # Number of ops (including micro ops) simulated system.physmem.bytes_read 521339715 # Number of bytes read from this memory system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory system.physmem.bytes_written 18908138 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 442 # Nu system.cpu.numCycles 108481333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91252969 # Number of instructions executed +system.cpu.committedInsts 90602415 # Number of instructions committed +system.cpu.committedOps 91252969 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 2f73411a5..14eb2c781 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 959967602..d74925785 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:48:15 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:51:58 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index d6f3be234..27b93150e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.148086 # Nu sim_ticks 148086239000 # Number of ticks simulated final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1300672 # Simulator instruction rate (inst/s) -host_tick_rate 2111359212 # Simulator tick rate (ticks/s) -host_mem_usage 351948 # Number of bytes of host memory used -host_seconds 70.14 # Real time elapsed on the host -sim_insts 91226321 # Number of instructions simulated +host_inst_rate 1696896 # Simulator instruction rate (inst/s) +host_op_rate 1709063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2774293546 # Simulator tick rate (ticks/s) +host_mem_usage 354444 # Number of bytes of host memory used +host_seconds 53.38 # Real time elapsed on the host +sim_insts 90576869 # Number of instructions simulated +sim_ops 91226321 # Number of ops (including micro ops) simulated system.physmem.bytes_read 986112 # Number of bytes read from this memory system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 442 # Nu system.cpu.numCycles 296172478 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91226321 # Number of instructions executed +system.cpu.committedInsts 90576869 # Number of instructions committed +system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 107830181 # To system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits -system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits -system.cpu.icache.overall_hits 107830181 # number of overall hits -system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses -system.cpu.icache.demand_misses 599 # number of demand (read+write) misses -system.cpu.icache.overall_misses 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits +system.cpu.icache.overall_hits::total 107830181 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses +system.cpu.icache.overall_misses::total 599 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 26345365 # To system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26337591 # number of overall hits -system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses -system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits +system.cpu.dcache.overall_hits::total 26337591 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses +system.cpu.dcache.overall_misses::total 946798 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12614490000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12614490000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13878032000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13878032000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13878032000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13878032000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22549408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22549408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27284389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27284389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942309 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks +system.cpu.dcache.writebacks::total 942309 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9913923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9913923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11037638000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 634 # number of replacements system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 1594542 # To system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 899928 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 32061 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 931989 # number of overall hits -system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 14548 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15408 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 756496000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 900788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 8910.209882 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 165.071875 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 160.025936 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.271918 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.005038 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004884 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.281839 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 899907 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 899928 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942309 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942309 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 931968 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 931989 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 931968 # number of overall hits +system.cpu.l2cache.overall_hits::total 931989 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 860 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14830 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15408 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14830 # number of overall misses +system.cpu.l2cache.overall_misses::total 15408 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14664000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 44720000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 771160000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 801216000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 771160000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 801216000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942309 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942309 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 32 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks +system.cpu.l2cache.writebacks::total 32 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 282 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 860 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14830 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14830 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15408 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 593200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 616320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 77055bd16..5d8a4468f 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic +cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout index 18a19b6d7..019979259 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:20:13 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:49 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index e3ffceab4..fc2e52856 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.122216 # Nu sim_ticks 122215830000 # Number of ticks simulated final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3409932 # Simulator instruction rate (inst/s) -host_tick_rate 1709135687 # Simulator tick rate (ticks/s) -host_mem_usage 338176 # Number of bytes of host memory used -host_seconds 71.51 # Real time elapsed on the host -sim_insts 243835278 # Number of instructions simulated +host_inst_rate 4048457 # Simulator instruction rate (inst/s) +host_op_rate 4048623 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2029262264 # Simulator tick rate (ticks/s) +host_mem_usage 335836 # Number of bytes of host memory used +host_seconds 60.23 # Real time elapsed on the host +sim_insts 243825163 # Number of instructions simulated +sim_ops 243835278 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1306360053 # Number of bytes read from this memory system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory system.physmem.bytes_written 91606089 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 443 # Nu system.cpu.numCycles 244431661 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 243835278 # Number of instructions executed +system.cpu.committedInsts 243825163 # Number of instructions committed +system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses system.cpu.num_func_calls 4252956 # number of times a function call or return occured diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index acd41b2d5..ad77524dc 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index ca44a686d..0301a7a93 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:21:35 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:58:00 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 7dc591cfe..14199b227 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.362431 # Nu sim_ticks 362430887000 # Number of ticks simulated final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1587659 # Simulator instruction rate (inst/s) -host_tick_rate 2359857170 # Simulator tick rate (ticks/s) -host_mem_usage 346888 # Number of bytes of host memory used -host_seconds 153.58 # Real time elapsed on the host -sim_insts 243835278 # Number of instructions simulated +host_inst_rate 1947938 # Simulator instruction rate (inst/s) +host_op_rate 1948018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2895487158 # Simulator tick rate (ticks/s) +host_mem_usage 344700 # Number of bytes of host memory used +host_seconds 125.17 # Real time elapsed on the host +sim_insts 243825163 # Number of instructions simulated +sim_ops 243835278 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1001472 # Number of bytes read from this memory system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory system.physmem.bytes_written 2560 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 443 # Nu system.cpu.numCycles 724861774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 243835278 # Number of instructions executed +system.cpu.committedInsts 243825163 # Number of instructions committed +system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses system.cpu.num_func_calls 4252956 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 244420630 # To system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits -system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits -system.cpu.icache.overall_hits 244420630 # number of overall hits -system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses -system.cpu.icache.demand_misses 882 # number of demand (read+write) misses -system.cpu.icache.overall_misses 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 49266000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 49266000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 49266000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55857.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55857.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits +system.cpu.icache.overall_hits::total 244420630 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses +system.cpu.icache.overall_misses::total 882 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 46620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 46620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 46620000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use @@ -102,38 +116,59 @@ system.cpu.dcache.total_refs 104186700 # To system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 22855241 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits 104182818 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 104182818 # number of overall hits -system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 46710 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses -system.cpu.dcache.demand_misses 939567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 12508482000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 1265712000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 98000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 13774194000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13774194000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.008938 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 24500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14660.150899 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits +system.cpu.dcache.overall_hits::total 104182818 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses +system.cpu.dcache.overall_misses::total 939567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 935237 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 46710 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 939567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 9829911000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 10955493000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 10955493000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 21500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks +system.cpu.dcache.writebacks::total 935237 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 865 # number of replacements system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use @@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs 1585884 # To system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 892658 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 935237 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 32147 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 924805 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 924805 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 14567 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15648 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15648 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 56212000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 757484000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 813696000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 813696000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 935237 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.311834 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016639 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016639 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits +system.cpu.l2cache.overall_hits::total 924805 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses +system.cpu.l2cache.overall_misses::total 15648 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 40 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 14567 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15648 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15648 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 582680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 625920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 625920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311834 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016639 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016639 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks +system.cpu.l2cache.writebacks::total 40 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 546611c4c..f9591bc5c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,14 +510,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 1c8484fc7..90035090e 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:13:01 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 0040f922c..1bd6324e3 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.070047 # Nu sim_ticks 70046988500 # Number of ticks simulated final_tick 70046988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78701 # Simulator instruction rate (inst/s) -host_tick_rate 19816485 # Simulator tick rate (ticks/s) -host_mem_usage 388420 # Number of bytes of host memory used -host_seconds 3534.78 # Real time elapsed on the host -sim_insts 278192519 # Number of instructions simulated +host_inst_rate 120922 # Simulator instruction rate (inst/s) +host_op_rate 212925 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53613076 # Simulator tick rate (ticks/s) +host_mem_usage 355612 # Number of bytes of host memory used +host_seconds 1306.53 # Real time elapsed on the host +sim_insts 157988582 # Number of instructions simulated +sim_ops 278192519 # Number of ops (including micro ops) simulated system.physmem.bytes_read 3895936 # Number of bytes read from this memory system.physmem.bytes_inst_read 65216 # Number of instructions bytes read from this memory system.physmem.bytes_written 892288 # Number of bytes written to this memory @@ -236,7 +238,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 2.229177 # insts written-back per cycle system.cpu.iew.wb_fanout 0.730584 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions +system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions system.cpu.commit.commitSquashedInsts 65103374 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1332005 # The number of times a branch was mispredicted @@ -257,7 +260,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 130436298 # Number of insts commited each cycle -system.cpu.commit.count 278192519 # Number of instructions committed +system.cpu.commit.committedInsts 157988582 # Number of instructions committed +system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed system.cpu.commit.loads 90779388 # Number of loads committed @@ -272,12 +276,13 @@ system.cpu.rob.rob_reads 457952368 # Th system.cpu.rob.rob_writes 695479183 # The number of ROB writes system.cpu.timesIdled 23894 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 787486 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 278192519 # Number of Instructions Simulated -system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.503586 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.503586 # CPI: Total CPI of All Threads -system.cpu.ipc 1.985756 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.985756 # IPC: Total IPC of All Threads +system.cpu.committedInsts 157988582 # Number of Instructions Simulated +system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated +system.cpu.cpi 0.886735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.886735 # CPI: Total CPI of All Threads +system.cpu.ipc 1.127733 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.127733 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 554395898 # number of integer regfile reads system.cpu.int_regfile_writes 279799467 # number of integer regfile writes system.cpu.fp_regfile_reads 352 # number of floating regfile reads @@ -289,26 +294,39 @@ system.cpu.icache.total_refs 28212585 # To system.cpu.icache.sampled_refs 1024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 27551.352539 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 822.534021 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.401628 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28212585 # number of ReadReq hits -system.cpu.icache.demand_hits 28212585 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28212585 # number of overall hits -system.cpu.icache.ReadReq_misses 1300 # number of ReadReq misses -system.cpu.icache.demand_misses 1300 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1300 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 46952500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 46952500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 46952500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28213885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28213885 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28213885 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36117.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36117.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36117.307692 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 822.534021 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.401628 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.401628 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 28212585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 28212585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 28212585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 28212585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 28212585 # number of overall hits +system.cpu.icache.overall_hits::total 28212585 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1300 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1300 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1300 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1300 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1300 # number of overall misses +system.cpu.icache.overall_misses::total 1300 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 46952500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 46952500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 46952500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 46952500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 46952500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 46952500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 28213885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 28213885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 28213885 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 28213885 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 28213885 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 28213885 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000046 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000046 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000046 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1025 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1025 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1025 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 36071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 36071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 36071500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.707317 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 275 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 275 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 275 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 275 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1025 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1025 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1025 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1025 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36071500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36071500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36071500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35191.707317 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2072906 # number of replacements system.cpu.dcache.tagsinuse 4073.029614 # Cycle average of tags in use @@ -345,32 +366,49 @@ system.cpu.dcache.total_refs 77489413 # To system.cpu.dcache.sampled_refs 2077002 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 37.308300 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 23588256000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4073.029614 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 46135653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31353751 # number of WriteReq hits -system.cpu.dcache.demand_hits 77489404 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 77489404 # number of overall hits -system.cpu.dcache.ReadReq_misses 2289012 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 86000 # number of WriteReq misses -system.cpu.dcache.demand_misses 2375012 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2375012 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 13766771000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 1501245288 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 15268016288 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 15268016288 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 48424665 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 79864416 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 79864416 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.047270 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002735 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.029738 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.029738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6014.285203 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17456.340558 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 6428.605956 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 6428.605956 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4073.029614 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994392 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994392 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 46135653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46135653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31353751 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31353751 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77489404 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77489404 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77489404 # number of overall hits +system.cpu.dcache.overall_hits::total 77489404 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2289012 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2289012 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 86000 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 86000 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2375012 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2375012 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2375012 # number of overall misses +system.cpu.dcache.overall_misses::total 2375012 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13766771000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13766771000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1501245288 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1501245288 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15268016288 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15268016288 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15268016288 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15268016288 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48424665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48424665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 79864416 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 79864416 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 79864416 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 79864416 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047270 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002735 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.029738 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029738 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6014.285203 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17456.340558 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1880780 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 294089 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3918 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 298007 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 298007 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1994923 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 82082 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2077005 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2077005 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5565133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1157645788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6722779288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6722779288 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.041196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2789.648272 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14103.528033 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3236.766059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3236.766059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1880780 # number of writebacks +system.cpu.dcache.writebacks::total 1880780 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 294089 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 294089 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3918 # 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mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2789.648272 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14103.528033 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 33246 # number of replacements system.cpu.l2cache.tagsinuse 18964.988080 # Cycle average of tags in use @@ -412,39 +458,80 @@ system.cpu.l2cache.total_refs 3764517 # To system.cpu.l2cache.sampled_refs 61253 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 61.458492 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6037.038666 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12927.949414 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.184236 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.394530 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1964445 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1880780 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 52709 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2017154 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2017154 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31361 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 34913500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2042479000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2077392500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1024 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994782 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995806 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1880780 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1880780 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82222 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995117 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.028818 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995117 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.028818 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34262.512267 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.615451 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34093.111510 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,34 +540,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 13942 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31361 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 29513 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 60874 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 60874 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 972854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 914925500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 1887779500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 1887779500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.015713 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.358943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.029294 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.029294 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.140907 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.762376 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.260965 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.260965 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 13942 # number of writebacks +system.cpu.l2cache.writebacks::total 13942 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30342 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31361 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29513 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29513 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 59855 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 60874 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 59855 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 60874 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31643000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941211000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 972854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 914925500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 914925500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31643000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1887779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31643000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1887779500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358943 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 96706c5cc..15b801d93 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index eb189c10a..a3234c831 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:52:52 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:18:06 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index e99e16cd0..e6ec29e4a 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.168950 # Nu sim_ticks 168950072000 # Number of ticks simulated final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2042288 # Simulator instruction rate (inst/s) -host_tick_rate 1240309006 # Simulator tick rate (ticks/s) -host_mem_usage 339312 # Number of bytes of host memory used -host_seconds 136.22 # Real time elapsed on the host -sim_insts 278192520 # Number of instructions simulated +host_inst_rate 1605694 # Simulator instruction rate (inst/s) +host_op_rate 2827368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1717098424 # Simulator tick rate (ticks/s) +host_mem_usage 344660 # Number of bytes of host memory used +host_seconds 98.39 # Real time elapsed on the host +sim_insts 157988583 # Number of instructions simulated +sim_ops 278192520 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2458815679 # Number of bytes read from this memory system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory system.physmem.bytes_written 243173115 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 444 # Nu system.cpu.numCycles 337900145 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 278192520 # Number of instructions executed +system.cpu.committedInsts 157988583 # Number of instructions committed +system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 008adeebb..426472e17 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index e89b51a20..064d05227 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:55:19 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:19:55 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 59ae818d2..a57ebe258 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.370011 # Nu sim_ticks 370010840000 # Number of ticks simulated final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1163147 # Simulator instruction rate (inst/s) -host_tick_rate 1547047043 # Simulator tick rate (ticks/s) -host_mem_usage 348152 # Number of bytes of host memory used -host_seconds 239.17 # Real time elapsed on the host -sim_insts 278192520 # Number of instructions simulated +host_inst_rate 912216 # Simulator instruction rate (inst/s) +host_op_rate 1606265 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2136418129 # Simulator tick rate (ticks/s) +host_mem_usage 353708 # Number of bytes of host memory used +host_seconds 173.19 # Real time elapsed on the host +sim_insts 157988583 # Number of instructions simulated +sim_ops 278192520 # Number of ops (including micro ops) simulated system.physmem.bytes_read 4900800 # Number of bytes read from this memory system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory system.physmem.bytes_written 1885440 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 444 # Nu system.cpu.numCycles 740021680 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 278192520 # Number of instructions executed +system.cpu.committedInsts 157988583 # Number of instructions committed +system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 217695401 # To system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits -system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits -system.cpu.icache.overall_hits 217695401 # number of overall hits -system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses -system.cpu.icache.demand_misses 808 # number of demand (read+write) misses -system.cpu.icache.overall_misses 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits +system.cpu.icache.overall_hits::total 217695401 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses +system.cpu.icache.overall_misses::total 808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use @@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 120152372 # To system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits -system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 120152372 # number of overall hits -system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses -system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits +system.cpu.dcache.overall_hits::total 120152372 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses +system.cpu.dcache.overall_misses::total 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1437080 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks +system.cpu.dcache.writebacks::total 1437080 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22966898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22966898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2950464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2950464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25917362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 49212 # number of replacements system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use @@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs 3296079 # To system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1991062 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76575 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 12062.804989 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 196.794797 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6355.003474 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.368128 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.006006 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.193939 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.568073 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 1927411 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1927411 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1437080 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1437080 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 63651 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 63651 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 1991062 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1991062 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 1991062 # number of overall hits +system.cpu.l2cache.overall_hits::total 1991062 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 33309 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 34117 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 42458 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 42458 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 75767 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 76575 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 75767 # number of overall misses +system.cpu.l2cache.overall_misses::total 76575 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1732068000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1774084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2207845500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2207845500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3939913500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3981929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3939913500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3981929500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1437080 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1437080 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29460 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks +system.cpu.l2cache.writebacks::total 29460 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 0436eab53..0afad448e 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,14 +508,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index cc61bb6b6..f2e7dd662 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:20 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:53:02 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c0ee61c5b..de8607854 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.274128 # Nu sim_ticks 274128411000 # Number of ticks simulated final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67477 # Simulator instruction rate (inst/s) -host_tick_rate 32262353 # Simulator tick rate (ticks/s) -host_mem_usage 260864 # Number of bytes of host memory used -host_seconds 8496.85 # Real time elapsed on the host -sim_insts 573341187 # Number of instructions simulated +host_inst_rate 133293 # Simulator instruction rate (inst/s) +host_op_rate 150155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71792865 # Simulator tick rate (ticks/s) +host_mem_usage 228092 # Number of bytes of host memory used +host_seconds 3818.32 # Real time elapsed on the host +sim_insts 508954626 # Number of instructions simulated +sim_ops 573341187 # Number of ops (including micro ops) simulated system.physmem.bytes_read 15240192 # Number of bytes read from this memory system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory system.physmem.bytes_written 10959680 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 574685071 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 510298510 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685071 # The number of committed instructions system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle -system.cpu.commit.count 574685071 # Number of instructions committed +system.cpu.commit.committedInsts 510298510 # Number of instructions committed +system.cpu.commit.committedOps 574685071 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 184376791 # Number of memory references committed system.cpu.commit.loads 126772935 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 1367535962 # Th system.cpu.rob.rob_writes 1823647630 # The number of ROB writes system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 573341187 # Number of Instructions Simulated -system.cpu.committedInsts_total 573341187 # Number of Instructions Simulated -system.cpu.cpi 0.956249 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.956249 # CPI: Total CPI of All Threads -system.cpu.ipc 1.045753 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.045753 # IPC: Total IPC of All Threads +system.cpu.committedInsts 508954626 # Number of Instructions Simulated +system.cpu.committedOps 573341187 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508954626 # Number of Instructions Simulated +system.cpu.cpi 1.077221 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.077221 # CPI: Total CPI of All Threads +system.cpu.ipc 0.928314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.928314 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads system.cpu.int_regfile_writes 815117578 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads @@ -335,26 +340,39 @@ system.cpu.icache.total_refs 141602716 # To system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1062.179544 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.518642 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 141602717 # number of ReadReq hits -system.cpu.icache.demand_hits 141602717 # number of demand (read+write) hits -system.cpu.icache.overall_hits 141602717 # number of overall hits -system.cpu.icache.ReadReq_misses 16509 # number of ReadReq misses -system.cpu.icache.demand_misses 16509 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16509 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 235489500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 235489500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 235489500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 141619226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 141619226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 141619226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000117 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 14264.310376 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 14264.310376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 14264.310376 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1062.179544 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.518642 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.518642 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 141602717 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 141602717 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 141602717 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 141602717 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 141602717 # number of overall hits +system.cpu.icache.overall_hits::total 141602717 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16509 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16509 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16509 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16509 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16509 # number of overall misses +system.cpu.icache.overall_misses::total 16509 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 235489500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 235489500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 235489500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 235489500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 235489500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 235489500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 141619226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 141619226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 141619226 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 141619226 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 141619226 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 141619226 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000117 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000117 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000117 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14264.310376 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,27 +381,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1646 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1646 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1646 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 14863 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 14863 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 14863 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 154537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 154537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 154537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10397.429859 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1646 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1646 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1646 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1646 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1646 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1646 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 14863 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 14863 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 14863 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 14863 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 14863 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 14863 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 154537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 154537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 154537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154537000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 154537000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10397.429859 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1212291 # number of replacements system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use @@ -391,40 +414,63 @@ system.cpu.dcache.total_refs 203801196 # To system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4058.220860 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.990777 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 146308743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 52772298 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2488014 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 2231920 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 199081041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 199081041 # number of overall hits -system.cpu.dcache.ReadReq_misses 1241922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1467008 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2708930 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2708930 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14257023500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 24962643993 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 523000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 39219667493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39219667493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 147550665 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 2488069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 2231920 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 201789971 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 201789971 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.008417 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.027047 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.013425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 11479.805898 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17016.024448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 9509.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14477.918401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14477.918401 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4058.220860 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990777 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990777 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 146308743 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146308743 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52772298 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52772298 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2488014 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2488014 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2231920 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2231920 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 199081041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 199081041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 199081041 # number of overall hits +system.cpu.dcache.overall_hits::total 199081041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1241922 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1241922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1467008 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1467008 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 55 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 55 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2708930 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2708930 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2708930 # number of overall misses +system.cpu.dcache.overall_misses::total 2708930 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14257023500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14257023500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24962643993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24962643993 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 523000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 523000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39219667493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39219667493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39219667493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39219667493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 147550665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 147550665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2488069 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2488069 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231920 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2231920 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201789971 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201789971 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201789971 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201789971 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008417 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027047 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000022 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013425 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013425 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11479.805898 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17016.024448 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9509.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 484000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,33 +479,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 7934.426230 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1079423 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 365990 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1126420 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1492410 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1492410 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 875932 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 340588 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1216520 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1216520 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 6305474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4364186500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 10669660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 10669660500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005936 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006279 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006029 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7198.588475 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12813.682514 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8770.641255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8770.641255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1079423 # number of writebacks +system.cpu.dcache.writebacks::total 1079423 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365990 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277841000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7389367500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111526500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277841000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7389367500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144048 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.267176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.859493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31048.453853 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.273152 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index cbe7d05b4..4fff23cb4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index e26a927e8..2e77896ee 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:54:41 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:54:26 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 12a51d6fd..52a899319 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.290499 # Nu sim_ticks 290498972000 # Number of ticks simulated final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3123764 # Simulator instruction rate (inst/s) -host_tick_rate 1589318228 # Simulator tick rate (ticks/s) -host_mem_usage 213568 # Number of bytes of host memory used -host_seconds 182.78 # Real time elapsed on the host -sim_insts 570968176 # Number of instructions simulated +host_inst_rate 2958479 # Simulator instruction rate (inst/s) +host_op_rate 3334501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1696537892 # Simulator tick rate (ticks/s) +host_mem_usage 216124 # Number of bytes of host memory used +host_seconds 171.23 # Real time elapsed on the host +sim_insts 506581615 # Number of instructions simulated +sim_ops 570968176 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2489298238 # Number of bytes read from this memory system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory system.physmem.bytes_written 216067624 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 548 # Nu system.cpu.numCycles 580997945 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 570968176 # Number of instructions executed +system.cpu.committedInsts 506581615 # Number of instructions committed +system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 15725605 # number of times a function call or return occured diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 5a2d86232..4d41782e0 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 8c1353073..3a1edbeaa 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:54:55 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:54:39 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index f9d747bd5..d73359a08 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.722234 # Nu sim_ticks 722234364000 # Number of ticks simulated final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1518630 # Simulator instruction rate (inst/s) -host_tick_rate 1927485562 # Simulator tick rate (ticks/s) -host_mem_usage 222536 # Number of bytes of host memory used -host_seconds 374.70 # Real time elapsed on the host -sim_insts 569034848 # Number of instructions simulated +host_inst_rate 1769028 # Simulator instruction rate (inst/s) +host_op_rate 1993395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2530070907 # Simulator tick rate (ticks/s) +host_mem_usage 225284 # Number of bytes of host memory used +host_seconds 285.46 # Real time elapsed on the host +sim_insts 504986861 # Number of instructions simulated +sim_ops 569034848 # Number of ops (including micro ops) simulated system.physmem.bytes_read 14797056 # Number of bytes read from this memory system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory system.physmem.bytes_written 11027328 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 548 # Nu system.cpu.numCycles 1444468728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 569034848 # Number of instructions executed +system.cpu.committedInsts 504986861 # Number of instructions committed +system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 15725605 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 516599864 # To system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits -system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits -system.cpu.icache.overall_hits 516599864 # number of overall hits -system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses -system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits +system.cpu.icache.overall_hits::total 516599864 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses +system.cpu.icache.overall_misses::total 11521 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 179817787 # To system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 176840705 # number of overall hits -system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses -system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits +system.cpu.dcache.overall_hits::total 176840705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses +system.cpu.dcache.overall_misses::total 1138918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1025440 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks +system.cpu.dcache.writebacks::total 1025440 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 212089 # number of replacements system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 1426644 # To system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 919235 # number of overall hits -system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 231204 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits +system.cpu.l2cache.overall_hits::total 919235 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses +system.cpu.l2cache.overall_misses::total 231204 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 172302 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks +system.cpu.l2cache.writebacks::total 172302 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 8f133335a..9b1d88e31 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,14 +510,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 1d5281a91..a99eb01f1 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:22:59 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 6f075b675..e2e62743e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.488026 # Nu sim_ticks 488026375000 # Number of ticks simulated final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87795 # Simulator instruction rate (inst/s) -host_tick_rate 28022613 # Simulator tick rate (ticks/s) -host_mem_usage 289796 # Number of bytes of host memory used -host_seconds 17415.45 # Real time elapsed on the host -sim_insts 1528988756 # Number of instructions simulated +host_inst_rate 101458 # Simulator instruction rate (inst/s) +host_op_rate 187607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59880945 # Simulator tick rate (ticks/s) +host_mem_usage 257144 # Number of bytes of host memory used +host_seconds 8149.94 # Real time elapsed on the host +sim_insts 826877144 # Number of instructions simulated +sim_ops 1528988756 # Number of ops (including micro ops) simulated system.physmem.bytes_read 37539712 # Number of bytes read from this memory system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory system.physmem.bytes_written 26338560 # Number of bytes written to this memory @@ -238,7 +240,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted @@ -259,7 +262,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle -system.cpu.commit.count 1528988756 # Number of instructions committed +system.cpu.commit.committedInsts 826877144 # Number of instructions committed +system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed system.cpu.commit.loads 384102160 # Number of loads committed @@ -274,12 +278,13 @@ system.cpu.rob.rob_reads 3076935822 # Th system.cpu.rob.rob_writes 4651204201 # The number of ROB writes system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1528988756 # Number of Instructions Simulated -system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.638365 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.638365 # CPI: Total CPI of All Threads -system.cpu.ipc 1.566502 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.566502 # IPC: Total IPC of All Threads +system.cpu.committedInsts 826877144 # Number of Instructions Simulated +system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated +system.cpu.cpi 1.180408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.180408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.847164 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.847164 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes system.cpu.fp_regfile_reads 120 # number of floating regfile reads @@ -290,26 +295,39 @@ system.cpu.icache.total_refs 193659156 # To system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 973.820201 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.475498 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 193665655 # number of ReadReq hits -system.cpu.icache.demand_hits 193665655 # number of demand (read+write) hits -system.cpu.icache.overall_hits 193665655 # number of overall hits -system.cpu.icache.ReadReq_misses 234749 # number of ReadReq misses -system.cpu.icache.demand_misses 234749 # number of demand (read+write) misses -system.cpu.icache.overall_misses 234749 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1699920500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1699920500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1699920500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 193900404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 193900404 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 193900404 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001211 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001211 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001211 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 7241.438728 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 7241.438728 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 7241.438728 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 973.820201 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.475498 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.475498 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 193665655 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 193665655 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 193665655 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 193665655 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 193665655 # number of overall hits +system.cpu.icache.overall_hits::total 193665655 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 234749 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 234749 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 234749 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 234749 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 234749 # number of overall misses +system.cpu.icache.overall_misses::total 234749 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1699920500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1699920500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1699920500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1699920500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1699920500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1699920500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 193900404 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 193900404 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 193900404 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 193900404 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 193900404 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 193900404 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001211 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001211 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001211 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7241.438728 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -318,27 +336,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2040 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2040 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2040 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 232709 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 232709 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 232709 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 952455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 952455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 952455000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001200 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001200 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001200 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4092.901435 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 4 # number of writebacks +system.cpu.icache.writebacks::total 4 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2040 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2040 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2040 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2040 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2040 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2040 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 232709 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 232709 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 232709 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 232709 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 232709 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 232709 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 952455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 952455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 952455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 952455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 952455000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 952455000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4092.901435 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4092.901435 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4092.901435 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2529316 # number of replacements system.cpu.dcache.tagsinuse 4087.520068 # Cycle average of tags in use @@ -346,32 +369,49 @@ system.cpu.dcache.total_refs 427611101 # To system.cpu.dcache.sampled_refs 2533412 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 168.788614 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 2115074000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.520068 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 278887188 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 148162157 # number of WriteReq hits -system.cpu.dcache.demand_hits 427049345 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 427049345 # number of overall hits -system.cpu.dcache.ReadReq_misses 2665882 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 998044 # number of WriteReq misses -system.cpu.dcache.demand_misses 3663926 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 3663926 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 39487902000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20586128000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 60074030000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 60074030000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 281553070 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 430713271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 430713271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.009468 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006691 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.008507 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14812.321776 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 20626.473382 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 16396.081689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 16396.081689 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4087.520068 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 278887188 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 278887188 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148162157 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148162157 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 427049345 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 427049345 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 427049345 # number of overall hits +system.cpu.dcache.overall_hits::total 427049345 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2665882 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2665882 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 998044 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 998044 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3663926 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3663926 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3663926 # number of overall misses +system.cpu.dcache.overall_misses::total 3663926 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39487902000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39487902000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20586128000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20586128000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 60074030000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 60074030000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 60074030000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 60074030000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 281553070 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 281553070 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 430713271 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 430713271 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 430713271 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 430713271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009468 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006691 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008507 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008507 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14812.321776 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20626.473382 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,32 +420,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229932 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 902993 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 909446 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 909446 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1762889 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 991591 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2754480 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2754480 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14966916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 17535799000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32502715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32502715500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.006261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006648 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006395 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006395 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8489.993698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17684.508028 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 2229932 # number of writebacks +system.cpu.dcache.writebacks::total 2229932 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902993 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 902993 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6453 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 909446 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 909446 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 909446 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 909446 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762889 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762889 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 991591 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 991591 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2754480 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2754480 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2754480 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2754480 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14966916500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14966916500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17535799000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17535799000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32502715500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32502715500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32502715500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32502715500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006261 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006648 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8489.993698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17684.508028 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 575774 # number of replacements system.cpu.l2cache.tagsinuse 21621.732877 # Cycle average of tags in use @@ -413,42 +461,85 @@ system.cpu.l2cache.total_refs 3195554 # To system.cpu.l2cache.sampled_refs 594946 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 5.371166 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 268816776000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7838.250700 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13783.482177 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.239204 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.420638 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1434280 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229936 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1289 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 524029 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1958309 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1958309 # number of overall hits -system.cpu.l2cache.ReadReq_misses 339456 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 219771 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247125 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 586581 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 586581 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11594725000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 9650000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8467808500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20062533500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20062533500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1773736 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229936 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 221060 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 771154 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2544890 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2544890 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191379 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994169 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.320461 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230494 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230494 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34156.783206 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 43.909342 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34265.284775 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34202.494626 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34202.494626 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 13783.482177 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 57.596580 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7780.654120 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.420638 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001758 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.237447 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.659843 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6132 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1428148 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1434280 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2229936 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2229936 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1289 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1289 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 524029 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 524029 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 6132 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1952177 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1958309 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6132 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1952177 # number of overall hits +system.cpu.l2cache.overall_hits::total 1958309 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 5424 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 334032 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 339456 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 219771 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 219771 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 247125 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 247125 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5424 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 581157 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 586581 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5424 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 581157 # number of overall misses +system.cpu.l2cache.overall_misses::total 586581 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 185788500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11408936500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11594725000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9650000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 9650000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8467808500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8467808500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 185788500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19876745000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20062533500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 185788500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19876745000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20062533500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11556 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762180 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1773736 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2229936 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2229936 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 221060 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 221060 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771154 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771154 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11556 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533334 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544890 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11556 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533334 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544890 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.469367 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189556 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994169 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320461 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469367 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229404 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469367 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229404 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.042035 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34155.220159 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 43.909342 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34265.284775 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -457,34 +548,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 411540 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 339456 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 219771 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247125 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 586581 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 586581 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10530013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6813351000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7661828500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18191842000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18191842000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191379 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994169 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320461 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.260358 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.047586 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.858371 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 411540 # number of writebacks +system.cpu.l2cache.writebacks::total 411540 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 334032 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 339456 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 219771 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 219771 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247125 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 247125 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 581157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 586581 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 581157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 586581 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168319500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10361694000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10530013500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6813351000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6813351000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7661828500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7661828500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168319500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18023522500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18191842000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168319500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18023522500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18191842000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189556 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994169 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320461 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31032.356195 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.063946 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31002.047586 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31003.858371 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index b1057156b..304b98194 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index b86175ab2..80f8eeac5 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:59:28 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:26:26 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 4e0a10e13..8da8b6e9b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.885229 # Nu sim_ticks 885229360000 # Number of ticks simulated final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2258239 # Simulator instruction rate (inst/s) -host_tick_rate 1307438877 # Simulator tick rate (ticks/s) -host_mem_usage 208528 # Number of bytes of host memory used -host_seconds 677.07 # Real time elapsed on the host -sim_insts 1528988757 # Number of instructions simulated +host_inst_rate 1663979 # Simulator instruction rate (inst/s) +host_op_rate 3076883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1781404357 # Simulator tick rate (ticks/s) +host_mem_usage 214024 # Number of bytes of host memory used +host_seconds 496.93 # Real time elapsed on the host +sim_insts 826877145 # Number of instructions simulated +sim_ops 1528988757 # Number of ops (including micro ops) simulated system.physmem.bytes_read 10832432532 # Number of bytes read from this memory system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory system.physmem.bytes_written 991849460 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 551 # Nu system.cpu.numCycles 1770458721 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1528988757 # Number of instructions executed +system.cpu.committedInsts 826877145 # Number of instructions committed +system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index c570a48d2..36ec559e8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index a297c4bc8..a07142e7a 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 07:10:56 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:34:54 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 28d09902a..aa053a273 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.658730 # Nu sim_ticks 1658729604000 # Number of ticks simulated final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1326745 # Simulator instruction rate (inst/s) -host_tick_rate 1439324936 # Simulator tick rate (ticks/s) -host_mem_usage 217512 # Number of bytes of host memory used -host_seconds 1152.44 # Real time elapsed on the host -sim_insts 1528988757 # Number of instructions simulated +host_inst_rate 1021382 # Simulator instruction rate (inst/s) +host_op_rate 1888649 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2048908881 # Simulator tick rate (ticks/s) +host_mem_usage 222932 # Number of bytes of host memory used +host_seconds 809.57 # Real time elapsed on the host +sim_insts 826877145 # Number of instructions simulated +sim_ops 1528988757 # Number of ops (including micro ops) simulated system.physmem.bytes_read 37094976 # Number of bytes read from this memory system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory system.physmem.bytes_written 26349376 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 551 # Nu system.cpu.numCycles 3317459208 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1528988757 # Number of instructions executed +system.cpu.committedInsts 826877145 # Number of instructions committed +system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 1068344296 # To system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits -system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1068344296 # number of overall hits -system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses -system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses -system.cpu.icache.overall_misses 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 882.231489 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.430777 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.430777 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits +system.cpu.icache.overall_hits::total 1068344296 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses +system.cpu.icache.overall_misses::total 2814 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 136878000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 136878000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 136878000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 136878000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 136878000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use @@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 530743932 # To system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits -system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 530743932 # number of overall hits -system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses -system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997674 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997674 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits +system.cpu.dcache.overall_hits::total 530743932 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses +system.cpu.dcache.overall_misses::total 2518458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38012508000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38012508000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21492013500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21492013500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 59504521500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 59504521500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 59504521500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 59504521500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2223170 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 2223170 # number of writebacks +system.cpu.dcache.writebacks::total 2223170 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32830264000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 568906 # number of replacements system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use @@ -167,36 +200,75 @@ system.cpu.l2cache.total_refs 3146531 # To system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1398652 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 30.006309 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7519.122292 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.417452 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000916 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.229465 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.647833 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 493 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1398159 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1398652 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2223170 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2223170 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 543011 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks +system.cpu.l2cache.writebacks::total 411709 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 331576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 248033 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 248033 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index 16e4d1756..2ad80ff6d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index 1c2a18294..b600ef537 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:43 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index a04efd18a..58ea20ddf 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.139995 # Nu sim_ticks 139995113500 # Number of ticks simulated final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118986 # Simulator instruction rate (inst/s) -host_tick_rate 41783300 # Simulator tick rate (ticks/s) -host_mem_usage 214012 # Number of bytes of host memory used -host_seconds 3350.50 # Real time elapsed on the host +host_inst_rate 154307 # Simulator instruction rate (inst/s) +host_op_rate 154307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54186341 # Simulator tick rate (ticks/s) +host_mem_usage 215920 # Number of bytes of host memory used +host_seconds 2583.59 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated +sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read 469184 # Number of bytes read from this memory system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -68,9 +70,10 @@ system.cpu.comNops 23089775 # Nu system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed system.cpu.comInts 112239074 # Number of Integer instructions committed system.cpu.comFloats 50439198 # Number of Floating Point instructions committed -system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads @@ -124,26 +127,39 @@ system.cpu.icache.total_refs 48855472 # To system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1829.847469 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.893480 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 48855472 # number of ReadReq hits -system.cpu.icache.demand_hits 48855472 # number of demand (read+write) hits -system.cpu.icache.overall_hits 48855472 # number of overall hits -system.cpu.icache.ReadReq_misses 4376 # number of ReadReq misses -system.cpu.icache.demand_misses 4376 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4376 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 214318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 214318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 214318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 48859848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 48859848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 48859848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000090 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000090 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000090 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 48975.891225 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 48975.891225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 48975.891225 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1829.847469 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893480 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893480 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48855472 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48855472 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48855472 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48855472 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48855472 # number of overall hits +system.cpu.icache.overall_hits::total 48855472 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4376 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4376 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4376 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4376 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4376 # number of overall misses +system.cpu.icache.overall_misses::total 4376 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214318500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214318500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214318500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214318500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214318500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214318500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48859848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48859848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48859848 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48859848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48859848 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48859848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000090 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000090 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000090 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48975.891225 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 479 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 479 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 185285000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 185285000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 185285000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3897 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3897 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3897 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3897 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3897 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3897 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185285000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 185285000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185285000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 185285000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185285000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 185285000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47545.547857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use @@ -180,32 +199,49 @@ system.cpu.dcache.total_refs 168261959 # To system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3284.892021 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.801976 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 94753265 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73508694 # number of WriteReq hits -system.cpu.dcache.demand_hits 168261959 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 168261959 # number of overall hits -system.cpu.dcache.ReadReq_misses 1224 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 12035 # number of WriteReq misses -system.cpu.dcache.demand_misses 13259 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 63830500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 626731500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 690562000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 690562000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 52082.509993 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 52082.509993 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3284.892021 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73508694 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73508694 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168261959 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168261959 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168261959 # number of overall hits +system.cpu.dcache.overall_hits::total 168261959 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 12035 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 12035 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 13259 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses +system.cpu.dcache.overall_misses::total 13259 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63830500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63830500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 626731500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 626731500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 690562000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 690562000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 690562000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 690562000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52149.101307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52075.737432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,32 +250,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 274 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 8833 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 9107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 9107 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 46185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 169537500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215722500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215722500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8833 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8833 # number of WriteReq MSHR hits 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+system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 46185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215722500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215722500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215722500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215722500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48615.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.376640 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51956.286127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51956.286127 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3900.004949 # Cycle average of tags in use @@ -247,36 +291,75 @@ system.cpu.l2cache.total_refs 729 # To system.cpu.l2cache.sampled_refs 4720 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.154449 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3529.472340 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 370.532609 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107711 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 658 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 718 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 718 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4186 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7331 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 219209500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 164966000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 384175500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 384175500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4844 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8049 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8049 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.864162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.910796 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.910796 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52404.242259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52404.242259 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 370.532609 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2905.642885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 623.829454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088673 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019038 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119019 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 541 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 658 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 541 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 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cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 175581500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208594000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 384175500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3897 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4844 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3897 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8049 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3897 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8049 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.861175 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.861175 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.861175 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.682956 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52563.855422 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52453.418124 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -285,30 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4186 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7331 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7331 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 168226500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 126764000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 294990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 294990500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.910796 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.910796 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3356 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4186 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3356 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3356 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7331 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134709500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168226500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126764000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126764000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134709500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160281000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 294990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134709500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160281000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 294990500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 0fce2844b..c359a496a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 137fd0ee8..d3938f090 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:45 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 28785f469..e5ff3033e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.089480 # Nu sim_ticks 89480174500 # Number of ticks simulated final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190161 # Simulator instruction rate (inst/s) -host_tick_rate 45305657 # Simulator tick rate (ticks/s) -host_mem_usage 214676 # Number of bytes of host memory used -host_seconds 1975.03 # Real time elapsed on the host +host_inst_rate 246728 # Simulator instruction rate (inst/s) +host_op_rate 246728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58782597 # Simulator tick rate (ticks/s) +host_mem_usage 216860 # Number of bytes of host memory used +host_seconds 1522.22 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated +sim_ops 375574794 # Number of ops (including micro ops) simulated system.physmem.bytes_read 475840 # Number of bytes read from this memory system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -271,6 +273,7 @@ system.cpu.iew.wb_rate 2.269707 # in system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions +system.cpu.commit.commitCommittedOps 398664569 # The number of committed instructions system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted @@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle -system.cpu.commit.count 398664569 # Number of instructions committed +system.cpu.commit.committedInsts 398664569 # Number of instructions committed +system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168275214 # Number of memory references committed system.cpu.commit.loads 94754486 # Number of loads committed @@ -307,6 +311,7 @@ system.cpu.rob.rob_writes 926487800 # Th system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated +system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads @@ -324,26 +329,39 @@ system.cpu.icache.total_refs 57898804 # To system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1834.326922 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.895667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 57898804 # number of ReadReq hits -system.cpu.icache.demand_hits 57898804 # number of demand (read+write) hits -system.cpu.icache.overall_hits 57898804 # number of overall hits -system.cpu.icache.ReadReq_misses 5282 # number of ReadReq misses -system.cpu.icache.demand_misses 5282 # number of demand (read+write) misses -system.cpu.icache.overall_misses 5282 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 167914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 167914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 57904086 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 57904086 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 31789.852329 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 31789.852329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 31789.852329 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1834.326922 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.895667 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.895667 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 57898804 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 57898804 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 57898804 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 57898804 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 57898804 # number of overall hits +system.cpu.icache.overall_hits::total 57898804 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5282 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5282 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5282 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5282 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5282 # number of overall misses +system.cpu.icache.overall_misses::total 5282 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 167914000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 167914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 167914000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 167914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 167914000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 167914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57904086 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57904086 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57904086 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57904086 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57904086 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57904086 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31789.852329 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4037 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4037 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 123459000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4037 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4037 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4037 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4037 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4037 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4037 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123459000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 123459000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123459000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 123459000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123459000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 123459000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30581.867724 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 793 # number of replacements system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use @@ -380,34 +401,53 @@ system.cpu.dcache.total_refs 164730953 # To system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3296.196945 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 91229707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73501239 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 164730946 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 164730946 # number of overall hits -system.cpu.dcache.ReadReq_misses 1678 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses -system.cpu.dcache.demand_misses 21167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 21167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 55919500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 568883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 624802500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 164752113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 164752113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 29517.763500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 29517.763500 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3296.196945 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804736 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804736 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 91229707 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 91229707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501239 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501239 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 164730946 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 164730946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 164730946 # number of overall hits +system.cpu.dcache.overall_hits::total 164730946 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1678 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1678 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21167 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21167 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21167 # number of overall misses +system.cpu.dcache.overall_misses::total 21167 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55919500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55919500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 568883000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 568883000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 624802500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 624802500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 624802500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 624802500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 91231385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 91231385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 164752113 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 164752113 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 164752113 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 164752113 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33325.089392 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29189.953307 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -416,32 +456,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 680 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16294 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 16974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 16974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4193 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4193 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31703500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 113133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 144837000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 144837000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 671 # number of writebacks +system.cpu.dcache.writebacks::total 671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16294 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16294 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16974 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16974 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16974 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16974 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4193 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4193 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4193 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4193 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31703500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31703500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144837000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 144837000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144837000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 144837000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31767.034068 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35409.546166 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 10 # number of replacements system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use @@ -449,36 +497,75 @@ system.cpu.l2cache.total_refs 810 # To system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3629.785283 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 377.670641 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.110772 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011526 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 730 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 671 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 65 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 795 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 795 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3130 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7435 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7435 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 148163500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 108392000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 256555500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 256555500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5035 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 671 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8230 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8230 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.855015 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.979656 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.903402 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.903402 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34506.455952 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34506.455952 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 377.670641 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2971.084033 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 658.701251 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011526 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.090670 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020102 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.122298 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 600 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 730 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 671 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 671 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 65 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 65 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 600 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 600 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 195 # number of overall hits +system.cpu.l2cache.overall_hits::total 795 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3437 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 868 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4305 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3437 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3998 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7435 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3437 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3998 # number of overall misses +system.cpu.l2cache.overall_misses::total 7435 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 118151500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30012000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 148163500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108392000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 108392000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 118151500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 138404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 256555500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 118151500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 138404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 256555500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4037 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5035 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 671 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 671 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4037 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4193 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8230 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4037 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4193 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8230 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.851375 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869739 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979656 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.851375 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.953494 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.851375 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.953494 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34376.345650 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34576.036866 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34630.031949 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,30 +574,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7435 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7435 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 134314000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98534000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 232848000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 232848000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.855015 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.979656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.903402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.903402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3437 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 868 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3998 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7435 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3437 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3998 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27274000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98534000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98534000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125808000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 232848000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125808000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 232848000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869739 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979656 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31143.439046 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31421.658986 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31480.511182 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 8310ba9e4..ce995453a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout index 3a628f576..3f05b7dba 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:11:11 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 3ed2b47f1..cdec8f7fd 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3927016 # Simulator instruction rate (inst/s) -host_tick_rate 1963508553 # Simulator tick rate (ticks/s) -host_mem_usage 204908 # Number of bytes of host memory used -host_seconds 101.52 # Real time elapsed on the host +host_inst_rate 4966970 # Simulator instruction rate (inst/s) +host_op_rate 4966969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2483485434 # Simulator tick rate (ticks/s) +host_mem_usage 206672 # Number of bytes of host memory used +host_seconds 80.26 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated +sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2257107875 # Number of bytes read from this memory system.physmem.bytes_inst_read 1594658604 # Number of instructions bytes read from this memory system.physmem.bytes_written 492356798 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 398664824 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 398664595 # Number of instructions executed +system.cpu.committedInsts 398664595 # Number of instructions committed +system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses system.cpu.num_func_calls 16015498 # number of times a function call or return occured diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index 63aac5a1a..c8010ddb2 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index 06075d86e..fe28e85e0 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:12:03 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index af7a7f90d..0281e5820 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.567343 # Nu sim_ticks 567343170000 # Number of ticks simulated final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1814376 # Simulator instruction rate (inst/s) -host_tick_rate 2582053806 # Simulator tick rate (ticks/s) -host_mem_usage 213620 # Number of bytes of host memory used -host_seconds 219.73 # Real time elapsed on the host +host_inst_rate 2193403 # Simulator instruction rate (inst/s) +host_op_rate 2193403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3121451222 # Simulator tick rate (ticks/s) +host_mem_usage 215564 # Number of bytes of host memory used +host_seconds 181.76 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated +sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read 459520 # Number of bytes read from this memory system.physmem.bytes_inst_read 205120 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 1134686340 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 398664609 # Number of instructions executed +system.cpu.committedInsts 398664609 # Number of instructions committed +system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses system.cpu.num_func_calls 16015498 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 398660993 # To system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.876529 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits -system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits -system.cpu.icache.overall_hits 398660993 # number of overall hits -system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses -system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses -system.cpu.icache.overall_misses 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1795.131074 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits +system.cpu.icache.overall_hits::total 398660993 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses +system.cpu.icache.overall_misses::total 3673 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186032000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186032000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 186032000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186032000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 186032000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186032000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 168271068 # To system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.802957 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits -system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 168271068 # number of overall hits -system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses -system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 176792000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 225078000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 225078000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54209.537572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3288.912598 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits +system.cpu.dcache.overall_hits::total 168271068 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses +system.cpu.dcache.overall_misses::total 4152 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48286000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48286000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 225078000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 225078000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 225078000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 225078000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 649 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4152 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45436000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45436000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212622000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212622000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use @@ -198,36 +231,75 @@ system.cpu.l2cache.total_refs 656 # To system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 645 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3142 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7180 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 371.536808 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2770.454482 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 626.720973 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019126 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.115012 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 585 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 177 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 206700000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 373360000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,30 +308,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 287200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.917572 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 833 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4038 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7180 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7180 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 159000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 287200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 46adc802e..3b6ae18fc 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index df63c01b7..347d30ac0 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:22 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:57:28 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 44e129451..242cca723 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.104493 # Nu sim_ticks 104492506500 # Number of ticks simulated final_tick 104492506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80425 # Simulator instruction rate (inst/s) -host_tick_rate 24075162 # Simulator tick rate (ticks/s) -host_mem_usage 264476 # Number of bytes of host memory used -host_seconds 4340.26 # Real time elapsed on the host -sim_insts 349066034 # Number of instructions simulated +host_inst_rate 158423 # Simulator instruction rate (inst/s) +host_op_rate 202536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60628822 # Simulator tick rate (ticks/s) +host_mem_usage 231676 # Number of bytes of host memory used +host_seconds 1723.48 # Real time elapsed on the host +sim_insts 273038258 # Number of instructions simulated +sim_ops 349066034 # Number of ops (including micro ops) simulated system.physmem.bytes_read 464000 # Number of bytes read from this memory system.physmem.bytes_inst_read 192512 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -280,7 +282,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.769576 # insts written-back per cycle system.cpu.iew.wb_fanout 0.508145 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 273038870 # The number of committed instructions +system.cpu.commit.commitCommittedOps 349066646 # The number of committed instructions system.cpu.commit.commitSquashedInsts 49103053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 3227876 # The number of times a branch was mispredicted @@ -301,7 +304,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 201258644 # Number of insts commited each cycle -system.cpu.commit.count 349066646 # Number of instructions committed +system.cpu.commit.committedInsts 273038870 # Number of instructions committed +system.cpu.commit.committedOps 349066646 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 177024831 # Number of memory references committed system.cpu.commit.loads 94649000 # Number of loads committed @@ -316,12 +320,13 @@ system.cpu.rob.rob_reads 587812621 # Th system.cpu.rob.rob_writes 803956224 # The number of ROB writes system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 112680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 349066034 # Number of Instructions Simulated -system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated -system.cpu.cpi 0.598698 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.598698 # CPI: Total CPI of All Threads -system.cpu.ipc 1.670292 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.670292 # IPC: Total IPC of All Threads +system.cpu.committedInsts 273038258 # Number of Instructions Simulated +system.cpu.committedOps 349066034 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273038258 # Number of Instructions Simulated +system.cpu.cpi 0.765406 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.765406 # CPI: Total CPI of All Threads +system.cpu.ipc 1.306497 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.306497 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 1781918480 # number of integer regfile reads system.cpu.int_regfile_writes 235832393 # number of integer regfile writes system.cpu.fp_regfile_reads 188783884 # number of floating regfile reads @@ -334,26 +339,39 @@ system.cpu.icache.total_refs 41220872 # To system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2578.238179 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1842.733120 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.899772 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 41220872 # number of ReadReq hits -system.cpu.icache.demand_hits 41220872 # number of demand (read+write) hits -system.cpu.icache.overall_hits 41220872 # number of overall hits -system.cpu.icache.ReadReq_misses 16648 # number of ReadReq misses -system.cpu.icache.demand_misses 16648 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16648 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 201025000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 201025000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 201025000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 41237520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 41237520 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 41237520 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12075.024027 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12075.024027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12075.024027 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1842.733120 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.899772 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.899772 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 41220872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41220872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 41220872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41220872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 41220872 # number of overall hits +system.cpu.icache.overall_hits::total 41220872 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16648 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16648 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16648 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16648 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16648 # number of overall misses +system.cpu.icache.overall_misses::total 16648 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 201025000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201025000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 201025000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201025000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 201025000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201025000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41237520 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41237520 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41237520 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41237520 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 41237520 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41237520 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000404 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000404 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000404 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12075.024027 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -362,27 +380,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 16011 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 16011 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 16011 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 135953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 135953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 135953500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8491.256011 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8491.256011 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8491.256011 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 637 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 637 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 637 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 637 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 637 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 637 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16011 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16011 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16011 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16011 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16011 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16011 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 135953500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 135953500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 135953500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 135953500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 135953500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 135953500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8491.256011 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8491.256011 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8491.256011 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1410 # number of replacements system.cpu.dcache.tagsinuse 3098.497902 # Cycle average of tags in use @@ -390,40 +411,63 @@ system.cpu.dcache.total_refs 176602100 # To system.cpu.dcache.sampled_refs 4594 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 38441.902481 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3098.497902 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.756469 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 94546395 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 82033205 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 11358 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11114 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 176579600 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 176579600 # number of overall hits -system.cpu.dcache.ReadReq_misses 3383 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 22872 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 22872 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 111712500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 649715000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 761427500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 761427500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 94549778 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11114 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 176602472 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 176602472 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000130 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33021.726278 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33337.523731 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33290.814096 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33290.814096 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3098.497902 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.756469 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.756469 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94546395 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94546395 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82033205 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82033205 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11358 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11358 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11114 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11114 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 176579600 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176579600 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176579600 # number of overall hits +system.cpu.dcache.overall_hits::total 176579600 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3383 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3383 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 22872 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 22872 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22872 # number of overall misses +system.cpu.dcache.overall_misses::total 22872 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 111712500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 111712500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 649715000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 649715000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 761427500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 761427500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 761427500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 761427500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94549778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94549778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052694 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052694 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11360 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11360 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11114 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11114 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 176602472 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 176602472 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 176602472 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 176602472 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000036 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000176 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000130 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000130 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33021.726278 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33337.523731 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33290.814096 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33290.814096 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,33 +476,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1034 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1633 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16622 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 18255 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 18255 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1750 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 2867 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4617 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4617 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 53344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 101787500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 155131500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 155131500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30482.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35503.139170 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33600.064977 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33600.064977 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1034 # number of writebacks +system.cpu.dcache.writebacks::total 1034 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1633 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1633 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16622 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16622 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 18255 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 18255 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 18255 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 18255 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1750 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1750 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2867 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2867 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4617 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4617 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4617 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4617 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53344000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53344000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101787500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 101787500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155131500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 155131500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155131500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 155131500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30482.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35503.139170 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33600.064977 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33600.064977 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 57 # number of replacements system.cpu.l2cache.tagsinuse 3892.486015 # Cycle average of tags in use @@ -466,39 +519,80 @@ system.cpu.l2cache.total_refs 13341 # To system.cpu.l2cache.sampled_refs 5352 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.492713 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3513.908293 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 378.577721 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107236 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011553 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 13258 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1034 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 13277 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 13277 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4479 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 23 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 2826 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7305 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7305 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 153679500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 97429500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 251109000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 251109000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 17737 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1034 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 23 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 2845 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 20582 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 20582 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.252523 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.993322 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.354922 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.354922 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34311.118553 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34476.114650 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34374.948665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34374.948665 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 378.577721 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2756.979421 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 756.928873 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011553 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.084136 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.023100 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.118789 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12970 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 288 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13258 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1034 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1034 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 19 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 19 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12970 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13277 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12970 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits +system.cpu.l2cache.overall_hits::total 13277 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3018 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1461 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4479 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 23 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 23 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2826 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2826 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3018 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4287 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7305 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3018 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4287 # number of overall misses +system.cpu.l2cache.overall_misses::total 7305 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 103392000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50287500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 153679500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97429500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 97429500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 103392000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 147717000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 251109000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 103392000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 147717000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 251109000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15988 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1749 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17737 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1034 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1034 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 23 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 23 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2845 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2845 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15988 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4594 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20582 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15988 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4594 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20582 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.188767 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835334 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993322 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.933174 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.933174 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34258.449304 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34419.917864 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.114650 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34258.449304 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34456.962911 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34258.449304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34456.962911 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,35 +601,57 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4424 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 2826 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7250 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7250 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 137822500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 713000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 226240500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 226240500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249422 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993322 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.352250 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.352250 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.367993 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31287.331918 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.586207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.586207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3008 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1416 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4424 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 23 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 23 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2826 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2826 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3008 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7250 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3008 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4242 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7250 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 93473500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44349000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 137822500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 713000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 713000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88418000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88418000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 93473500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132767000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 226240500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 93473500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132767000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 226240500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993322 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.966755 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31319.915254 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31287.331918 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 5628f29f0..2d58b9952 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 2369bef1b..861cd978d 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:01:21 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:59:35 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 7857a9031..24bfa1f56 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.212344 # Nu sim_ticks 212344048000 # Number of ticks simulated final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2434260 # Simulator instruction rate (inst/s) -host_tick_rate 1480812932 # Simulator tick rate (ticks/s) -host_mem_usage 218160 # Number of bytes of host memory used -host_seconds 143.40 # Real time elapsed on the host -sim_insts 349065408 # Number of instructions simulated +host_inst_rate 2097833 # Simulator instruction rate (inst/s) +host_op_rate 2681977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1631504750 # Simulator tick rate (ticks/s) +host_mem_usage 220728 # Number of bytes of host memory used +host_seconds 130.15 # Real time elapsed on the host +sim_insts 273037671 # Number of instructions simulated +sim_ops 349065408 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1875350709 # Number of bytes read from this memory system.physmem.bytes_inst_read 1394641440 # Number of instructions bytes read from this memory system.physmem.bytes_written 400047783 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 191 # Nu system.cpu.numCycles 424688097 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 349065408 # Number of instructions executed +system.cpu.committedInsts 273037671 # Number of instructions committed +system.cpu.committedOps 349065408 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12433363 # number of times a function call or return occured diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 28a0917d8..bc61fa4c6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 3428f8224..aff2d34a5 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:03:55 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:01:56 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 3b365c759..bcea217f3 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.525854 # Nu sim_ticks 525854475000 # Number of ticks simulated final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1206167 # Simulator instruction rate (inst/s) -host_tick_rate 1819018700 # Simulator tick rate (ticks/s) -host_mem_usage 227092 # Number of bytes of host memory used -host_seconds 289.09 # Real time elapsed on the host -sim_insts 348687131 # Number of instructions simulated +host_inst_rate 1153060 # Simulator instruction rate (inst/s) +host_op_rate 1474144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2223154070 # Simulator tick rate (ticks/s) +host_mem_usage 229624 # Number of bytes of host memory used +host_seconds 236.54 # Real time elapsed on the host +sim_insts 272739291 # Number of instructions simulated +sim_ops 348687131 # Number of ops (including micro ops) simulated system.physmem.bytes_read 437312 # Number of bytes read from this memory system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls 191 # Nu system.cpu.numCycles 1051708950 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 348687131 # Number of instructions executed +system.cpu.committedInsts 272739291 # Number of instructions committed +system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12433363 # number of times a function call or return occured @@ -88,26 +91,39 @@ system.cpu.icache.total_refs 348644756 # To system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1765.984158 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.862297 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 348644756 # number of ReadReq hits -system.cpu.icache.demand_hits 348644756 # number of demand (read+write) hits -system.cpu.icache.overall_hits 348644756 # number of overall hits -system.cpu.icache.ReadReq_misses 15603 # number of ReadReq misses -system.cpu.icache.demand_misses 15603 # number of demand (read+write) misses -system.cpu.icache.overall_misses 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 328062000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 328062000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 348660359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 348660359 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 348660359 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 21025.572005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits +system.cpu.icache.overall_hits::total 348644756 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses +system.cpu.icache.overall_misses::total 15603 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 15603 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 15603 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 15603 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 281253000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 281253000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 281253000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000045 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000045 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use @@ -143,36 +157,57 @@ system.cpu.dcache.total_refs 176641600 # To system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3078.396238 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.751562 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 94570005 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 82049805 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 10895 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 176619810 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 176619810 # number of overall hits -system.cpu.dcache.ReadReq_misses 1606 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 2872 # number of WriteReq misses -system.cpu.dcache.demand_misses 4478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 79898000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 160160000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 240058000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 240058000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 94571611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 176624288 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 176624288 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 53608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 53608.307280 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits +system.cpu.dcache.overall_hits::total 176619810 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses +system.cpu.dcache.overall_misses::total 4478 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79898000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79898000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 160160000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 160160000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 240058000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 176624288 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,30 +216,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 998 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1606 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 2872 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4478 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4478 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 998 # number of writebacks +system.cpu.dcache.writebacks::total 998 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 48 # number of replacements system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use @@ -212,36 +249,75 @@ system.cpu.l2cache.total_refs 13308 # To system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3134.059650 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 341.613272 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.095644 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 13232 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 998 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 13248 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 13248 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3977 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 2856 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 6833 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 6833 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 206804000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 355316000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 17209 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 998 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 20081 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 20081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.231100 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.340272 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.340272 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13248 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12993 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits +system.cpu.l2cache.overall_hits::total 13248 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2610 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3977 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2610 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 6833 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2610 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses +system.cpu.l2cache.overall_misses::total 6833 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135720000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 206804000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 135720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 355316000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 135720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 355316000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 273320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231100 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.340272 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.340272 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 6833 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2610 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 6833 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 273320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index c87170fbe..2d167e65d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 2a099e16b..af8dce3f0 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:26:04 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:12:28 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 90210da82..4c98d6289 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.643030 # Nu sim_ticks 643030478500 # Number of ticks simulated final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153915 # Simulator instruction rate (inst/s) -host_tick_rate 54289503 # Simulator tick rate (ticks/s) -host_mem_usage 215008 # Number of bytes of host memory used -host_seconds 11844.47 # Real time elapsed on the host +host_inst_rate 198283 # Simulator instruction rate (inst/s) +host_op_rate 198283 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69939236 # Simulator tick rate (ticks/s) +host_mem_usage 217424 # Number of bytes of host memory used +host_seconds 9194.13 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated +sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94779264 # Number of bytes read from this memory system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory system.physmem.bytes_written 4281472 # Number of bytes written to this memory @@ -272,6 +274,7 @@ system.cpu.iew.wb_rate 1.604576 # in system.cpu.iew.wb_fanout 0.675414 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions +system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions system.cpu.commit.commitSquashedInsts 979738658 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 28886163 # The number of times a branch was mispredicted @@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 1150060787 # Number of insts commited each cycle -system.cpu.commit.count 2008987604 # Number of instructions committed +system.cpu.commit.committedInsts 2008987604 # Number of instructions committed +system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 721864922 # Number of memory references committed system.cpu.commit.loads 511070026 # Number of loads committed @@ -308,6 +312,7 @@ system.cpu.rob.rob_writes 6113513811 # Th system.cpu.timesIdled 3507 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 125916 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated +system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated system.cpu.cpi 0.705447 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.705447 # CPI: Total CPI of All Threads @@ -325,26 +330,39 @@ system.cpu.icache.total_refs 398299261 # To system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 40046.175447 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1650.873085 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.806090 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 398299261 # number of ReadReq hits -system.cpu.icache.demand_hits 398299261 # number of demand (read+write) hits -system.cpu.icache.overall_hits 398299261 # number of overall hits -system.cpu.icache.ReadReq_misses 11100 # number of ReadReq misses -system.cpu.icache.demand_misses 11100 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11100 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 182477500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 182477500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 182477500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 398310361 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 398310361 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 398310361 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 16439.414414 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 16439.414414 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 16439.414414 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1650.873085 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.806090 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.806090 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 398299261 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 398299261 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 398299261 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 398299261 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 398299261 # number of overall hits +system.cpu.icache.overall_hits::total 398299261 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11100 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11100 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11100 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11100 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11100 # number of overall misses +system.cpu.icache.overall_misses::total 11100 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182477500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182477500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182477500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182477500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182477500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182477500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 398310361 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 398310361 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 398310361 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 398310361 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 398310361 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 398310361 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16439.414414 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9947 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9947 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9947 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 119555000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 119555000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 119555000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12019.201769 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12019.201769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12019.201769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1153 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9947 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9947 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9947 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9947 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9947 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9947 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 119555000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 119555000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 119555000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 119555000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 119555000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 119555000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12019.201769 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1527592 # number of replacements system.cpu.dcache.tagsinuse 4095.113983 # Cycle average of tags in use @@ -381,38 +402,59 @@ system.cpu.dcache.total_refs 660890207 # To system.cpu.dcache.sampled_refs 1531688 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 431.478347 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 255376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.113983 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 450646939 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 210243259 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 660890198 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 660890198 # number of overall hits -system.cpu.dcache.ReadReq_misses 1928305 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 551637 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2479942 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2479942 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 71444429000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20878144491 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 59000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 92322573491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 92322573491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 452575244 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 663370140 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 663370140 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004261 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002617 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.003738 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37050.377923 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37847.614448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 29500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 37227.714798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 37227.714798 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4095.113983 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 450646939 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 450646939 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 210243259 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210243259 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 660890198 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660890198 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660890198 # number of overall hits +system.cpu.dcache.overall_hits::total 660890198 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1928305 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1928305 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 551637 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 551637 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2479942 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2479942 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2479942 # number of overall misses +system.cpu.dcache.overall_misses::total 2479942 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71444429000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71444429000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20878144491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20878144491 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 59000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 59000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92322573491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92322573491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92322573491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92322573491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 452575244 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 452575244 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 663370140 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 663370140 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 663370140 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 663370140 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004261 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002617 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003738 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003738 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37050.377923 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37847.614448 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37227.714798 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37227.714798 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 79500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -421,37 +463,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 5678.571429 system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107326 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52435407500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52435407500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003226 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.090909 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002309 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002309 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34205.118274 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34817.819985 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34233.761532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34233.761532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107326 # number of writebacks +system.cpu.dcache.writebacks::total 107326 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468223 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 468223 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480032 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 480032 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52435407500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52435407500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52435407500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003226 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002309 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002309 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34205.118274 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34817.819985 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34233.761532 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34233.761532 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480630 # number of replacements system.cpu.l2cache.tagsinuse 31935.913288 # Cycle average of tags in use @@ -459,36 +512,75 @@ system.cpu.l2cache.total_refs 63583 # To system.cpu.l2cache.sampled_refs 1513317 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.042016 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28876.475418 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3059.437870 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2349021500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 99564500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 50762967000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50862531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 99564500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 50762967000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50862531500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9947 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460083 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1470030 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107326 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107326 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71605 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71605 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9947 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1531688 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1541635 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9947 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1531688 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1541635 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.291646 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966500 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933664 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.291646 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964965 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.291646 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964965 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.751465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34307.663499 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35136.063122 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -497,30 +589,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66898 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1414071 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1480926 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1480926 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43837380500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147695000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 45985075500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 45985075500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961933 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933664 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.960620 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.960620 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.834117 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.672799 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks +system.cpu.l2cache.writebacks::total 66898 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2901 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411170 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1414071 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2901 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1478025 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1480926 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2901 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1478025 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1480926 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90197000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43747183500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43837380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2147695000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147695000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90197000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45894878500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 45985075500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90197000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45894878500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 45985075500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966500 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933664 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.692520 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.647335 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32124.672799 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index a895468a4..e114fdc81 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 67c7a90bd..d7926f03a 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:26:36 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:12:42 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 5a9e50b92..4c63884c7 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.004711 # Nu sim_ticks 1004710587000 # Number of ticks simulated final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4051601 # Simulator instruction rate (inst/s) -host_tick_rate 2026237516 # Simulator tick rate (ticks/s) -host_mem_usage 204820 # Number of bytes of host memory used -host_seconds 495.85 # Real time elapsed on the host +host_inst_rate 5076159 # Simulator instruction rate (inst/s) +host_op_rate 5076159 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2538627026 # Simulator tick rate (ticks/s) +host_mem_usage 206544 # Number of bytes of host memory used +host_seconds 395.77 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated +sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11607100996 # Number of bytes read from this memory system.physmem.bytes_inst_read 8037684280 # Number of instructions bytes read from this memory system.physmem.bytes_written 1586125963 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 39 # Nu system.cpu.numCycles 2009421175 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2008987605 # Number of instructions executed +system.cpu.committedInsts 2008987605 # Number of instructions committed +system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses system.cpu.num_func_calls 79910682 # number of times a function call or return occured diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index f60b78837..794cf18d1 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index e767ec1c4..25b995793 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:28:03 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:14:25 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 668a6f1dd..19236d338 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.813468 # Nu sim_ticks 2813467842000 # Number of ticks simulated final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1954286 # Simulator instruction rate (inst/s) -host_tick_rate 2736861040 # Simulator tick rate (ticks/s) -host_mem_usage 213480 # Number of bytes of host memory used -host_seconds 1027.99 # Real time elapsed on the host +host_inst_rate 2306294 # Simulator instruction rate (inst/s) +host_op_rate 2306294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3229827855 # Simulator tick rate (ticks/s) +host_mem_usage 215660 # Number of bytes of host memory used +host_seconds 871.09 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated +sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94708160 # Number of bytes read from this memory system.physmem.bytes_inst_read 152128 # Number of instructions bytes read from this memory system.physmem.bytes_written 4281472 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 39 # Nu system.cpu.numCycles 5626935684 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2008987605 # Number of instructions executed +system.cpu.committedInsts 2008987605 # Number of instructions committed +system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses system.cpu.num_func_calls 79910682 # number of times a function call or return occured @@ -79,26 +82,39 @@ system.cpu.icache.total_refs 2009410475 # To system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.721886 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits -system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits -system.cpu.icache.overall_hits 2009410475 # number of overall hits -system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses -system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses -system.cpu.icache.overall_misses 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1478.423269 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.721886 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.721886 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2009410475 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2009410475 # number of overall hits +system.cpu.icache.overall_hits::total 2009410475 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10596 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses +system.cpu.icache.overall_misses::total 10596 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 248178000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 248178000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 248178000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 248178000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 248178000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 248178000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2009421071 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23421.857305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10596 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use @@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 720334778 # To system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits -system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 720334778 # number of overall hits -system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses -system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 79658418000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 3815994000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 83474412000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 83474412000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54553.304787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4095.204626 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits +system.cpu.dcache.overall_hits::total 720334778 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses +system.cpu.dcache.overall_misses::total 1530144 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79658418000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79658418000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3815994000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3815994000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83474412000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83474412000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83474412000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83474412000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54628.209454 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107612 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 75283842000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 78883980000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 78883980000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107612 # number of writebacks +system.cpu.dcache.writebacks::total 107612 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75283842000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75283842000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78883980000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78883980000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78883980000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78883980000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51628.209454 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1479797 # number of replacements system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use @@ -199,36 +232,75 @@ system.cpu.l2cache.total_refs 63431 # To system.cpu.l2cache.sampled_refs 1512480 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.041938 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.880371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.094050 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 55846 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107612 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 5079 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 60925 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 60925 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1412942 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 66873 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1479815 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1479815 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 73472984000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3477396000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 76950380000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 76950380000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107612 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.961978 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.929411 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.960457 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.960457 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 3081.828747 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.409968 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28814.603011 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.094050 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001020 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.879352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.974421 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 47627 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 55846 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107612 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107612 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 76950380000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 123604000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 76826776000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 76950380000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107612 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107612 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1530144 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1540740 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10596 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.967338 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.965555 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.965555 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,30 +309,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66898 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks +system.cpu.l2cache.writebacks::total 66898 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2377 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410565 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1412942 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2377 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1477438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1479815 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1477438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1479815 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56422600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56517680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59097520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59192600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59097520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 59192600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.967338 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 78c85cac9..3a59e4035 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 76bc74d1e..96ddf0fe4 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:22 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:06:03 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 801f115d2..b8fd6e344 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.708285 # Nu sim_ticks 708285420500 # Number of ticks simulated final_tick 708285420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74841 # Simulator instruction rate (inst/s) -host_tick_rate 28116271 # Simulator tick rate (ticks/s) -host_mem_usage 262240 # Number of bytes of host memory used -host_seconds 25191.30 # Real time elapsed on the host -sim_insts 1885333786 # Number of instructions simulated +host_inst_rate 110657 # Simulator instruction rate (inst/s) +host_op_rate 150700 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56615274 # Simulator tick rate (ticks/s) +host_mem_usage 229476 # Number of bytes of host memory used +host_seconds 12510.50 # Real time elapsed on the host +sim_insts 1384379033 # Number of instructions simulated +sim_ops 1885333786 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94806144 # Number of bytes read from this memory system.physmem.bytes_inst_read 201024 # Number of instructions bytes read from this memory system.physmem.bytes_written 4230336 # Number of bytes written to this memory @@ -281,7 +283,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.741158 # insts written-back per cycle system.cpu.iew.wb_fanout 0.534869 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions system.cpu.commit.commitSquashedInsts 1192760864 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 38418907 # The number of times a branch was mispredicted @@ -302,7 +305,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 1198732893 # Number of insts commited each cycle -system.cpu.commit.count 1885344802 # Number of instructions committed +system.cpu.commit.committedInsts 1384390049 # Number of instructions committed +system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 908385853 # Number of memory references committed system.cpu.commit.loads 631388869 # Number of loads committed @@ -317,12 +321,13 @@ system.cpu.rob.rob_reads 4196573290 # Th system.cpu.rob.rob_writes 6322749564 # The number of ROB writes system.cpu.timesIdled 1340847 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 51326273 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1885333786 # Number of Instructions Simulated -system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated -system.cpu.cpi 0.751363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.751363 # CPI: Total CPI of All Threads -system.cpu.ipc 1.330914 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.330914 # IPC: Total IPC of All Threads +system.cpu.committedInsts 1384379033 # Number of Instructions Simulated +system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated +system.cpu.cpi 1.023254 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.023254 # CPI: Total CPI of All Threads +system.cpu.ipc 0.977275 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.977275 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 12567200244 # number of integer regfile reads system.cpu.int_regfile_writes 2359430733 # number of integer regfile writes system.cpu.fp_regfile_reads 68800397 # number of floating regfile reads @@ -335,26 +340,39 @@ system.cpu.icache.total_refs 384162744 # To system.cpu.icache.sampled_refs 28920 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 13283.635685 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1638.335274 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.799968 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 384163979 # number of ReadReq hits -system.cpu.icache.demand_hits 384163979 # number of demand (read+write) hits -system.cpu.icache.overall_hits 384163979 # number of overall hits -system.cpu.icache.ReadReq_misses 34037 # number of ReadReq misses -system.cpu.icache.demand_misses 34037 # number of demand (read+write) misses -system.cpu.icache.overall_misses 34037 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 300707500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 300707500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 300707500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 384198016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 384198016 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 384198016 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 8834.723977 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 8834.723977 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 8834.723977 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1638.335274 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.799968 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.799968 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 384163979 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 384163979 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 384163979 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 384163979 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 384163979 # number of overall hits +system.cpu.icache.overall_hits::total 384163979 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34037 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34037 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34037 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34037 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34037 # number of overall misses +system.cpu.icache.overall_misses::total 34037 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 300707500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 300707500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 300707500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 300707500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 300707500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 300707500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 384198016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 384198016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 384198016 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 384198016 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 384198016 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 384198016 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8834.723977 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,27 +381,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 775 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 775 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 775 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 33262 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 33262 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 33262 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 180621500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 180621500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 180621500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5430.265769 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5430.265769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5430.265769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 775 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 775 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 775 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 775 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 775 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 775 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33262 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 33262 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 33262 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 33262 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 33262 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 33262 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 180621500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 180621500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 180621500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 180621500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 180621500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 180621500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5430.265769 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5430.265769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5430.265769 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1531781 # number of replacements system.cpu.dcache.tagsinuse 4094.791758 # Cycle average of tags in use @@ -391,40 +412,63 @@ system.cpu.dcache.total_refs 1029515809 # To system.cpu.dcache.sampled_refs 1535877 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 670.311365 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 305571000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.791758 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 753356755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 276118556 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 15246 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11672 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 1029475311 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1029475311 # number of overall hits -system.cpu.dcache.ReadReq_misses 1938073 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 817122 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2755195 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2755195 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 69347083500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 28485572000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 97832655500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 97832655500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 755294828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 15249 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11672 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1032230506 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1032230506 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000197 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35781.461018 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 34860.855539 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35508.432434 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35508.432434 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.791758 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999705 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999705 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 753356755 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 753356755 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276118556 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276118556 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15246 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15246 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11672 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11672 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1029475311 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1029475311 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1029475311 # number of overall hits +system.cpu.dcache.overall_hits::total 1029475311 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1938073 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1938073 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 817122 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 817122 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2755195 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2755195 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2755195 # number of overall misses +system.cpu.dcache.overall_misses::total 2755195 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69347083500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69347083500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28485572000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28485572000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 108500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 108500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97832655500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97832655500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97832655500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97832655500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 755294828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 755294828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15249 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15249 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11672 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11672 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1032230506 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1032230506 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1032230506 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1032230506 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002566 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002951 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000197 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35781.461018 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34860.855539 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35508.432434 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35508.432434 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,33 +477,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 106815 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 474897 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 740078 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1214975 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1214975 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1463176 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 77044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1540220 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1540220 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 50021914000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2483063000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52504977000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52504977000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34187.216029 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32229.154769 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34089.271013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34089.271013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 106815 # number of writebacks +system.cpu.dcache.writebacks::total 106815 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474897 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 474897 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740078 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 740078 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1214975 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1214975 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1214975 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1214975 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463176 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1463176 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 77044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1540220 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1540220 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1540220 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1540220 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50021914000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50021914000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2483063000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2483063000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52504977000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52504977000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52504977000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52504977000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001937 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34187.216029 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32229.154769 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34089.271013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34089.271013 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480005 # number of replacements system.cpu.l2cache.tagsinuse 31970.457215 # Cycle average of tags in use @@ -467,40 +520,82 @@ system.cpu.l2cache.total_refs 85123 # To system.cpu.l2cache.sampled_refs 1512725 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.056271 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 29003.484666 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2966.972548 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.885116 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.090545 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 76806 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 106815 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 6620 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 83426 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 83426 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1415291 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4338 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1481373 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1481373 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48556724500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2252633500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50809358000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50809358000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1492097 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 106815 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 4342 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 72702 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1564799 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1564799 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.948525 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.999079 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.908943 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.946686 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.946686 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34308.650659 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.458279 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34298.828182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34298.828182 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 2966.972548 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 53.821499 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28949.663167 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.090545 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001643 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.883474 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.975661 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 25776 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 51030 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 76806 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 106815 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 106815 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 6620 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6620 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 25776 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 57650 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 83426 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 25776 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 57650 # number of overall hits +system.cpu.l2cache.overall_hits::total 83426 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3145 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1412146 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1415291 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4338 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4338 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66082 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66082 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3145 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1478228 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1481373 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3145 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1478228 # number of overall misses +system.cpu.l2cache.overall_misses::total 1481373 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107831000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48448893500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 48556724500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252633500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2252633500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 107831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 50701527000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50809358000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 107831000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 50701527000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50809358000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 28921 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1463176 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1492097 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 106815 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 106815 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4342 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4342 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72702 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72702 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 28921 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1535878 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1564799 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 28921 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1535878 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1564799 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108745 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.965124 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999079 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908943 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108745 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.962464 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108745 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.962464 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.486486 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34308.700021 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34088.458279 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.486486 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.854439 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.486486 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.854439 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,35 +604,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1415264 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4338 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1481346 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1481346 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43971004500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 134478000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 46019602000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 46019602000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948507 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999079 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.946669 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.946669 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118200 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072342 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072342 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks +system.cpu.l2cache.writebacks::total 66099 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3141 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412123 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1415264 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4338 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4338 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66082 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1478205 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1481346 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3141 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1478205 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1481346 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97624500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43873380000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43971004500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 134478000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 134478000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048597500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048597500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97624500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45921977500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46019602000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97624500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45921977500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46019602000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965108 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999079 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908943 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.706781 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31069.092423 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.839866 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 6a275dc9a..3b0020443 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index dd29e750e..31662be21 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:17:45 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:09:56 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 49ae2817e..a0e247e5f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.945613 # Nu sim_ticks 945613131000 # Number of ticks simulated final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2997522 # Simulator instruction rate (inst/s) -host_tick_rate 1503443037 # Simulator tick rate (ticks/s) -host_mem_usage 215364 # Number of bytes of host memory used -host_seconds 628.97 # Real time elapsed on the host -sim_insts 1885336367 # Number of instructions simulated +host_inst_rate 2494982 # Simulator instruction rate (inst/s) +host_op_rate 3397821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1704217996 # Simulator tick rate (ticks/s) +host_mem_usage 217680 # Number of bytes of host memory used +host_seconds 554.87 # Real time elapsed on the host +sim_insts 1384381614 # Number of instructions simulated +sim_ops 1885336367 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8025491315 # Number of bytes read from this memory system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory system.physmem.bytes_written 1123958396 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 1411 # Nu system.cpu.numCycles 1891226263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1885336367 # Number of instructions executed +system.cpu.committedInsts 1384381614 # Number of instructions committed +system.cpu.committedOps 1885336367 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_func_calls 80344203 # number of times a function call or return occured diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 01aaafc03..62f983a26 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index df0dd80b9..608f1b673 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:28:26 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:19:22 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 117215dc5..70fd39037 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.369902 # Nu sim_ticks 2369901960000 # Number of ticks simulated final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1407810 # Simulator instruction rate (inst/s) -host_tick_rate 1780114775 # Simulator tick rate (ticks/s) -host_mem_usage 224180 # Number of bytes of host memory used -host_seconds 1331.32 # Real time elapsed on the host -sim_insts 1874244950 # Number of instructions simulated +host_inst_rate 1307856 # Simulator instruction rate (inst/s) +host_op_rate 1774200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2243399723 # Simulator tick rate (ticks/s) +host_mem_usage 226844 # Number of bytes of host memory used +host_seconds 1056.39 # Real time elapsed on the host +sim_insts 1381604347 # Number of instructions simulated +sim_ops 1874244950 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94696320 # Number of bytes read from this memory system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory system.physmem.bytes_written 4230336 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 1411 # Nu system.cpu.numCycles 4739803920 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1874244950 # Number of instructions executed +system.cpu.committedInsts 1381604347 # Number of instructions committed +system.cpu.committedOps 1874244950 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_func_calls 80344203 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 1390251708 # To system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits -system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1390251708 # number of overall hits -system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses -system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses -system.cpu.icache.overall_misses 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1392.324437 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1390251708 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1390251708 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1390251708 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1390251708 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1390251708 # number of overall hits +system.cpu.icache.overall_hits::total 1390251708 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses +system.cpu.icache.overall_misses::total 19803 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 372036000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 372036000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 372036000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 372036000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 372036000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 372036000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1390271511 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1390271511 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1390271511 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1390271511 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312627000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 312627000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312627000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 312627000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312627000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 312627000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 895757409 # To system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 895737439 # number of overall hits -system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses -system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.960333 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999746 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999746 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 618874541 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 618874541 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 895737439 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 895737439 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 895737439 # number of overall hits +system.cpu.dcache.overall_hits::total 895737439 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses +system.cpu.dcache.overall_misses::total 1533653 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79725982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79725982000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794826000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3794826000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83520808000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83520808000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83520808000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83520808000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 620335414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 620335414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 897271092 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 897271092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107259 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107259 # number of writebacks +system.cpu.dcache.writebacks::total 107259 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75343363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75343363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78919849000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1478755 # number of replacements system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 75453 # To system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 73826 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1479630 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 3041.423322 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 32.598415 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28860.822381 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.092817 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000995 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.880762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.974574 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 49593 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 67139 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107259 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107259 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17546 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 56280 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 73826 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 17546 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 56280 # number of overall hits +system.cpu.l2cache.overall_hits::total 73826 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2257 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1411280 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1413537 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2257 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1477373 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1479630 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2257 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1477373 # number of overall misses +system.cpu.l2cache.overall_misses::total 1479630 # number of overall misses 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+system.cpu.l2cache.overall_miss_latency::total 76940760000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107259 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107259 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72780 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72780 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 19803 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1533653 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1553456 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 19803 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963303 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 59185200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks +system.cpu.l2cache.writebacks::total 66099 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2257 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411280 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1413537 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2257 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1477373 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1479630 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2257 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1477373 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1479630 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56451200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56541480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59094920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59185200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59094920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 59185200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 1b963b10c..90c413b65 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 0aab67a06..8786d03ec 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:28:56 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:15:15 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 32a07ce20..22fcb32bd 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.046914 # Nu sim_ticks 46914279500 # Number of ticks simulated final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107347 # Simulator instruction rate (inst/s) -host_tick_rate 57007816 # Simulator tick rate (ticks/s) -host_mem_usage 216192 # Number of bytes of host memory used -host_seconds 822.94 # Real time elapsed on the host +host_inst_rate 145791 # Simulator instruction rate (inst/s) +host_op_rate 145791 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77424105 # Simulator tick rate (ticks/s) +host_mem_usage 218104 # Number of bytes of host memory used +host_seconds 605.94 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11164096 # Number of bytes read from this memory system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory system.physmem.bytes_written 7712960 # Number of bytes written to this memory @@ -69,9 +71,10 @@ system.cpu.comNops 8748916 # Nu system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed system.cpu.comInts 30791227 # Number of Integer instructions committed system.cpu.comFloats 151453 # Number of Floating Point instructions committed -system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads @@ -125,26 +128,39 @@ system.cpu.icache.total_refs 12263478 # To system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1886.858130 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.921317 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12263478 # number of ReadReq hits -system.cpu.icache.demand_hits 12263478 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12263478 # number of overall hits -system.cpu.icache.ReadReq_misses 116984 # number of ReadReq misses -system.cpu.icache.demand_misses 116984 # number of demand (read+write) misses -system.cpu.icache.overall_misses 116984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 2068004000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 2068004000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 2068004000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12380462 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12380462 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12380462 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.009449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.009449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.009449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 17677.665322 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 17677.665322 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 17677.665322 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1886.858130 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921317 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921317 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12263478 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12263478 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12263478 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12263478 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12263478 # number of overall hits +system.cpu.icache.overall_hits::total 12263478 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 116984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 116984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 116984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 116984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 116984 # number of overall misses +system.cpu.icache.overall_misses::total 116984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2068004000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2068004000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2068004000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2068004000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2068004000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2068004000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12380462 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12380462 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12380462 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12380462 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12380462 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12380462 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009449 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009449 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009449 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.665322 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 31328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 31328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 31328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 85656 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 85656 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 85656 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 1345401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 1345401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 1345401500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006919 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006919 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15707.031615 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31328 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 31328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 31328 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 31328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 31328 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 31328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 85656 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 85656 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 85656 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 85656 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 85656 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 85656 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1345401500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1345401500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1345401500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1345401500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1345401500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1345401500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15707.031615 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use @@ -181,32 +200,49 @@ system.cpu.dcache.total_refs 34126014 # To system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4073.105766 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994411 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20180445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13945569 # number of WriteReq hits -system.cpu.dcache.demand_hits 34126014 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 34126014 # number of overall hits -system.cpu.dcache.ReadReq_misses 96193 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 667808 # number of WriteReq misses -system.cpu.dcache.demand_misses 764001 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 764001 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4158649000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 35332073000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 39490722000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39490722000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004744 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.045698 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 43232.345389 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52907.531806 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 51689.359045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 51689.359045 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4073.105766 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994411 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994411 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180445 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180445 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945569 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945569 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34126014 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34126014 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34126014 # number of overall hits +system.cpu.dcache.overall_hits::total 34126014 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96193 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667808 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667808 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764001 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764001 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764001 # number of overall misses +system.cpu.dcache.overall_misses::total 764001 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158649000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4158649000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35332073000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35332073000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39490722000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39490722000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39490722000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39490722000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43232.345389 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52907.531806 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161216 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 35426 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 524228 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 559654 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 559654 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 60767 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 204347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2088724500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 7254420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9343144500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9343144500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34372.677605 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.282073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 161216 # number of writebacks +system.cpu.dcache.writebacks::total 161216 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35426 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35426 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524228 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524228 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559654 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559654 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559654 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559654 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254420000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254420000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343144500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9343144500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343144500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9343144500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34372.677605 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.282073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 148060 # number of replacements system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use @@ -248,36 +292,75 @@ system.cpu.l2cache.total_refs 131331 # To system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3005.792321 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15657.764606 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.091730 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.477837 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 103294 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161216 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12270 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 115564 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 115564 # number of overall hits -system.cpu.l2cache.ReadReq_misses 42939 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131500 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 174439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 174439 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 2242306500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 6854385000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9096691500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9096691500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 146233 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161216 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 290003 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 290003 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.293634 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.601508 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.601508 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52148.266729 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52148.266729 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15657.764606 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1362.413436 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1643.378886 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.477837 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.041578 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.050152 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.569567 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 76292 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 27002 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 103294 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 161216 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 161216 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 76292 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39272 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 115564 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 76292 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39272 # number of overall hits +system.cpu.l2cache.overall_hits::total 115564 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 9364 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 33575 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 42939 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131500 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9364 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 165075 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174439 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9364 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 165075 # number of overall misses +system.cpu.l2cache.overall_misses::total 174439 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 489614500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752692000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2242306500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854385000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6854385000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 489614500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8607077000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9096691500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 489614500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8607077000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9096691500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 85656 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146233 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 161216 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 161216 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 85656 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290003 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 85656 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290003 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.109321 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554253 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109321 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.807817 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109321 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.807817 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.896625 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52202.293373 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.600760 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -286,30 +369,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 120515 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 42939 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131500 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 174439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 174439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1718628500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262711000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 6981339500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 6981339500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.601508 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.601508 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 120515 # number of writebacks +system.cpu.l2cache.writebacks::total 120515 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9364 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33575 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 42939 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9364 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606060500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6981339500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 375279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606060500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6981339500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554253 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index ea038d4da..427d5ea46 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 9e435cc97..8276bb368 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:35:02 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:19:29 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 9c4b77b7d..a0babad48 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.021260 # Nu sim_ticks 21259532000 # Number of ticks simulated final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187781 # Simulator instruction rate (inst/s) -host_tick_rate 50157547 # Simulator tick rate (ticks/s) -host_mem_usage 217440 # Number of bytes of host memory used -host_seconds 423.86 # Real time elapsed on the host +host_inst_rate 240617 # Simulator instruction rate (inst/s) +host_op_rate 240617 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64270421 # Simulator tick rate (ticks/s) +host_mem_usage 219780 # Number of bytes of host memory used +host_seconds 330.78 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated +sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11229312 # Number of bytes read from this memory system.physmem.bytes_inst_read 642688 # Number of instructions bytes read from this memory system.physmem.bytes_written 7713344 # Number of bytes written to this memory @@ -272,6 +274,7 @@ system.cpu.iew.wb_rate 2.037162 # in system.cpu.iew.wb_fanout 0.767384 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions +system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions system.cpu.commit.commitSquashedInsts 8835054 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 366565 # The number of times a branch was mispredicted @@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 40775556 # Number of insts commited each cycle -system.cpu.commit.count 88340672 # Number of instructions committed +system.cpu.commit.committedInsts 88340672 # Number of instructions committed +system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 34890015 # Number of memory references committed system.cpu.commit.loads 20276638 # Number of loads committed @@ -308,6 +312,7 @@ system.cpu.rob.rob_writes 195703293 # Th system.cpu.timesIdled 15923 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 394564 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated +system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated system.cpu.cpi 0.534214 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.534214 # CPI: Total CPI of All Threads @@ -325,26 +330,39 @@ system.cpu.icache.total_refs 13782143 # To system.cpu.icache.sampled_refs 90426 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 152.413498 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 17839872000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1927.638696 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.941230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 13782143 # number of ReadReq hits -system.cpu.icache.demand_hits 13782143 # number of demand (read+write) hits -system.cpu.icache.overall_hits 13782143 # number of overall hits -system.cpu.icache.ReadReq_misses 94908 # number of ReadReq misses -system.cpu.icache.demand_misses 94908 # number of demand (read+write) misses -system.cpu.icache.overall_misses 94908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 914028500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 914028500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 914028500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 13877051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 13877051 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 13877051 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.006839 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.006839 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.006839 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 9630.679184 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 9630.679184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 9630.679184 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1927.638696 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.941230 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.941230 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13782143 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13782143 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13782143 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13782143 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13782143 # number of overall hits +system.cpu.icache.overall_hits::total 13782143 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 94908 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 94908 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 94908 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 94908 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 94908 # number of overall misses +system.cpu.icache.overall_misses::total 94908 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 914028500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 914028500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 914028500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 914028500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 914028500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 914028500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13877051 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13877051 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13877051 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13877051 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13877051 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13877051 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006839 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006839 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006839 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9630.679184 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 9630.679184 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 9630.679184 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 4481 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 4481 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 4481 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 90427 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 90427 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 90427 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 542589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 542589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 542589500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006516 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006516 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006516 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6000.304113 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6000.304113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6000.304113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4481 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4481 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4481 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4481 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4481 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4481 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 90427 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 90427 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 90427 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 90427 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 90427 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 90427 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 542589500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 542589500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 542589500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 542589500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 542589500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 542589500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6000.304113 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6000.304113 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6000.304113 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 201340 # number of replacements system.cpu.dcache.tagsinuse 4076.154176 # Cycle average of tags in use @@ -381,34 +402,53 @@ system.cpu.dcache.total_refs 34207250 # To system.cpu.dcache.sampled_refs 205436 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 166.510495 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 157430000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.154176 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995155 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20628725 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13578476 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 49 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 34207201 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 34207201 # number of overall hits -system.cpu.dcache.ReadReq_misses 257071 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1034901 # number of WriteReq misses -system.cpu.dcache.demand_misses 1291972 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1291972 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8273144500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 33900181500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 42173326000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 42173326000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20885796 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 49 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 35499173 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 35499173 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.012308 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.070819 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.036394 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.036394 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32182.332896 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32756.931822 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32642.600614 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32642.600614 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4076.154176 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995155 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995155 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20628725 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20628725 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13578476 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13578476 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34207201 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34207201 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34207201 # number of overall hits +system.cpu.dcache.overall_hits::total 34207201 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 257071 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 257071 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1034901 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1034901 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1291972 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1291972 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1291972 # number of overall misses +system.cpu.dcache.overall_misses::total 1291972 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8273144500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8273144500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33900181500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33900181500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42173326000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42173326000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42173326000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42173326000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20885796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20885796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35499173 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35499173 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35499173 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35499173 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012308 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070819 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036394 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036394 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32182.332896 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32756.931822 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.600614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.600614 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 53500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked @@ -417,32 +457,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2675 system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161613 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 195029 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 891507 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1086536 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1086536 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 62042 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143394 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 205436 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 205436 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1278233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4733826000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6012059000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6012059000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002971 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005787 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005787 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20602.704619 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33012.720197 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29264.875679 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29264.875679 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 161613 # number of writebacks +system.cpu.dcache.writebacks::total 161613 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 195029 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 195029 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891507 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891507 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1086536 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1086536 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1086536 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1086536 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62042 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62042 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205436 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205436 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205436 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205436 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1278233000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1278233000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733826000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733826000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6012059000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6012059000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6012059000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6012059000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002971 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005787 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005787 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20602.704619 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33012.720197 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29264.875679 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29264.875679 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 149119 # number of replacements system.cpu.l2cache.tagsinuse 18923.797261 # Cycle average of tags in use @@ -450,36 +498,75 @@ system.cpu.l2cache.total_refs 136861 # To system.cpu.l2cache.sampled_refs 174485 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.784371 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3200.297768 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15723.499493 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.097665 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.479843 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 108391 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161613 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12014 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 120405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 120405 # number of overall hits -system.cpu.l2cache.ReadReq_misses 44050 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131408 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 175458 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 175458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1516062500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4525488500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 6041551000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 6041551000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 152441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143422 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 295863 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 295863 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.288964 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.916233 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.593038 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.593038 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34416.855846 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34438.455041 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34433.032407 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34433.032407 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15723.499493 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1497.146716 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1703.151052 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.479843 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.045689 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.051976 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.577508 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 80385 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 28006 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 108391 # 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number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131408 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131408 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10042 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 165416 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 175458 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10042 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 165416 # number of overall misses +system.cpu.l2cache.overall_misses::total 175458 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 344615000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1171447500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1516062500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4525488500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4525488500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 344615000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5696936000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6041551000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 344615000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5696936000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6041551000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 90427 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62014 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 152441 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 161613 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 161613 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143422 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143422 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 90427 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 295863 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 90427 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 295863 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111051 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.548392 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.916233 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111051 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.805195 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111051 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.805195 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.367058 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34446.233239 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34438.455041 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.367058 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.054166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.367058 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.054166 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,30 +575,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 120521 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 44050 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131408 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 175458 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 175458 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1367587500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118168500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5485756000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5485756000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.288964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.916233 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.593038 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.593038 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31046.254257 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31338.795964 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31265.351252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31265.351252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 120521 # number of writebacks +system.cpu.l2cache.writebacks::total 120521 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10042 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34008 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 44050 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131408 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131408 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10042 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 175458 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10042 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165416 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 175458 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 312130500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1055457000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1367587500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4118168500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4118168500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 312130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5173625500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5485756000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 312130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5173625500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5485756000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.548392 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916233 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.805195 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.805195 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.503485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.550459 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31338.795964 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index d8535707b..cf8e1051d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout index 160c80ddb..0548e6bad 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:42:17 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:25:10 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 4fc91e266..45c7e3698 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3998504 # Simulator instruction rate (inst/s) -host_tick_rate 2001543652 # Simulator tick rate (ticks/s) -host_mem_usage 206876 # Number of bytes of host memory used -host_seconds 22.09 # Real time elapsed on the host +host_inst_rate 5044223 # Simulator instruction rate (inst/s) +host_op_rate 5044217 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2524999281 # Simulator tick rate (ticks/s) +host_mem_usage 208636 # Number of bytes of host memory used +host_seconds 17.51 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read 480454939 # Number of bytes read from this memory system.physmem.bytes_inst_read 353752292 # Number of instructions bytes read from this memory system.physmem.bytes_written 91652896 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4583 # Nu system.cpu.numCycles 88442007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.committedInsts 88340673 # Number of instructions committed +system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses system.cpu.num_func_calls 3321606 # number of times a function call or return occured diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index f99b5fb55..4c4894527 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout index e74b48d2a..471c7b55a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:42:49 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:25:32 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 59b869a9f..c906eecdf 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.134277 # Nu sim_ticks 134276988000 # Number of ticks simulated final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1801981 # Simulator instruction rate (inst/s) -host_tick_rate 2738992827 # Simulator tick rate (ticks/s) -host_mem_usage 215584 # Number of bytes of host memory used -host_seconds 49.02 # Real time elapsed on the host +host_inst_rate 2261546 # Simulator instruction rate (inst/s) +host_op_rate 2261545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3437525661 # Simulator tick rate (ticks/s) +host_mem_usage 217500 # Number of bytes of host memory used +host_seconds 39.06 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11121920 # Number of bytes read from this memory system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory system.physmem.bytes_written 7712384 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4583 # Nu system.cpu.numCycles 268553976 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.committedInsts 88340673 # Number of instructions committed +system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses system.cpu.num_func_calls 3321606 # number of times a function call or return occured @@ -79,26 +82,39 @@ system.cpu.icache.total_refs 88361638 # To system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses -system.cpu.icache.overall_misses 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1436470000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1436470000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 18793.107960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1871.404551 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913772 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913772 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits +system.cpu.icache.overall_hits::total 88361638 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses +system.cpu.icache.overall_misses::total 76436 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1436470000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1436470000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1436470000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1436470000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1436470000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1436470000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 1207162000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 1207162000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 1207162000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1207162000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1207162000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1207162000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1207162000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1207162000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1207162000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use @@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 34685671 # To system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995815 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2261000000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 7532210000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 9793210000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9793210000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 47925.116470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4078.858373 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995815 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995815 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits +system.cpu.dcache.overall_hits::total 34685671 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses +system.cpu.dcache.overall_misses::total 204344 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2261000000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2261000000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7532210000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7532210000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9793210000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9793210000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9793210000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9793210000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161222 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 204344 # 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number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7101476000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7101476000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9180178000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9180178000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9180178000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9180178000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 147405 # number of replacements system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use @@ -199,36 +232,75 @@ system.cpu.l2cache.total_refs 122958 # To system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 94901 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1305.254425 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1501.295351 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.482430 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.039833 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.045816 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.568079 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 67713 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 27188 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 94901 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 161222 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 161222 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12099 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,30 +309,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 120506 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 120506 # number of writebacks +system.cpu.l2cache.writebacks::total 120506 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8723 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 42301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131479 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131479 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8723 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165057 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 173780 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8723 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165057 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 173780 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 348920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1692040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5259160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5259160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 348920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6602280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6951200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 348920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.915732 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 18c9a5809..1d9e3541a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 08b53cf2f..e2d26e372 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:22 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:25:27 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index b5c5ac05d..228286404 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.031189 # Nu sim_ticks 31189496500 # Number of ticks simulated final_tick 31189496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53036 # Simulator instruction rate (inst/s) -host_tick_rate 16437569 # Simulator tick rate (ticks/s) -host_mem_usage 264816 # Number of bytes of host memory used -host_seconds 1897.45 # Real time elapsed on the host -sim_insts 100634170 # Number of instructions simulated +host_inst_rate 144507 # Simulator instruction rate (inst/s) +host_op_rate 205068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63556485 # Simulator tick rate (ticks/s) +host_mem_usage 231932 # Number of bytes of host memory used +host_seconds 490.74 # Real time elapsed on the host +sim_insts 70914922 # Number of instructions simulated +sim_ops 100634170 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8651712 # Number of bytes read from this memory system.physmem.bytes_inst_read 350080 # Number of instructions bytes read from this memory system.physmem.bytes_written 5661248 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.689926 # insts written-back per cycle system.cpu.iew.wb_fanout 0.519070 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100639722 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 70920474 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100639722 # The number of committed instructions system.cpu.commit.commitSquashedInsts 11954174 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 703033 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 788567 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 59169182 # Number of insts commited each cycle -system.cpu.commit.count 100639722 # Number of instructions committed +system.cpu.commit.committedInsts 70920474 # Number of instructions committed +system.cpu.commit.committedOps 100639722 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 47865761 # Number of memory references committed system.cpu.commit.loads 27308566 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 166686934 # Th system.cpu.rob.rob_writes 227096473 # The number of ROB writes system.cpu.timesIdled 61617 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 1306838 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100634170 # Number of Instructions Simulated -system.cpu.committedInsts_total 100634170 # Number of Instructions Simulated -system.cpu.cpi 0.619859 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.619859 # CPI: Total CPI of All Threads -system.cpu.ipc 1.613270 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.613270 # IPC: Total IPC of All Threads +system.cpu.committedInsts 70914922 # Number of Instructions Simulated +system.cpu.committedOps 100634170 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70914922 # Number of Instructions Simulated +system.cpu.cpi 0.879631 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.879631 # CPI: Total CPI of All Threads +system.cpu.ipc 1.136840 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.136840 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 511674990 # number of integer regfile reads system.cpu.int_regfile_writes 103897673 # number of integer regfile writes system.cpu.fp_regfile_reads 166 # number of floating regfile reads @@ -336,26 +341,39 @@ system.cpu.icache.total_refs 12180358 # To system.cpu.icache.sampled_refs 28166 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 432.448981 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1805.600642 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.881641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12180359 # number of ReadReq hits -system.cpu.icache.demand_hits 12180359 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12180359 # number of overall hits -system.cpu.icache.ReadReq_misses 29272 # number of ReadReq misses -system.cpu.icache.demand_misses 29272 # number of demand (read+write) misses -system.cpu.icache.overall_misses 29272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 357988500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 357988500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 357988500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12209631 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12209631 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12209631 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002397 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002397 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002397 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12229.724652 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12229.724652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12229.724652 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1805.600642 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.881641 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.881641 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12180359 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12180359 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12180359 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12180359 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12180359 # number of overall hits +system.cpu.icache.overall_hits::total 12180359 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 29272 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 29272 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 29272 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 29272 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 29272 # number of overall misses +system.cpu.icache.overall_misses::total 29272 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 357988500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 357988500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 357988500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 357988500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 357988500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 357988500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12209631 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12209631 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12209631 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12209631 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12209631 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12209631 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002397 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002397 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002397 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12229.724652 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,27 +382,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1063 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1063 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1063 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 28209 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 28209 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 28209 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 247071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 247071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 247071500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002310 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002310 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8758.605410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8758.605410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8758.605410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1063 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1063 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1063 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1063 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1063 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1063 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28209 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28209 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28209 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28209 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28209 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28209 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 247071500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 247071500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 247071500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 247071500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 247071500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 247071500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8758.605410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157892 # number of replacements system.cpu.dcache.tagsinuse 4072.334227 # Cycle average of tags in use @@ -392,40 +415,63 @@ system.cpu.dcache.total_refs 44746410 # To system.cpu.dcache.sampled_refs 161988 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 276.232869 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 306594000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4072.334227 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994222 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26399659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18310286 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 18924 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17376 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 44709945 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 44709945 # number of overall hits -system.cpu.dcache.ReadReq_misses 108879 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1539615 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 26 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1648494 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1648494 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2418798500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 52283607500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 349000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 54702406000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 54702406000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 26508538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 18950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17376 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46358439 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46358439 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004107 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001372 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035560 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035560 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22215.473140 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33958.884202 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 13423.076923 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33183.260600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33183.260600 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4072.334227 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994222 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994222 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26399659 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26399659 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18310286 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18310286 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 18924 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18924 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 17376 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 17376 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44709945 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44709945 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44709945 # number of overall hits +system.cpu.dcache.overall_hits::total 44709945 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 108879 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 108879 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1539615 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1539615 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1648494 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1648494 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1648494 # number of overall misses +system.cpu.dcache.overall_misses::total 1648494 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2418798500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2418798500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52283607500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52283607500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 349000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 349000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54702406000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54702406000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54702406000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54702406000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26508538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26508538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18950 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18950 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 17376 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 17376 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46358439 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46358439 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46358439 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46358439 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004107 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077563 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035560 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035560 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22215.473140 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33958.884202 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.076923 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,33 +480,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123473 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 53766 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1432695 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 26 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1486461 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1486461 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55113 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106920 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 162033 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 162033 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1035745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3662420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4698165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4698165500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002079 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003495 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003495 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18793.125034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.834643 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 28995.115193 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 28995.115193 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 123473 # number of writebacks +system.cpu.dcache.writebacks::total 123473 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53766 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53766 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432695 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1432695 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 26 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 26 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1486461 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1486461 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1486461 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1486461 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55113 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55113 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106920 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106920 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162033 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162033 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162033 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162033 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1035745500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1035745500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3662420000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3662420000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4698165500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4698165500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698165500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4698165500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002079 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005386 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18793.125034 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34253.834643 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 114916 # number of replacements system.cpu.l2cache.tagsinuse 18304.706842 # Cycle average of tags in use @@ -468,40 +523,82 @@ system.cpu.l2cache.total_refs 72481 # To system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.541817 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2370.559791 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15934.147051 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072344 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486272 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 50571 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 123474 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 14 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 4310 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 54881 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 54881 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32667 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 30 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 102597 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 135264 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 135264 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1118379000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3526118000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4644497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4644497000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 83238 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 123474 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 44 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 190145 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 190145 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.392453 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.681818 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.959685 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.711373 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.711373 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34235.742492 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.626763 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34336.534481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34336.534481 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15934.147051 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 839.668596 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1530.891195 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.486272 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.025625 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.046719 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.558615 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 22667 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 27904 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 50571 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 123474 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 123474 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 14 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 14 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4310 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4310 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22667 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 32214 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 54881 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22667 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 32214 # number of overall hits +system.cpu.l2cache.overall_hits::total 54881 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 5494 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27173 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 32667 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102597 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102597 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5494 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 129770 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 135264 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5494 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 129770 # number of overall misses +system.cpu.l2cache.overall_misses::total 135264 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188188000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 930191000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1118379000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3526118000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3526118000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 188188000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4456309000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4644497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 188188000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4456309000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4644497000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 28161 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55077 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 83238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 123474 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 123474 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 106907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 28161 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 161984 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 190145 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 28161 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 161984 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 190145 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.195093 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.493364 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.681818 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959685 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.195093 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.801129 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.195093 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.801129 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.367310 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34232.179001 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.626763 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,35 +607,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88457 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32586 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 30 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102597 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 135183 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 135183 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1012814500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 931000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197894500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4210709000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4210709000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391480 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.681818 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959685 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.710947 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.710947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.277236 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31033.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.473766 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31148.213903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31148.213903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 88457 # number of writebacks +system.cpu.l2cache.writebacks::total 88457 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5470 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27116 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32586 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102597 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102597 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5470 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 129713 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 135183 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5470 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129713 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 135183 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169929500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 842885000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1012814500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 931000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 931000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3197894500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3197894500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169929500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4040779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4210709000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169929500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4040779500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4210709000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.492329 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.681818 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959685 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.722121 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31084.415105 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31033.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31169.473766 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 321a621c1..e57dda708 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index cba7edc9e..1d79bb34d 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:35:25 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:26:23 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 550377594..89b488ea9 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.053932 # Nu sim_ticks 53932162000 # Number of ticks simulated final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3016681 # Simulator instruction rate (inst/s) -host_tick_rate 1616735818 # Simulator tick rate (ticks/s) -host_mem_usage 217624 # Number of bytes of host memory used -host_seconds 33.36 # Real time elapsed on the host -sim_insts 100632437 # Number of instructions simulated +host_inst_rate 2464229 # Simulator instruction rate (inst/s) +host_op_rate 3496968 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1874136829 # Simulator tick rate (ticks/s) +host_mem_usage 220180 # Number of bytes of host memory used +host_seconds 28.78 # Real time elapsed on the host +sim_insts 70913189 # Number of instructions simulated +sim_ops 100632437 # Number of ops (including micro ops) simulated system.physmem.bytes_read 419153654 # Number of bytes read from this memory system.physmem.bytes_inst_read 312580308 # Number of instructions bytes read from this memory system.physmem.bytes_written 78660211 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 107864325 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 100632437 # Number of instructions executed +system.cpu.committedInsts 70913189 # Number of instructions committed +system.cpu.committedOps 100632437 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 62eb4cdbf..a85bd162d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index 4fb750502..3a0d84b6b 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:36:06 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:27:02 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 2fff6cef5..0f7cee094 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.133117 # Nu sim_ticks 133117442000 # Number of ticks simulated final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1410680 # Simulator instruction rate (inst/s) -host_tick_rate 1881780580 # Simulator tick rate (ticks/s) -host_mem_usage 226592 # Number of bytes of host memory used -host_seconds 70.74 # Real time elapsed on the host -sim_insts 99791663 # Number of instructions simulated +host_inst_rate 1269489 # Simulator instruction rate (inst/s) +host_op_rate 1800168 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2401339947 # Simulator tick rate (ticks/s) +host_mem_usage 229088 # Number of bytes of host memory used +host_seconds 55.43 # Real time elapsed on the host +sim_insts 70373636 # Number of instructions simulated +sim_ops 99791663 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8570688 # Number of bytes read from this memory system.physmem.bytes_inst_read 294208 # Number of instructions bytes read from this memory system.physmem.bytes_written 5660736 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 266234884 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 99791663 # Number of instructions executed +system.cpu.committedInsts 70373636 # Number of instructions committed +system.cpu.committedOps 99791663 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 78126170 # To system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 78126170 # number of ReadReq hits -system.cpu.icache.demand_hits 78126170 # number of demand (read+write) hits -system.cpu.icache.overall_hits 78126170 # number of overall hits -system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses -system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses -system.cpu.icache.overall_misses 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 457786000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 457786000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 457786000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 78145078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 78145078 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 24211.233340 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 24211.233340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1736.182852 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847746 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847746 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 78126170 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126170 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126170 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126170 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126170 # number of overall hits +system.cpu.icache.overall_hits::total 78126170 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses +system.cpu.icache.overall_misses::total 18908 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 457786000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 457786000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 457786000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 457786000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 457786000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 457786000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78145078 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145078 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145078 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145078 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145078 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 401062000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 401062000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 401062000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401062000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 401062000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 401062000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 401062000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401062000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 401062000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 46862075 # To system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 27087368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 19742869 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 46830237 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 46830237 # number of overall hits -system.cpu.dcache.ReadReq_misses 52966 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 107032 # number of WriteReq misses -system.cpu.dcache.demand_misses 159998 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 1862630000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 5808782000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7671412000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7671412000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 27140334 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46990235 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.003405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 47946.924337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4076.934010 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995345 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995345 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 27087368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27087368 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46830237 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46830237 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46830237 # number of overall hits +system.cpu.dcache.overall_hits::total 46830237 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses +system.cpu.dcache.overall_misses::total 159998 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1862630000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1862630000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5808782000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5808782000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7671412000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7671412000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7671412000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7671412000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27140334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27140334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46990235 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46990235 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46990235 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46990235 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 122808 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 52966 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 107032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 159998 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1703732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5487686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7191418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7191418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003405 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 122808 # number of writebacks +system.cpu.dcache.writebacks::total 122808 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1703732000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1703732000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5487686000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5487686000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7191418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7191418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7191418000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7191418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 113660 # number of replacements system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 61800 # To system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16025.699940 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066099 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.489066 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 40584 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 122808 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 4405 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 44989 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 44989 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31290 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 102627 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 133917 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 133917 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1627080000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 5336604000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 6963684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 6963684000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 122808 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 178906 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.435345 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.958844 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.748533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.748533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16025.699940 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 701.722418 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1464.198671 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.489066 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021415 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.044684 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.555164 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14311 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 26273 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40584 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 122808 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 122808 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4405 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4405 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14311 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 30678 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 44989 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14311 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 30678 # number of overall hits +system.cpu.l2cache.overall_hits::total 44989 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4597 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 26693 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 31290 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102627 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102627 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4597 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 129320 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 133917 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4597 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 129320 # number of overall misses +system.cpu.l2cache.overall_misses::total 133917 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239044000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1388036000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1627080000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5336604000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5336604000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 239044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6724640000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6963684000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 239044000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6724640000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6963684000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 122808 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 122808 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243125 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.503965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.958844 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243125 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.808260 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243125 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.808260 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88449 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102627 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 133917 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 133917 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1251600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4105080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5356680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5356680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.435345 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.748533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.748533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 88449 # number of writebacks +system.cpu.l2cache.writebacks::total 88449 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4597 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 26693 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31290 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102627 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102627 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 129320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 133917 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4597 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129320 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 133917 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1067720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1251600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4105080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4105080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5172800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5356680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5172800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5356680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.503965 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.958844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 2df6b792d..4295b5950 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic +cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 542479326..7e99d8ae7 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:24:20 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:00:16 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index dc6c31998..12070ccfb 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.068149 # Nu sim_ticks 68148678500 # Number of ticks simulated final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3420916 # Simulator instruction rate (inst/s) -host_tick_rate 1712444497 # Simulator tick rate (ticks/s) -host_mem_usage 214012 # Number of bytes of host memory used -host_seconds 39.80 # Real time elapsed on the host -sim_insts 136139203 # Number of instructions simulated +host_inst_rate 3965699 # Simulator instruction rate (inst/s) +host_op_rate 4017046 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2010855033 # Simulator tick rate (ticks/s) +host_mem_usage 211680 # Number of bytes of host memory used +host_seconds 33.89 # Real time elapsed on the host +sim_insts 134398975 # Number of instructions simulated +sim_ops 136139203 # Number of ops (including micro ops) simulated system.physmem.bytes_read 685773693 # Number of bytes read from this memory system.physmem.bytes_inst_read 538214332 # Number of instructions bytes read from this memory system.physmem.bytes_written 89882950 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 136297358 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 136139203 # Number of instructions executed +system.cpu.committedInsts 134398975 # Number of instructions committed +system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 5e34ae7a1..2507c0ed4 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index 787eaa97a..a6a3d32b7 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:24:48 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:01:00 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 168a8eefa..b24bd2c93 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.202942 # Nu sim_ticks 202941992000 # Number of ticks simulated final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1608666 # Simulator instruction rate (inst/s) -host_tick_rate 2398029397 # Simulator tick rate (ticks/s) -host_mem_usage 222724 # Number of bytes of host memory used -host_seconds 84.63 # Real time elapsed on the host -sim_insts 136139203 # Number of instructions simulated +host_inst_rate 1927976 # Simulator instruction rate (inst/s) +host_op_rate 1952939 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2911235123 # Simulator tick rate (ticks/s) +host_mem_usage 220544 # Number of bytes of host memory used +host_seconds 69.71 # Real time elapsed on the host +sim_insts 134398975 # Number of instructions simulated +sim_ops 136139203 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8970304 # Number of bytes read from this memory system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory system.physmem.bytes_written 5584960 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 405883984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 136139203 # Number of instructions executed +system.cpu.committedInsts 134398975 # Number of instructions committed +system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 134366560 # To system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 2004.721102 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.978868 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits -system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits -system.cpu.icache.overall_hits 134366560 # number of overall hits -system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses -system.cpu.icache.overall_misses 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 3166478000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 3166478000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 3166478000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 16930.864488 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 16930.864488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 16930.864488 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 2004.721102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978868 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978868 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134366560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134366560 # number of overall hits +system.cpu.icache.overall_hits::total 134366560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses +system.cpu.icache.overall_misses::total 187024 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3166478000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3166478000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3166478000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3166478000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3166478000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3166478000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 134553584 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 134553584 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 2605406000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 2605406000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 2605406000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 13930.864488 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2605406000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2605406000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2605406000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2605406000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2605406000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2605406000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use @@ -102,38 +116,59 @@ system.cpu.dcache.total_refs 57960843 # To system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.617150 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997953 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 1709246000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 5738404000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 462000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 7447650000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7447650000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37566.671795 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54566.239398 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 30800 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 49432.508313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 49432.508313 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4087.617150 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997953 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997953 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 57944942 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944942 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944942 # number of overall hits +system.cpu.dcache.overall_hits::total 57944942 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45499 # 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number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 462000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 462000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7447650000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7447650000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7447650000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7447650000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 58095605 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 58095605 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 58095605 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 58095605 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 30800 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 118818 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1572749000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5422912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 417000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6995661000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6995661000 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1572749000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1572749000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5422912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5422912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 417000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 417000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6995661000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6995661000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6995661000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6995661000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 27800 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 120138 # number of replacements system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use @@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs 212003 # To system.cpu.l2cache.sampled_refs 139002 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.525179 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3965.924560 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15768.107062 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.121030 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.481204 # 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average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15768.107062 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2612.732810 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1353.191750 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.481204 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.079734 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.041296 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.602235 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 173973 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 19969 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 193942 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 118818 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 118818 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6609720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7288372000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 678652000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6609720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7288372000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 118818 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 118818 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.069782 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.561111 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965782 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069782 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.843587 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069782 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.843587 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 87265 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 38581 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 101580 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 140161 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 140161 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1543240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4063200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5606440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5606440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165923 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.965782 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.415043 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.415043 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 87265 # number of writebacks +system.cpu.l2cache.writebacks::total 87265 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13051 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 25530 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101580 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101580 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13051 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 127110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 140161 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13051 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 127110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 140161 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 522040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1021200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1543240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4063200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4063200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 522040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5084400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5606440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 522040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5084400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5606440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.561111 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965782 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 0d09e2e14..103775415 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 8bc14bb8a..d36129661 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:42:50 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:25:39 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index bf815a6e1..d5a78ee76 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.009857 # Nu sim_ticks 1009857089500 # Number of ticks simulated final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102085 # Simulator instruction rate (inst/s) -host_tick_rate 56650413 # Simulator tick rate (ticks/s) -host_mem_usage 208040 # Number of bytes of host memory used -host_seconds 17826.12 # Real time elapsed on the host +host_inst_rate 137029 # Simulator instruction rate (inst/s) +host_op_rate 137029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76042102 # Simulator tick rate (ticks/s) +host_mem_usage 209964 # Number of bytes of host memory used +host_seconds 13280.24 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated +sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172617984 # Number of bytes read from this memory system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory system.physmem.bytes_written 74938304 # Number of bytes written to this memory @@ -69,9 +71,10 @@ system.cpu.comNops 83736345 # Nu system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed system.cpu.comInts 916086844 # Number of Integer instructions committed system.cpu.comFloats 190 # Number of Floating Point instructions committed -system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads @@ -125,26 +128,39 @@ system.cpu.icache.total_refs 233079667 # To system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 664.479191 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.324453 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 233079667 # number of ReadReq hits -system.cpu.icache.demand_hits 233079667 # number of demand (read+write) hits -system.cpu.icache.overall_hits 233079667 # number of overall hits -system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses -system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1062 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 58337000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 58337000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 58337000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 233080729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 233080729 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 233080729 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54931.261770 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54931.261770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54931.261770 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 664.479191 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.324453 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.324453 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 233079667 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 233079667 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 233079667 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 233079667 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 233079667 # number of overall hits +system.cpu.icache.overall_hits::total 233079667 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1062 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1062 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1062 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1062 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1062 # number of overall misses +system.cpu.icache.overall_misses::total 1062 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58337000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58337000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58337000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58337000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58337000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58337000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 233080729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 233080729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 233080729 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 233080729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 233080729 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 233080729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54931.261770 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 204 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 204 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 204 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 858 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45872500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45872500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45872500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 204 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 204 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 204 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 204 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 858 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 858 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 858 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45872500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45872500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45872500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45872500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45872500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45872500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53464.452214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use @@ -181,32 +200,49 @@ system.cpu.dcache.total_refs 595070081 # To system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4082.611665 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.996731 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 437271428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 157798653 # number of WriteReq hits -system.cpu.dcache.demand_hits 595070081 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 595070081 # number of overall hits -system.cpu.dcache.ReadReq_misses 7324235 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 2929849 # number of WriteReq misses -system.cpu.dcache.demand_misses 10254084 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 10254084 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 180892053500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110288339500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 291180393000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 291180393000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.018229 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 28396.528934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 28396.528934 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4082.611665 # Average occupied blocks per requestor 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+system.cpu.dcache.demand_miss_latency::total 291180393000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 291180393000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 291180393000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24697.740242 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.011466 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked @@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 101953 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1040683 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1142636 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1142636 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 59191835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215279506500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215279506500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks +system.cpu.dcache.writebacks::total 3058572 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101953 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101953 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1040683 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1142636 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1142636 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1142636 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1142636 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889166 # number of WriteReq MSHR misses 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MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215279506500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215279506500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21611.960181 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.257462 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency 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-system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6415150 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6415150 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1807881 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2697156 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94453509000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46507390000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 140960899000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 140960899000 # number of overall miss cycles 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52262.790510 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52262.790510 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 10843.964569 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.537327 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15484.737472 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.330932 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.472557 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.804298 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3058572 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1000333 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1000333 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6415150 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits +system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 858 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1807023 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1807881 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 889275 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 889275 # number of ReadExReq misses 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+system.cpu.l2cache.demand_miss_latency::cpu.inst 44903500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 140915995500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 140960899000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44903500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 140915995500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 140960899000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 858 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221840 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3058572 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3058572 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889608 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889608 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 858 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112306 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 858 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52335.081585 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52245.381215 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52298.096764 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -286,30 +366,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1170911 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1807881 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 889275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72354298500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671113500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 108025412000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 108025412000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks +system.cpu.l2cache.writebacks::total 1170911 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1807881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889275 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 889275 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2696298 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2697156 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2696298 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2697156 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34440500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319858000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671113500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671113500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34440500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108025412000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34440500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990971500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108025412000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.442890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.548149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.578786 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 4951679e2..66f7d63e2 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 35ea78ab1..17636478e 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:43:49 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:26:22 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 3e098da07..a211c592b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.615292 # Nu sim_ticks 615292058500 # Number of ticks simulated final_tick 615292058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151558 # Simulator instruction rate (inst/s) -host_tick_rate 53715526 # Simulator tick rate (ticks/s) -host_mem_usage 208624 # Number of bytes of host memory used -host_seconds 11454.64 # Real time elapsed on the host +host_inst_rate 195644 # Simulator instruction rate (inst/s) +host_op_rate 195644 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69340417 # Simulator tick rate (ticks/s) +host_mem_usage 211040 # Number of bytes of host memory used +host_seconds 8873.50 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated +sim_ops 1736043781 # Number of ops (including micro ops) simulated system.physmem.bytes_read 173080384 # Number of bytes read from this memory system.physmem.bytes_inst_read 60288 # Number of instructions bytes read from this memory system.physmem.bytes_written 74996480 # Number of bytes written to this memory @@ -272,6 +274,7 @@ system.cpu.iew.wb_rate 1.916228 # in system.cpu.iew.wb_fanout 0.790955 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions system.cpu.commit.commitSquashedInsts 736139047 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 19443221 # The number of times a branch was mispredicted @@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 1119336917 # Number of insts commited each cycle -system.cpu.commit.count 1819780126 # Number of instructions committed +system.cpu.commit.committedInsts 1819780126 # Number of instructions committed +system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 605324165 # Number of memory references committed system.cpu.commit.loads 444595663 # Number of loads committed @@ -308,6 +312,7 @@ system.cpu.rob.rob_writes 5217723058 # Th system.cpu.timesIdled 398057 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 5523098 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated +system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated system.cpu.cpi 0.708844 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.708844 # CPI: Total CPI of All Threads @@ -325,26 +330,39 @@ system.cpu.icache.total_refs 385399748 # To system.cpu.icache.sampled_refs 942 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 409129.244161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 746.155324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.364334 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 385399748 # number of ReadReq hits -system.cpu.icache.demand_hits 385399748 # number of demand (read+write) hits -system.cpu.icache.overall_hits 385399748 # number of overall hits -system.cpu.icache.ReadReq_misses 1348 # number of ReadReq misses -system.cpu.icache.demand_misses 1348 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 47398000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 47398000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 47398000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 385401096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 385401096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 385401096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35161.721068 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35161.721068 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35161.721068 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 746.155324 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.364334 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.364334 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 385399748 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 385399748 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 385399748 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 385399748 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 385399748 # number of overall hits +system.cpu.icache.overall_hits::total 385399748 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses +system.cpu.icache.overall_misses::total 1348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47398000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47398000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47398000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47398000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47398000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47398000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 385401096 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 385401096 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 385401096 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 385401096 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 385401096 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 385401096 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.721068 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.721068 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.721068 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 406 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 406 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 942 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 942 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 942 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33448000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33448000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33448000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35507.430998 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35507.430998 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35507.430998 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 406 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 406 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 406 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 406 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 406 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 942 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 942 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 942 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 942 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 942 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 942 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33448000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33448000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33448000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33448000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33448000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33448000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35507.430998 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35507.430998 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35507.430998 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9159821 # number of replacements system.cpu.dcache.tagsinuse 4086.961398 # Cycle average of tags in use @@ -381,38 +402,59 @@ system.cpu.dcache.total_refs 693411949 # To system.cpu.dcache.sampled_refs 9163917 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 75.667637 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5157991000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4086.961398 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997793 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 537597174 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 155814773 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 693411947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 693411947 # number of overall hits -system.cpu.dcache.ReadReq_misses 10313435 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 4913729 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15227164 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15227164 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 172073260500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 137521396881 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 309594657381 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 309594657381 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 547910609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 708639111 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 708639111 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.018823 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.030572 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.021488 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021488 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16684.379210 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27987.175703 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 20331.734615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 20331.734615 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4086.961398 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997793 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997793 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 537597174 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 537597174 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155814773 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155814773 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 693411947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 693411947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 693411947 # number of overall hits +system.cpu.dcache.overall_hits::total 693411947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10313435 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10313435 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4913729 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4913729 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 15227164 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15227164 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15227164 # number of overall misses +system.cpu.dcache.overall_misses::total 15227164 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 172073260500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 172073260500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 137521396881 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 137521396881 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 38500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 309594657381 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 309594657381 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 309594657381 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 309594657381 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 547910609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 547910609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 708639111 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 708639111 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 708639111 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 708639111 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018823 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030572 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021488 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021488 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16684.379210 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27987.175703 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20331.734615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20331.734615 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 119268264 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2148368000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 37813 # number of cycles access was blocked @@ -421,36 +463,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.160315 system.cpu.dcache.avg_blocked_cycles::no_targets 32994.455792 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3077535 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3034555 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3028693 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6063248 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6063248 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7278880 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1885036 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9163916 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9163916 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 81039107500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38640356536 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 119679464036 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 119679464036 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013285 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011728 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.012932 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.012932 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11133.458375 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20498.471401 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 13059.860439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 13059.860439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3077535 # number of writebacks +system.cpu.dcache.writebacks::total 3077535 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3034555 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3034555 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3028693 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3028693 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6063248 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6063248 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6063248 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6063248 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7278880 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7278880 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885036 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1885036 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9163916 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9163916 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9163916 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9163916 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 81039107500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 81039107500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38640356536 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 38640356536 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119679464036 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 119679464036 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119679464036 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 119679464036 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013285 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011728 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012932 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012932 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11133.458375 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20498.471401 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13059.860439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13059.860439 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2693797 # number of replacements system.cpu.l2cache.tagsinuse 26669.588705 # Cycle average of tags in use @@ -458,36 +510,72 @@ system.cpu.l2cache.total_refs 7633154 # To system.cpu.l2cache.sampled_refs 2718439 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.807918 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 126954186500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15903.024773 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10766.563932 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.485322 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.328569 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5458962 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3077535 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1001516 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6460478 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6460478 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1820852 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 883529 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2704381 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2704381 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 62524059000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 30450873000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 92974932000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 92974932000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7279814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3077535 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1885045 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9164859 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9164859 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250123 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.468704 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.295082 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.295082 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34337.803951 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.052081 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34379.376279 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34379.376279 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 10766.563932 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 21.661075 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15881.363698 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.328569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000661 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.484661 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.813891 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5458962 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5458962 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3077535 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3077535 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1001516 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1001516 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6460478 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6460478 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6460478 # number of overall hits +system.cpu.l2cache.overall_hits::total 6460478 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 942 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1819910 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1820852 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 883529 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 883529 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 942 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2703439 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2704381 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 942 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2703439 # number of overall misses +system.cpu.l2cache.overall_misses::total 2704381 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32355500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62491703500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 62524059000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 30450873000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 30450873000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32355500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 92942576500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 92974932000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32355500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 92942576500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 92974932000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 942 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7278872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7279814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3077535 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3077535 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1885045 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1885045 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 942 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9163917 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9164859 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 942 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9163917 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9164859 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250026 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.468704 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.295009 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.295009 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34347.664544 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34337.798847 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.052081 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34347.664544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34379.387329 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34347.664544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34379.387329 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 17570000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1704 # number of cycles access was blocked @@ -496,30 +584,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10311.032864 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1171820 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1820852 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 883529 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2704381 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2704381 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56737753000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 27632234500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 84369987500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 84369987500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250123 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468704 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295082 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.295082 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31160.002570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31274.847232 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31197.522649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31197.522649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1171820 # number of writebacks +system.cpu.l2cache.writebacks::total 1171820 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 942 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1819910 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1820852 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 883529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 883529 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 942 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2703439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2704381 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 942 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2703439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2704381 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29342500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56708410500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56737753000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 27632234500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 27632234500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29342500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84340645000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 84369987500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29342500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84340645000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 84369987500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250026 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468704 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295009 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295009 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31149.150743 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31160.008187 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31274.847232 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31149.150743 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31197.539504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31149.150743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31197.539504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 52ac7c920..d36004a3f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 3465b9fda..632f371aa 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:45:21 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:29:07 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 1f32f6942..2d84c17ba 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4221832 # Simulator instruction rate (inst/s) -host_tick_rate 2118570165 # Simulator tick rate (ticks/s) -host_mem_usage 198896 # Number of bytes of host memory used -host_seconds 431.04 # Real time elapsed on the host +host_inst_rate 5189226 # Simulator instruction rate (inst/s) +host_op_rate 5189226 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2604020675 # Simulator tick rate (ticks/s) +host_mem_usage 200656 # Number of bytes of host memory used +host_seconds 350.68 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated +sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read 9280309971 # Number of bytes read from this memory system.physmem.bytes_inst_read 7305514036 # Number of instructions bytes read from this memory system.physmem.bytes_written 827777307 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 1826378527 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1819780127 # Number of instructions executed +system.cpu.committedInsts 1819780127 # Number of instructions committed +system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses system.cpu.num_func_calls 33534877 # number of times a function call or return occured diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index b74c06509..70d2dba0c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 5e40861f7..91c7dc82f 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:52:43 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:35:09 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 99a911858..52ac717c2 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.663444 # Nu sim_ticks 2663443716000 # Number of ticks simulated final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1948044 # Simulator instruction rate (inst/s) -host_tick_rate 2851171142 # Simulator tick rate (ticks/s) -host_mem_usage 207608 # Number of bytes of host memory used -host_seconds 934.16 # Real time elapsed on the host +host_inst_rate 2433308 # Simulator instruction rate (inst/s) +host_op_rate 2433308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3561407770 # Simulator tick rate (ticks/s) +host_mem_usage 209524 # Number of bytes of host memory used +host_seconds 747.86 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated +sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172614208 # Number of bytes read from this memory system.physmem.bytes_inst_read 51328 # Number of instructions bytes read from this memory system.physmem.bytes_written 74939072 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 5326887432 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1819780127 # Number of instructions executed +system.cpu.committedInsts 1819780127 # Number of instructions committed +system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses system.cpu.num_func_calls 33534877 # number of times a function call or return occured @@ -79,26 +82,39 @@ system.cpu.icache.total_refs 1826377708 # To system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits -system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1826377708 # number of overall hits -system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.demand_misses 802 # number of demand (read+write) misses -system.cpu.icache.overall_misses 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 612.356766 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299002 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299002 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits +system.cpu.icache.overall_hits::total 1826377708 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses +system.cpu.icache.overall_misses::total 802 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44912000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44912000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44912000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44912000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44912000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44912000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42506000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42506000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use @@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 596212431 # To system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits -system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 596212431 # number of overall hits -system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses -system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4079.504248 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995973 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995973 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits +system.cpu.dcache.overall_hits::total 596212431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses +system.cpu.dcache.overall_misses::total 9111734 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177010400000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177010400000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63798266000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63798266000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 240808666000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 240808666000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 240808666000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 240808666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3058802 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3058802 # number of writebacks +system.cpu.dcache.writebacks::total 3058802 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155343158000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 155343158000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58130306000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58130306000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213473464000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 213473464000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213473464000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 213473464000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30767.845574 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686269 # number of replacements system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use @@ -199,36 +232,72 @@ system.cpu.l2cache.total_refs 7565346 # To system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1000087 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6415439 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 889233 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2697097 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 10727.578894 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 29.806952 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15282.701350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.327380 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000910 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.466391 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.794680 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5415352 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5415352 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3058802 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3058802 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1000087 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1000087 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6415439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6415439 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6415439 # number of overall hits +system.cpu.l2cache.overall_hits::total 6415439 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1807062 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3058802 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3058802 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250202 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470663 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.295915 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.295915 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,30 +306,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1170923 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 107883880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295977 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72314560000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35569320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35569320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107851800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 107883880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107851800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 107883880000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250202 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470663 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 5b9d120fe..51e908aa2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 90c937ca7..4a2c04206 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:20 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:28:08 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 8595a64e2..1d3623ac5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.483300 # Nu sim_ticks 483300356500 # Number of ticks simulated final_tick 483300356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96252 # Simulator instruction rate (inst/s) -host_tick_rate 26997552 # Simulator tick rate (ticks/s) -host_mem_usage 256412 # Number of bytes of host memory used -host_seconds 17901.64 # Real time elapsed on the host -sim_insts 1723073849 # Number of instructions simulated +host_inst_rate 175200 # Simulator instruction rate (inst/s) +host_op_rate 195449 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54820940 # Simulator tick rate (ticks/s) +host_mem_usage 223460 # Number of bytes of host memory used +host_seconds 8815.98 # Real time elapsed on the host +sim_insts 1544563036 # Number of instructions simulated +sim_ops 1723073849 # Number of ops (including micro ops) simulated system.physmem.bytes_read 188191232 # Number of bytes read from this memory system.physmem.bytes_inst_read 45952 # Number of instructions bytes read from this memory system.physmem.bytes_written 77928320 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 2.025916 # insts written-back per cycle system.cpu.iew.wb_fanout 0.632400 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 1544563054 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073867 # The number of committed instructions system.cpu.commit.commitSquashedInsts 464107908 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 18315306 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 888130278 # Number of insts commited each cycle -system.cpu.commit.count 1723073867 # Number of instructions committed +system.cpu.commit.committedInsts 1544563054 # Number of instructions committed +system.cpu.commit.committedOps 1723073867 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 660773817 # Number of memory references committed system.cpu.commit.loads 485926771 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 2976436889 # Th system.cpu.rob.rob_writes 4442782654 # The number of ROB writes system.cpu.timesIdled 920078 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 10281556 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1723073849 # Number of Instructions Simulated -system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated -system.cpu.cpi 0.560975 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.560975 # CPI: Total CPI of All Threads -system.cpu.ipc 1.782612 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.782612 # IPC: Total IPC of All Threads +system.cpu.committedInsts 1544563036 # Number of Instructions Simulated +system.cpu.committedOps 1723073849 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563036 # Number of Instructions Simulated +system.cpu.cpi 0.625809 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625809 # CPI: Total CPI of All Threads +system.cpu.ipc 1.597933 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.597933 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 9941434858 # number of integer regfile reads system.cpu.int_regfile_writes 1939754373 # number of integer regfile writes system.cpu.fp_regfile_reads 96 # number of floating regfile reads @@ -336,26 +341,39 @@ system.cpu.icache.total_refs 285077321 # To system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 382141.180965 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 609.966952 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.297835 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 285077321 # number of ReadReq hits -system.cpu.icache.demand_hits 285077321 # number of demand (read+write) hits -system.cpu.icache.overall_hits 285077321 # number of overall hits -system.cpu.icache.ReadReq_misses 1018 # number of ReadReq misses -system.cpu.icache.demand_misses 1018 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35270500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35270500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35270500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 285078339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 285078339 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 285078339 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34646.856582 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34646.856582 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34646.856582 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 609.966952 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.297835 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.297835 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 285077321 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285077321 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285077321 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285077321 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285077321 # number of overall hits +system.cpu.icache.overall_hits::total 285077321 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1018 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1018 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1018 # number of overall misses +system.cpu.icache.overall_misses::total 1018 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35270500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35270500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35270500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35270500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35270500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35270500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 285078339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 285078339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 285078339 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 285078339 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 285078339 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 285078339 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34646.856582 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,27 +382,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 272 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 272 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 272 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25653000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25653000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25653000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34387.399464 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34387.399464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34387.399464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 272 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 272 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 272 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 272 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 272 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 272 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 746 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 746 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 746 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25653000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25653000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25653000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25653000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25653000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25653000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34387.399464 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9570609 # number of replacements system.cpu.dcache.tagsinuse 4087.729265 # Cycle average of tags in use @@ -392,40 +413,63 @@ system.cpu.dcache.total_refs 666885051 # To system.cpu.dcache.sampled_refs 9574705 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 69.650715 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 3484295000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.729265 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 499489564 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 167395365 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 666884929 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 666884929 # number of overall hits -system.cpu.dcache.ReadReq_misses 10445560 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5190682 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15636242 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15636242 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 184478558500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 128511717246 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 312990275746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 312990275746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 509935124 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 682521171 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 682521171 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.020484 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.022910 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.022910 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 17660.954367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24758.156490 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 20016.975674 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 20016.975674 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4087.729265 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 499489564 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 499489564 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167395365 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167395365 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 666884929 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666884929 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666884929 # number of overall hits +system.cpu.dcache.overall_hits::total 666884929 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10445560 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10445560 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5190682 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5190682 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 15636242 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15636242 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15636242 # number of overall misses +system.cpu.dcache.overall_misses::total 15636242 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 184478558500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 184478558500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128511717246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128511717246 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 312990275746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 312990275746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 312990275746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 312990275746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 509935124 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 509935124 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 682521171 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 682521171 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 682521171 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 682521171 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030076 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047619 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022910 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022910 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17660.954367 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24758.156490 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 266779202 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 225500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 90534 # number of cycles access was blocked @@ -434,33 +478,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.729428 system.cpu.dcache.avg_blocked_cycles::no_targets 16107.142857 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3128454 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2763491 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3298046 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6061537 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6061537 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7682069 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1892636 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9574705 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9574705 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 92052400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 45263240996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 137315641496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 137315641496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11982.761480 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.449667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 14341.501017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 14341.501017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3128454 # number of writebacks +system.cpu.dcache.writebacks::total 3128454 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2763491 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2763491 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3298046 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3298046 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6061537 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6061537 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6061537 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6061537 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7682069 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7682069 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1892636 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1892636 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9574705 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9574705 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9574705 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9574705 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 92052400500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 92052400500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45263240996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 45263240996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137315641496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137315641496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137315641496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 137315641496 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015065 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010966 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11982.761480 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23915.449667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2928111 # number of replacements system.cpu.l2cache.tagsinuse 26779.513847 # Cycle average of tags in use @@ -468,36 +521,75 @@ system.cpu.l2cache.total_refs 7850665 # To system.cpu.l2cache.sampled_refs 2955434 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.656349 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 102043879500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15980.141778 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10799.372069 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.487675 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.329571 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5654844 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3128454 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 980108 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6634952 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6634952 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2027970 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 912529 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2940499 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2940499 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 69622687500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 31651212500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 101273900000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 101273900000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7682814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3128454 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1892637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9575451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9575451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.263962 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.482147 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.307087 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.307087 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34331.221616 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.157951 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34441.059154 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34441.059154 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 10799.372069 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 11.094827 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15969.046951 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.329571 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000339 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.487337 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.817246 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5654817 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5654844 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3128454 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3128454 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 980108 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 980108 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 6634925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6634952 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24699000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 69597988500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 69622687500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31651212500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 31651212500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101249201000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101273900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24699000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101249201000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101273900000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 746 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7682068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7682814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3128454 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3128454 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1892637 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1892637 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 746 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9574705 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9575451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 746 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9574705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9575451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963807 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.263894 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.482147 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963807 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.307036 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963807 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.307036 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34351.877608 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34331.214290 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34685.157951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 56425000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 6634 # number of cycles access was blocked @@ -506,31 +598,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8505.426590 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1217630 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2027959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 912529 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2940488 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2940488 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 63243262500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28812389000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 92055651500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 92055651500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263960 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482147 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.307086 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.307086 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.671160 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31574.217367 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31306.249677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31306.249677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1217630 # number of writebacks +system.cpu.l2cache.writebacks::total 1217630 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 718 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2027241 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2027959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 912529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 912529 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 718 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2939770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2940488 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 718 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2939770 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2940488 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22382500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63220880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63243262500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28812389000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28812389000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22382500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92033269000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 92055651500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22382500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92033269000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 92055651500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.263893 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.482147 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31173.398329 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31185.675507 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31574.217367 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index bbede2479..6c19f0c57 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index e599bde0b..1bac004a3 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:37:28 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:28:58 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index e23300649..1bd7f49d7 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.861538 # Nu sim_ticks 861538205000 # Number of ticks simulated final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3027828 # Simulator instruction rate (inst/s) -host_tick_rate 1513916118 # Simulator tick rate (ticks/s) -host_mem_usage 210380 # Number of bytes of host memory used -host_seconds 569.08 # Real time elapsed on the host -sim_insts 1723073862 # Number of instructions simulated +host_inst_rate 3097767 # Simulator instruction rate (inst/s) +host_op_rate 3455787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1727895925 # Simulator tick rate (ticks/s) +host_mem_usage 212936 # Number of bytes of host memory used +host_seconds 498.61 # Real time elapsed on the host +sim_insts 1544563049 # Number of instructions simulated +sim_ops 1723073862 # Number of ops (including micro ops) simulated system.physmem.bytes_read 7759650064 # Number of bytes read from this memory system.physmem.bytes_inst_read 6178262392 # Number of instructions bytes read from this memory system.physmem.bytes_written 624158392 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 46 # Nu system.cpu.numCycles 1723076411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1723073862 # Number of instructions executed +system.cpu.committedInsts 1544563049 # Number of instructions committed +system.cpu.committedOps 1723073862 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330134 # number of times a function call or return occured diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 71abd898d..9736169e4 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 8198567b7..424d2bbd8 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:45:39 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:33:49 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 04e3122e6..e00ec713c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.431420 # Nu sim_ticks 2431419954000 # Number of ticks simulated final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1410228 # Simulator instruction rate (inst/s) -host_tick_rate 1996689457 # Simulator tick rate (ticks/s) -host_mem_usage 219344 # Number of bytes of host memory used -host_seconds 1217.73 # Real time elapsed on the host -sim_insts 1717270343 # Number of instructions simulated +host_inst_rate 1647360 # Simulator instruction rate (inst/s) +host_op_rate 1838469 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2603021191 # Simulator tick rate (ticks/s) +host_mem_usage 221840 # Number of bytes of host memory used +host_seconds 934.08 # Real time elapsed on the host +sim_insts 1538759609 # Number of instructions simulated +sim_ops 1717270343 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172766016 # Number of bytes read from this memory system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory system.physmem.bytes_written 75006720 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 46 # Nu system.cpu.numCycles 4862839908 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1717270343 # Number of instructions executed +system.cpu.committedInsts 1538759609 # Number of instructions committed +system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330134 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 1544564961 # To system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 514.872896 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.251403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1544564961 # number of ReadReq hits -system.cpu.icache.demand_hits 1544564961 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1544564961 # number of overall hits -system.cpu.icache.ReadReq_misses 638 # number of ReadReq misses -system.cpu.icache.demand_misses 638 # number of demand (read+write) misses -system.cpu.icache.overall_misses 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34804000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34804000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34804000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1544565599 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1544565599 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1544565599 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54551.724138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54551.724138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits +system.cpu.icache.overall_hits::total 1544564961 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses +system.cpu.icache.overall_misses::total 638 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 638 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 638 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 638 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32890000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32890000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32890000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32890000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32890000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32890000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 645855060 # To system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4083.719979 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997002 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 475158040 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 645854938 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 645854938 # number of overall hits -system.cpu.dcache.ReadReq_misses 7226087 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1889149 # number of WriteReq misses -system.cpu.dcache.demand_misses 9115236 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 177140908000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63824222000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 240965130000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 240965130000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 482384127 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 654970174 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 654970174 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 26435.424162 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 26435.424162 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 645854938 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 645854938 # number of overall hits +system.cpu.dcache.overall_hits::total 645854938 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses +system.cpu.dcache.overall_misses::total 9115236 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63824222000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63824222000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 240965130000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 240965130000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 240965130000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 240965130000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 482384127 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 482384127 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 654970174 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 654970174 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3061985 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7226087 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9115236 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9115236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 58156775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 213619422000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 213619422000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks +system.cpu.dcache.writebacks::total 3061985 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58156775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2687066 # number of replacements system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 7569171 # To system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15027.621217 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11106.896016 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.458607 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.338956 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5417164 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3061985 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 999241 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6416405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6416405 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1809561 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 889908 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2699469 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2699469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94097172000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46275216000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 140372388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 140372388000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7226725 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3061985 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9115874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9115874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250398 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.471063 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.296128 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.296128 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 11106.896016 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 11.181020 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15016.440197 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.338956 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.458265 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.797562 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5417142 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5417164 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3061985 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3061985 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 999241 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 999241 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 6416383 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6416405 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 6416383 # number of overall hits +system.cpu.l2cache.overall_hits::total 6416405 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1808945 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1809561 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 889908 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 889908 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2698853 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2699469 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2698853 # number of overall misses +system.cpu.l2cache.overall_misses::total 2699469 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94065140000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94097172000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46275216000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46275216000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 140372388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 140372388000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3061985 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3061985 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1171980 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1809561 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 889908 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2699469 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2699469 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72382440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35596320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 107978760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 107978760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250398 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.296128 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.296128 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks +system.cpu.l2cache.writebacks::total 1171980 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 889908 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2698853 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2699469 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2698853 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2699469 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72357800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72382440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index fe30d10a3..6cebafbf0 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index a5a0064e6..23e0a7dab 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 07:13:31 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:34:58 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 6725100b8..c4996594d 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007259500 # Number of ticks simulated final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2006575 # Simulator instruction rate (inst/s) -host_tick_rate 1218454030 # Simulator tick rate (ticks/s) -host_mem_usage 204704 # Number of bytes of host memory used -host_seconds 2335.75 # Real time elapsed on the host -sim_insts 4686862651 # Number of instructions simulated +host_inst_rate 1815306 # Simulator instruction rate (inst/s) +host_op_rate 2828411 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1717498350 # Simulator tick rate (ticks/s) +host_mem_usage 210188 # Number of bytes of host memory used +host_seconds 1657.07 # Real time elapsed on the host +sim_insts 3008081057 # Number of instructions simulated +sim_ops 4686862651 # Number of ops (including micro ops) simulated system.physmem.bytes_read 37129731755 # Number of bytes read from this memory system.physmem.bytes_inst_read 32105863408 # Number of instructions bytes read from this memory system.physmem.bytes_written 1544656790 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 46 # Nu system.cpu.numCycles 5692014520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 4686862651 # Number of instructions executed +system.cpu.committedInsts 3008081057 # Number of instructions committed +system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index e57f67518..a21cde2b2 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 5d5232885..0e700a575 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 07:30:19 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:48:34 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 94c5d24c6..aefb42b3b 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 5.923548 # Nu sim_ticks 5923548078000 # Number of ticks simulated final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1176749 # Simulator instruction rate (inst/s) -host_tick_rate 1487248019 # Simulator tick rate (ticks/s) -host_mem_usage 213688 # Number of bytes of host memory used -host_seconds 3982.89 # Real time elapsed on the host -sim_insts 4686862651 # Number of instructions simulated +host_inst_rate 1064786 # Simulator instruction rate (inst/s) +host_op_rate 1659033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2096788716 # Simulator tick rate (ticks/s) +host_mem_usage 219100 # Number of bytes of host memory used +host_seconds 2825.06 # Real time elapsed on the host +sim_insts 3008081057 # Number of instructions simulated +sim_ops 4686862651 # Number of ops (including micro ops) simulated system.physmem.bytes_read 173910080 # Number of bytes read from this memory system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory system.physmem.bytes_written 75176384 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 46 # Nu system.cpu.numCycles 11847096156 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 4686862651 # Number of instructions executed +system.cpu.committedInsts 3008081057 # Number of instructions committed +system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 4013232252 # To system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits -system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits -system.cpu.icache.overall_hits 4013232252 # number of overall hits -system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses -system.cpu.icache.demand_misses 675 # number of demand (read+write) misses -system.cpu.icache.overall_misses 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 555.713137 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.271344 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.271344 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits +system.cpu.icache.overall_hits::total 4013232252 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses +system.cpu.icache.overall_misses::total 675 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use @@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 1668600409 # To system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits -system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1668600409 # number of overall hits -system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses -system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4084.662246 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997232 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997232 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses +system.cpu.dcache.overall_misses::total 9112677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177808540000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177808540000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63869078000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63869078000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 241677618000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 241677618000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 241677618000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 241677618000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3053391 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks +system.cpu.dcache.writebacks::total 3053391 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156139990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 156139990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58199597000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58199597000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214339587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2706631 # number of replacements system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use @@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs 7537629 # To system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6396007 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2717345 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 11028.544571 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 19.163936 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15459.641562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.336564 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000585 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.471791 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.808940 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5396930 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5396930 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3053391 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3053391 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 999077 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 999077 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6396007 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6396007 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6396007 # number of overall hits +system.cpu.l2cache.overall_hits::total 6396007 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1825920 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1826595 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 890750 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 890750 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2716670 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2717345 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2716670 # number of overall misses +system.cpu.l2cache.overall_misses::total 2717345 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35100000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94947840000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94982940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46319000000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46319000000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35100000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 141266840000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 141301940000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35100000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 141266840000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 141301940000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3053391 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3053391 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.252798 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.298120 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.298120 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1174631 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks +system.cpu.l2cache.writebacks::total 1174631 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1825920 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1826595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 890750 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 890750 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2716670 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2717345 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2716670 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2717345 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 73036800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73063800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35630000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35630000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108666800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108693800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 64fd65cd8..1763cd3d7 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index ab1cbef0e..ddac6bec8 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:57:18 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:36:18 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index db43e1bd8..7525585e3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.041834 # Nu sim_ticks 41833966000 # Number of ticks simulated final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111295 # Simulator instruction rate (inst/s) -host_tick_rate 50660994 # Simulator tick rate (ticks/s) -host_mem_usage 211656 # Number of bytes of host memory used -host_seconds 825.76 # Real time elapsed on the host +host_inst_rate 151560 # Simulator instruction rate (inst/s) +host_op_rate 151560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68989742 # Simulator tick rate (ticks/s) +host_mem_usage 213560 # Number of bytes of host memory used +host_seconds 606.38 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 316032 # Number of bytes read from this memory system.physmem.bytes_inst_read 178816 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -68,9 +70,10 @@ system.cpu.comNops 7723346 # Nu system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed system.cpu.comInts 43665352 # Number of Integer instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed -system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads @@ -124,26 +127,39 @@ system.cpu.icache.total_refs 9979713 # To system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits -system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits -system.cpu.icache.overall_hits 9979713 # number of overall hits -system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses -system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits +system.cpu.icache.overall_hits::total 9979713 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses +system.cpu.icache.overall_misses::total 11486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9991199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9991199 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9991199 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2050 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2050 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2050 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use @@ -180,32 +199,49 @@ system.cpu.dcache.total_refs 26491206 # To system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26491206 # number of overall hits -system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 6095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491206 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491206 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491206 # number of overall hits +system.cpu.dcache.overall_hits::total 26491206 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 553 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 553 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5542 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5542 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6095 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6095 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6095 # number of overall misses +system.cpu.dcache.overall_misses::total 6095 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28393500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28393500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 303801000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 303801000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 332194500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 332194500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 332194500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 332194500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54817.935763 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,32 +250,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3872 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 116210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3794 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3794 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3872 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3872 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3872 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3872 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92997500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92997500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 116210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use @@ -247,36 +291,75 @@ system.cpu.l2cache.total_refs 6704 # To system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2171.415543 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.838059 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066266 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 6695 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6721 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 168327500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 258892500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 258892500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 9911 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 11659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 11659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.324488 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.423535 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.423535 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52428.614824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52428.614824 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 17.838059 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.375269 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.040274 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055553 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066811 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6642 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6695 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 6642 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6721 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6642 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 6721 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2794 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4938 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses +system.cpu.l2cache.overall_misses::total 4938 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146193000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22134500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 168327500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90565000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90565000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 146193000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112699500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 258892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 146193000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112699500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 258892500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 9911 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 11659 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 11659 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.296100 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296100 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -285,30 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 129053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 198397500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 198397500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.324488 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.423535 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.423535 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3216 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112072000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129053500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69344000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69344000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112072000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 198397500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112072000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86325500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 198397500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index a6f9e5430..10359186b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 9901dc40b..f5b2c31fd 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:08:28 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:45:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 55d9dc21f..221154573 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.029167 # Nu sim_ticks 29167093500 # Number of ticks simulated final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155660 # Simulator instruction rate (inst/s) -host_tick_rate 53933893 # Simulator tick rate (ticks/s) -host_mem_usage 212576 # Number of bytes of host memory used -host_seconds 540.79 # Real time elapsed on the host +host_inst_rate 198361 # Simulator instruction rate (inst/s) +host_op_rate 198361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68729352 # Simulator tick rate (ticks/s) +host_mem_usage 214912 # Number of bytes of host memory used +host_seconds 424.38 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated +sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read 332416 # Number of bytes read from this memory system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -271,6 +273,7 @@ system.cpu.iew.wb_rate 1.710877 # in system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted @@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle -system.cpu.commit.count 91903055 # Number of instructions committed +system.cpu.commit.committedInsts 91903055 # Number of instructions committed +system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed system.cpu.commit.loads 19996198 # Number of loads committed @@ -307,6 +311,7 @@ system.cpu.rob.rob_writes 271380444 # Th system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads @@ -324,26 +329,39 @@ system.cpu.icache.total_refs 18592194 # To system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses -system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits +system.cpu.icache.overall_hits::total 18592194 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses +system.cpu.icache.overall_misses::total 11853 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1225 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use @@ -380,38 +401,59 @@ system.cpu.dcache.total_refs 30399158 # To system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23906051 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23906051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 30399106 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 30399106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 30399106 # number of overall hits +system.cpu.dcache.overall_hits::total 30399106 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8986 # number of overall misses +system.cpu.dcache.overall_misses::total 8986 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28163500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289889000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318052500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318052500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 30408092 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 30408092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 30408092 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 30408092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000039 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018868 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000296 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -420,36 +462,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6741 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1731 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61655000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6317 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6317 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6741 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78124500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78124500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018868 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32041.828794 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35618.139804 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use @@ -457,36 +509,75 @@ system.cpu.l2cache.total_refs 7666 # To system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 25 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 382.154472 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000538 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.061050 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011662 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073251 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7599 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 56 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7599 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10628 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 12874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.285002 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.891262 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.285002 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.285002 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,30 +586,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # 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average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3488 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5194 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94144500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14345500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108490000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94144500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index c3b5c0104..452e0175b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout index 887ca3f4e..b6a6db444 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:10:21 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:46:35 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index af93195e1..defa21ce1 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4191883 # Simulator instruction rate (inst/s) -host_tick_rate 2095941744 # Simulator tick rate (ticks/s) -host_mem_usage 202544 # Number of bytes of host memory used -host_seconds 21.92 # Real time elapsed on the host +host_inst_rate 5286635 # Simulator instruction rate (inst/s) +host_op_rate 5286630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2643314521 # Simulator tick rate (ticks/s) +host_mem_usage 204308 # Number of bytes of host memory used +host_seconds 17.38 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 475949877 # Number of bytes read from this memory system.physmem.bytes_inst_read 367612356 # Number of instructions bytes read from this memory system.physmem.bytes_written 30920974 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 91903136 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses system.cpu.num_func_calls 2059216 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 2fe44f969..16b0989b3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 84097b1db..1373e7148 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:10:54 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:47:03 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index ba87aad33..244f3ca51 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.118740 # Nu sim_ticks 118740049000 # Number of ticks simulated final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2095418 # Simulator instruction rate (inst/s) -host_tick_rate 2707308980 # Simulator tick rate (ticks/s) -host_mem_usage 211256 # Number of bytes of host memory used -host_seconds 43.86 # Real time elapsed on the host +host_inst_rate 2598987 # Simulator instruction rate (inst/s) +host_op_rate 2598985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3357924345 # Simulator tick rate (ticks/s) +host_mem_usage 213168 # Number of bytes of host memory used +host_seconds 35.36 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 304960 # Number of bytes read from this memory system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 237480098 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses system.cpu.num_func_calls 2059216 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 91894580 # To system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits -system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses -system.cpu.icache.overall_misses 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1418.037996 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.692401 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.692401 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits +system.cpu.icache.overall_hits::total 91894580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses +system.cpu.icache.overall_misses::total 8510 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 229222000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 229222000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 229222000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 229222000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 229222000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 229222000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 26495078 # To system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1442.028823 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121170000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121170000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121170000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121170000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use @@ -198,36 +231,75 @@ system.cpu.l2cache.total_refs 5951 # To system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 5968 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 17.795183 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1704.999565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.253845 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052032 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.063295 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 5968 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,30 +308,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index ce56be1ef..eef0e971d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 442ecd78f..d10088405 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:20 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:37:09 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 83e315e2a..98dddaff0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.105851 # Nu sim_ticks 105850842000 # Number of ticks simulated final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46914 # Simulator instruction rate (inst/s) -host_tick_rate 26320721 # Simulator tick rate (ticks/s) -host_mem_usage 259812 # Number of bytes of host memory used -host_seconds 4021.58 # Real time elapsed on the host -sim_insts 188667627 # Number of instructions simulated +host_inst_rate 122767 # Simulator instruction rate (inst/s) +host_op_rate 134419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75414821 # Simulator tick rate (ticks/s) +host_mem_usage 227032 # Number of bytes of host memory used +host_seconds 1403.58 # Real time elapsed on the host +sim_insts 172314144 # Number of instructions simulated +sim_ops 188667627 # Number of ops (including micro ops) simulated system.physmem.bytes_read 239936 # Number of bytes read from this memory system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -280,7 +282,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188682015 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted @@ -301,7 +304,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle -system.cpu.commit.count 188682015 # Number of instructions committed +system.cpu.commit.committedInsts 172328532 # Number of instructions committed +system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 42498565 # Number of memory references committed system.cpu.commit.loads 29851708 # Number of loads committed @@ -316,12 +320,13 @@ system.cpu.rob.rob_reads 519029825 # Th system.cpu.rob.rob_writes 693007050 # The number of ROB writes system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667627 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667627 # Number of Instructions Simulated -system.cpu.cpi 1.122088 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.122088 # CPI: Total CPI of All Threads -system.cpu.ipc 0.891196 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.891196 # IPC: Total IPC of All Threads +system.cpu.committedInsts 172314144 # Number of Instructions Simulated +system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated +system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads +system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads system.cpu.int_regfile_writes 407368356 # number of integer regfile writes system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads @@ -334,26 +339,39 @@ system.cpu.icache.total_refs 40615441 # To system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1329.301324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.649073 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 40615441 # number of ReadReq hits -system.cpu.icache.demand_hits 40615441 # number of demand (read+write) hits -system.cpu.icache.overall_hits 40615441 # number of overall hits -system.cpu.icache.ReadReq_misses 4234 # number of ReadReq misses -system.cpu.icache.demand_misses 4234 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4234 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 101275500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 101275500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 40619675 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 40619675 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23919.579594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23919.579594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23919.579594 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits +system.cpu.icache.overall_hits::total 40615441 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses +system.cpu.icache.overall_misses::total 4234 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -362,27 +380,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3640 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3640 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3640 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74572500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74572500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74572500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20486.950549 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3640 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3640 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3640 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3640 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3640 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3640 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74572500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74572500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74572500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74572500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74572500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74572500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 53 # number of replacements system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use @@ -390,40 +411,63 @@ system.cpu.dcache.total_refs 48643693 # To system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1403.723956 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 36234545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356727 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27791 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24630 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 48591272 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 48591272 # number of overall hits -system.cpu.dcache.ReadReq_misses 1808 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7560 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9368 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9368 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59529000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 237156500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 296685500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 296685500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 36236353 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27793 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24630 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 48600640 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 48600640 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32925.331858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31369.907407 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31670.100342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31670.100342 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 36234545 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 36234545 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356727 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356727 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 27791 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 27791 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 24630 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24630 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 48591272 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 48591272 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 48591272 # number of overall hits +system.cpu.dcache.overall_hits::total 48591272 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7560 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7560 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9368 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9368 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9368 # number of overall misses +system.cpu.dcache.overall_misses::total 9368 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59529000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59529000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 237156500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 237156500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 63500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296685500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296685500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296685500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296685500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 36236353 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 36236353 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27793 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 27793 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 24630 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24630 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 48600640 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 48600640 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 48600640 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 48600640 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000050 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000193 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000193 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,33 +476,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6469 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7522 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7522 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 755 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1091 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1846 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1846 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24116500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38344000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62460500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.384106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1053 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1053 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7522 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7522 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7522 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7522 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 755 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1091 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1091 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1846 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1846 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1846 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1846 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24116500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24116500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38344000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 38344000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62460500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62460500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62460500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62460500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31942.384106 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35145.737855 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 1923.480613 # Cycle average of tags in use @@ -466,36 +519,75 @@ system.cpu.l2cache.total_refs 1714 # To system.cpu.l2cache.sampled_refs 2676 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.640508 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1919.476269 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 4.004344 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058578 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1714 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 18 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1723 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2681 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3763 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3763 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 91922000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37184000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129106000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129106000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.610011 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.685928 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.685928 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34286.460276 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.988909 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34309.327664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34309.327664 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 4.004344 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1392.392495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 527.083774 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.042492 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016085 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.058700 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1633 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 81 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1714 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1633 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 90 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1723 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1633 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 90 # number of overall hits +system.cpu.l2cache.overall_hits::total 1723 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2007 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 674 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2681 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1082 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1082 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2007 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3763 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2007 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses +system.cpu.l2cache.overall_misses::total 3763 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68771500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23150500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 91922000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37184000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 37184000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 68771500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 60334500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 129106000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 68771500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 60334500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 129106000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3640 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 755 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1091 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1091 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3640 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1846 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3640 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1846 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.551374 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892715 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991751 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.551374 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.951246 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.551374 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.951246 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34265.819631 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34347.922849 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34365.988909 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,31 +596,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2667 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3749 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3749 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 82895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116485000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606826 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.683376 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.683376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.739783 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2005 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 662 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2667 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2005 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1744 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3749 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2005 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1744 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3749 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62251500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20643500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82895000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54233500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 116485000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54233500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 116485000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876821 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 01def30a3..8e458b793 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index f2a9f0661..36b361cbc 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:50:48 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:37:27 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 079a70f11..5d6608220 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.103107 # Nu sim_ticks 103106771000 # Number of ticks simulated final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3006793 # Simulator instruction rate (inst/s) -host_tick_rate 1643182108 # Simulator tick rate (ticks/s) -host_mem_usage 213456 # Number of bytes of host memory used -host_seconds 62.75 # Real time elapsed on the host -sim_insts 188670900 # Number of instructions simulated +host_inst_rate 3118510 # Simulator instruction rate (inst/s) +host_op_rate 3414466 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1865971013 # Simulator tick rate (ticks/s) +host_mem_usage 216012 # Number of bytes of host memory used +host_seconds 55.26 # Real time elapsed on the host +sim_insts 172317417 # Number of instructions simulated +sim_ops 188670900 # Number of ops (including micro ops) simulated system.physmem.bytes_read 869973902 # Number of bytes read from this memory system.physmem.bytes_inst_read 759440240 # Number of instructions bytes read from this memory system.physmem.bytes_written 45252940 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 206213543 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 188670900 # Number of instructions executed +system.cpu.committedInsts 172317417 # Number of instructions committed +system.cpu.committedOps 188670900 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3504894 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 3f54c6512..f90360da8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index b21763742..322e5b2f2 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:52:01 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:38:33 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index d861ddab1..f86e3b057 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.232077 # Nu sim_ticks 232077154000 # Number of ticks simulated final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1497030 # Simulator instruction rate (inst/s) -host_tick_rate 1846187485 # Simulator tick rate (ticks/s) -host_mem_usage 222460 # Number of bytes of host memory used -host_seconds 125.71 # Real time elapsed on the host -sim_insts 188185929 # Number of instructions simulated +host_inst_rate 1867609 # Simulator instruction rate (inst/s) +host_op_rate 2045232 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2522247357 # Simulator tick rate (ticks/s) +host_mem_usage 224952 # Number of bytes of host memory used +host_seconds 92.01 # Real time elapsed on the host +sim_insts 171842491 # Number of instructions simulated +sim_ops 188185929 # Number of ops (including micro ops) simulated system.physmem.bytes_read 220992 # Number of bytes read from this memory system.physmem.bytes_inst_read 110656 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 464154308 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 188185929 # Number of instructions executed +system.cpu.committedInsts 171842491 # Number of instructions committed +system.cpu.committedOps 188185929 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3504894 # number of times a function call or return occured @@ -88,26 +91,39 @@ system.cpu.icache.total_refs 189857010 # To system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1147.981155 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.560538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 189857010 # number of ReadReq hits -system.cpu.icache.demand_hits 189857010 # number of demand (read+write) hits -system.cpu.icache.overall_hits 189857010 # number of overall hits -system.cpu.icache.ReadReq_misses 3051 # number of ReadReq misses -system.cpu.icache.demand_misses 3051 # number of demand (read+write) misses -system.cpu.icache.overall_misses 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 115332000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 115332000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 115332000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 189860061 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 189860061 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 189860061 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 37801.376598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 37801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1147.981155 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 189857010 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 189857010 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 189857010 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 189857010 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 189857010 # number of overall hits +system.cpu.icache.overall_hits::total 189857010 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses +system.cpu.icache.overall_misses::total 3051 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115332000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115332000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115332000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 189860061 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 189860061 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 189860061 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 189860061 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3051 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3051 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3051 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 106179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 106179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 106179000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use @@ -143,36 +157,57 @@ system.cpu.dcache.total_refs 42007359 # To system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1363.604315 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.332911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 29599358 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12363187 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 41962545 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 41962545 # number of overall hits -system.cpu.dcache.ReadReq_misses 689 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1100 # number of WriteReq misses -system.cpu.dcache.demand_misses 1789 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 36190000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 61264000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 97454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 97454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 29600047 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 41964334 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 41964334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54474.007826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54474.007826 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1363.604315 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332911 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332911 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 29599358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 29599358 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41962545 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41962545 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41962545 # number of overall hits +system.cpu.dcache.overall_hits::total 41962545 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses +system.cpu.dcache.overall_misses::total 1789 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36190000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36190000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61264000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61264000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 29600047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 29600047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 41964334 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41964334 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,30 +216,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 16 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 689 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1100 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1789 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 34123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 92087000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 92087000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use @@ -212,36 +249,75 @@ system.cpu.l2cache.total_refs 1379 # To system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.582102 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1672.609981 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.038048 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.051044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1379 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1387 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1387 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2361 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1092 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3453 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 122772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 56784000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 179556000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 179556000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 3740 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1100 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 4840 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 4840 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.631283 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.992727 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.713430 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 3.038048 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1169.027734 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 503.582248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits +system.cpu.l2cache.overall_hits::total 1387 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses +system.cpu.l2cache.overall_misses::total 3453 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 89648000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1092 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3453 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 43680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 138120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631283 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.713430 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 5551fc718..bf42eae33 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic +cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 5a1dc45d3..288eec929 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:25:10 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:01:49 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index fabf573dd..acb9c3a66 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.096723 # Nu sim_ticks 96722951500 # Number of ticks simulated final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3381365 # Simulator instruction rate (inst/s) -host_tick_rate 1690691780 # Simulator tick rate (ticks/s) -host_mem_usage 210080 # Number of bytes of host memory used -host_seconds 57.21 # Real time elapsed on the host -sim_insts 193444769 # Number of instructions simulated +host_inst_rate 4190258 # Simulator instruction rate (inst/s) +host_op_rate 4190262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2095142285 # Simulator tick rate (ticks/s) +host_mem_usage 207744 # Number of bytes of host memory used +host_seconds 46.17 # Real time elapsed on the host +sim_insts 193444531 # Number of instructions simulated +sim_ops 193444769 # Number of ops (including micro ops) simulated system.physmem.bytes_read 997245606 # Number of bytes read from this memory system.physmem.bytes_inst_read 773782192 # Number of instructions bytes read from this memory system.physmem.bytes_written 72065412 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 401 # Nu system.cpu.numCycles 193445904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.committedInsts 193444531 # Number of instructions committed +system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses system.cpu.num_func_calls 1957920 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index 2d0b36d34..4355111bc 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index e7f89f9a0..cb4fa4440 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:26:18 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:02:21 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 16bfeed42..fba3d7989 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.270577 # Nu sim_ticks 270576960000 # Number of ticks simulated final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1675606 # Simulator instruction rate (inst/s) -host_tick_rate 2343719954 # Simulator tick rate (ticks/s) -host_mem_usage 218792 # Number of bytes of host memory used -host_seconds 115.45 # Real time elapsed on the host -sim_insts 193444769 # Number of instructions simulated +host_inst_rate 2083715 # Simulator instruction rate (inst/s) +host_op_rate 2083717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2914556895 # Simulator tick rate (ticks/s) +host_mem_usage 216616 # Number of bytes of host memory used +host_seconds 92.84 # Real time elapsed on the host +sim_insts 193444531 # Number of instructions simulated +sim_ops 193444769 # Number of ops (including micro ops) simulated system.physmem.bytes_read 331072 # Number of bytes read from this memory system.physmem.bytes_inst_read 230208 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 401 # Nu system.cpu.numCycles 541153920 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.committedInsts 193444531 # Number of instructions committed +system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses system.cpu.num_func_calls 1957920 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 193433261 # To system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits -system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits -system.cpu.icache.overall_hits 193433261 # number of overall hits -system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses -system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses -system.cpu.icache.overall_misses 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1591.571713 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777135 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777135 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 193433261 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 193433261 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 193433261 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 193433261 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 193433261 # number of overall hits +system.cpu.icache.overall_hits::total 193433261 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses +system.cpu.icache.overall_misses::total 12288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 323106000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 323106000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 323106000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 193445549 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 193445549 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 193445549 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 193445549 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use @@ -101,38 +115,59 @@ system.cpu.dcache.total_refs 76732338 # To system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.302050 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits 76709933 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 76709933 # number of overall hits -system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.demand_misses 1575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 60312000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 56000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 88200000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 88200000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1237.197455 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.302050 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.302050 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 57734571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734571 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 76709933 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709933 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709933 # number of overall hits +system.cpu.dcache.overall_hits::total 76709933 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses +system.cpu.dcache.overall_misses::total 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27888000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27888000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60312000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 56000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 56000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 88200000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 76711508 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711508 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711508 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711508 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +176,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1077 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 57081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 53000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 83475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 2 # number of writebacks +system.cpu.dcache.writebacks::total 2 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use @@ -176,35 +215,70 @@ system.cpu.l2cache.total_refs 8691 # To system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.081736 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits -system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 8691 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5173 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 0.000454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2275.271466 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 403.055215 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits +system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits +system.cpu.l2cache.overall_hits::total 8691 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses +system.cpu.l2cache.overall_misses::total 5173 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -213,30 +287,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 9f72e3b54..82a282d96 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,12 +510,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 0b6a80ec2..99b3e7f21 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:02:46 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 2a68affc2..0aeabdea4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.096266 # Nu sim_ticks 96266258000 # Number of ticks simulated final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60515 # Simulator instruction rate (inst/s) -host_tick_rate 26316743 # Simulator tick rate (ticks/s) -host_mem_usage 262352 # Number of bytes of host memory used -host_seconds 3657.99 # Real time elapsed on the host -sim_insts 221363017 # Number of instructions simulated +host_inst_rate 89516 # Simulator instruction rate (inst/s) +host_op_rate 150037 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65247901 # Simulator tick rate (ticks/s) +host_mem_usage 229524 # Number of bytes of host memory used +host_seconds 1475.39 # Real time elapsed on the host +sim_insts 132071227 # Number of instructions simulated +sim_ops 221363017 # Number of ops (including micro ops) simulated system.physmem.bytes_read 339712 # Number of bytes read from this memory system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -235,7 +237,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions +system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted @@ -256,7 +259,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle -system.cpu.commit.count 221363017 # Number of instructions committed +system.cpu.commit.committedInsts 132071227 # Number of instructions committed +system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed system.cpu.commit.loads 56649590 # Number of loads committed @@ -271,12 +275,13 @@ system.cpu.rob.rob_reads 560089335 # Th system.cpu.rob.rob_writes 814800236 # The number of ROB writes system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 221363017 # Number of Instructions Simulated -system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.869759 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.869759 # CPI: Total CPI of All Threads -system.cpu.ipc 1.149744 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.149744 # IPC: Total IPC of All Threads +system.cpu.committedInsts 132071227 # Number of Instructions Simulated +system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated +system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads +system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 530367480 # number of integer regfile reads system.cpu.int_regfile_writes 288604591 # number of integer regfile writes system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads @@ -289,26 +294,39 @@ system.cpu.icache.total_refs 28751182 # To system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1597.649860 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.780102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28751182 # number of ReadReq hits -system.cpu.icache.demand_hits 28751182 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28751182 # number of overall hits -system.cpu.icache.ReadReq_misses 7479 # number of ReadReq misses -system.cpu.icache.demand_misses 7479 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 173725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 173725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28758661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28758661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23228.372777 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23228.372777 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23228.372777 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits +system.cpu.icache.overall_hits::total 28751182 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses +system.cpu.icache.overall_misses::total 7479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6360 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6360 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19690.801887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 56 # number of replacements system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use @@ -345,32 +366,49 @@ system.cpu.dcache.total_refs 72938173 # To system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1415.486536 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52423955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20513973 # number of WriteReq hits -system.cpu.dcache.demand_hits 72937928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 72937928 # number of overall hits -system.cpu.dcache.ReadReq_misses 771 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1757 # number of WriteReq misses -system.cpu.dcache.demand_misses 2528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 24605500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 66582500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 91188000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 52424726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 72940456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 72940456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31913.748379 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37895.560615 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 36071.202532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 36071.202532 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits +system.cpu.dcache.overall_hits::total 72937928 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses +system.cpu.dcache.overall_misses::total 2528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 344 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 346 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1755 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14039500 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 344 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 346 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 346 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 427 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1755 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1755 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2182 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2182 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 75284000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 75284000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 75284000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 75284000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.391101 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34897.150997 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2496.824684 # Cycle average of tags in use @@ -412,39 +458,80 @@ system.cpu.l2cache.total_refs 2842 # To system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.756858 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2494.880189 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.944495 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076138 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000059 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2840 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 13 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2848 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2848 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3753 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 193 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1555 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128533500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53066500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 181600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 181600000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 193 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8156 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8156 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.569240 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.650809 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.650809 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34248.201439 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34126.366559 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34212.509420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34212.509420 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 1.944495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2209.976363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 284.903826 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.067443 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.008695 # 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number of overall misses +system.cpu.l2cache.overall_misses::total 5308 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 115037500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13496000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 128533500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53066500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 53066500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 115037500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 66562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 181600000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 115037500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 66562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 181600000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6167 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 426 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 6593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 193 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 193 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1563 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1563 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6167 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1989 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8156 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6167 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1989 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8156 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.544511 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927230 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.544511 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980392 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.544511 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980392 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34257.742704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34167.088608 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34126.366559 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,34 +540,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3753 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5308 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116413500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5983000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48232500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 164646000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 164646000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.569240 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.650809 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.650809 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.784972 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31017.684887 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 395 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3753 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 193 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3358 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1950 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5308 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3358 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1950 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5308 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104175500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12238000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116413500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5983000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5983000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 4d9868de9..1355f971a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 3217ab200..d61c2b9aa 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 08:24:02 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:27:33 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 39967f660..0e7ef2e19 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.131393 # Nu sim_ticks 131393100000 # Number of ticks simulated final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1953897 # Simulator instruction rate (inst/s) -host_tick_rate 1159762651 # Simulator tick rate (ticks/s) -host_mem_usage 211876 # Number of bytes of host memory used -host_seconds 113.29 # Real time elapsed on the host -sim_insts 221363018 # Number of instructions simulated +host_inst_rate 1741959 # Simulator instruction rate (inst/s) +host_op_rate 2919677 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1733014386 # Simulator tick rate (ticks/s) +host_mem_usage 217356 # Number of bytes of host memory used +host_seconds 75.82 # Real time elapsed on the host +sim_insts 132071228 # Number of instructions simulated +sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1698379042 # Number of bytes read from this memory system.physmem.bytes_inst_read 1387955288 # Number of instructions bytes read from this memory system.physmem.bytes_written 99822189 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 262786201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.committedInsts 132071228 # Number of instructions committed +system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index d7a510398..62a1aa7b0 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index a3170a407..fff65e67f 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 08:26:06 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:28:59 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 1c9d2c1e6..6e3725588 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1263573 # Simulator instruction rate (inst/s) -host_tick_rate 1432520595 # Simulator tick rate (ticks/s) -host_mem_usage 220856 # Number of bytes of host memory used -host_seconds 175.19 # Real time elapsed on the host -sim_insts 221363018 # Number of instructions simulated +host_inst_rate 1043901 # Simulator instruction rate (inst/s) +host_op_rate 1749670 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1983612036 # Simulator tick rate (ticks/s) +host_mem_usage 226268 # Number of bytes of host memory used +host_seconds 126.52 # Real time elapsed on the host +sim_insts 132071228 # Number of instructions simulated +sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 303040 # Number of bytes read from this memory system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 501921262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.committedInsts 132071228 # Number of instructions committed +system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 173489718 # To system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits -system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits -system.cpu.icache.overall_hits 173489718 # number of overall hits -system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses -system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1455.289108 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.710590 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.710590 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173489718 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173489718 # number of overall hits +system.cpu.icache.overall_hits::total 173489718 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses +system.cpu.icache.overall_misses::total 4694 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185041500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185041500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185041500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185041500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173494412 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170928000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170928000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use @@ -101,32 +115,49 @@ system.cpu.dcache.total_refs 77195833 # To system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits -system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 77195833 # number of overall hits -system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1363.451495 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 56681681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681681 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195833 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195833 # number of overall hits +system.cpu.dcache.overall_hits::total 77195833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88242000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88242000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106262000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106262000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197738 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,30 +166,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 7 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use @@ -166,36 +199,75 @@ system.cpu.l2cache.total_refs 1861 # To system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1864 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 0.021756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.968899 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.177535 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits +system.cpu.l2cache.overall_hits::total 1864 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses +system.cpu.l2cache.overall_misses::total 4735 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 164335500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 147694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 246235500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 147694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 246235500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,30 +276,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |