diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:41:27 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:41:27 -0500 |
| commit | af2e83c7f13098b66ceb6ba69599f1959da44ea1 (patch) | |
| tree | a634f32d705cb32d614dcd43d819d8e3e26dd547 /tests/long/se | |
| parent | 22b60c57e697289baa205f11b164f356363c2bee (diff) | |
| download | gem5-af2e83c7f13098b66ceb6ba69599f1959da44ea1.tar.xz | |
x86, regressions: updates stats
This is due to op class, function call, walker patches.
Diffstat (limited to 'tests/long/se')
14 files changed, 2532 insertions, 2549 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index a7b0854c3..b2e32248a 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,72 +1,72 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.607388 # Number of seconds simulated -sim_ticks 607388314000 # Number of ticks simulated -final_tick 607388314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.602332 # Number of seconds simulated +sim_ticks 602332345500 # Number of ticks simulated +final_tick 602332345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39851 # Simulator instruction rate (inst/s) -host_op_rate 73427 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27504625 # Simulator tick rate (ticks/s) -host_mem_usage 294932 # Number of bytes of host memory used -host_seconds 22083.13 # Real time elapsed on the host +host_inst_rate 59375 # Simulator instruction rate (inst/s) +host_op_rate 109402 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40639301 # Simulator tick rate (ticks/s) +host_mem_usage 298404 # Number of bytes of host memory used +host_seconds 14821.42 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693120 # Number of bytes read from this memory -system.physmem.bytes_read::total 1751040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory -system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26455 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2787541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2882900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 266900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 266900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 266900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2787541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3149800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27361 # Total number of read requests seen -system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29894 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1751040 # Total number of bytes read from memory -system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1751040 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 57280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory +system.physmem.bytes_read::total 1750464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 57280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162240 # Number of bytes written to this memory +system.physmem.bytes_written::total 162240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27351 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2535 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2535 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 95097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2811046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2906143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 269353 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 269353 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 269353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2811046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3175496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27351 # Total number of read requests seen +system.physmem.writeReqs 2535 # Total number of write requests seen +system.physmem.cpureqs 29886 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1750464 # Total number of bytes read from memory +system.physmem.bytesWritten 162240 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1750464 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162240 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1742 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1741 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1707 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1659 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1717 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1751 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1735 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 1703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1742 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 161 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 155 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 156 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 158 # Track writes on a per bank basis @@ -74,28 +74,28 @@ system.physmem.perBankWrReqs::11 159 # Tr system.physmem.perBankWrReqs::12 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 160 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 607388300000 # Total gap between requests +system.physmem.totGap 602332206500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27361 # Categorize read packet sizes +system.physmem.readPktSize::6 27351 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2533 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 26894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2535 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 26932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -127,8 +127,8 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see @@ -156,265 +156,265 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 89920500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 894824250 # Sum of mem lat for all requests -system.physmem.totBusLat 136805000 # Total cycles spent in databus access -system.physmem.totBankLat 668098750 # Total cycles spent in bank access -system.physmem.avgQLat 3286.45 # Average queueing delay per request -system.physmem.avgBankLat 24417.92 # Average bank access latency per request +system.physmem.totQLat 88037750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 893262750 # Sum of mem lat for all requests +system.physmem.totBusLat 136755000 # Total cycles spent in databus access +system.physmem.totBankLat 668470000 # Total cycles spent in bank access +system.physmem.avgQLat 3218.81 # Average queueing delay per request +system.physmem.avgBankLat 24440.42 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32704.37 # Average memory access latency -system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 32659.24 # Average memory access latency +system.physmem.avgRdBW 2.91 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.91 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.62 # Average write queue length over time -system.physmem.readRowHits 16432 # Number of row buffer hits during reads -system.physmem.writeRowHits 1027 # Number of row buffer hits during writes -system.physmem.readRowHitRate 60.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.54 # Row buffer hit rate for writes -system.physmem.avgGap 20318067.17 # Average gap between requests -system.cpu.branchPred.lookups 158363276 # Number of BP lookups -system.cpu.branchPred.condPredicted 158363276 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26388177 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 84556073 # Number of BTB lookups -system.cpu.branchPred.BTBHits 84327975 # Number of BTB hits +system.physmem.avgWrQLen 8.01 # Average write queue length over time +system.physmem.readRowHits 16404 # Number of row buffer hits during reads +system.physmem.writeRowHits 1020 # Number of row buffer hits during writes +system.physmem.readRowHitRate 59.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.24 # Row buffer hit rate for writes +system.physmem.avgGap 20154326.66 # Average gap between requests +system.cpu.branchPred.lookups 155894666 # Number of BP lookups +system.cpu.branchPred.condPredicted 155894666 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25699129 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80742532 # Number of BTB lookups +system.cpu.branchPred.BTBHits 80542859 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.730241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.752704 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 2586842 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5513 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1214776629 # number of cpu cycles simulated +system.cpu.numCycles 1204664695 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 179085869 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1458535582 # Number of instructions fetch has processed -system.cpu.fetch.Branches 158363276 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84327975 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 399051382 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88177914 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574644515 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 188128638 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12060508 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214415274 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.059853 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.253551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175314236 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1434822441 # Number of instructions fetch has processed +system.cpu.fetch.Branches 155894666 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83129701 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 393116244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83893731 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 577823849 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 123 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 791 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 184597714 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11658023 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1204295068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.043367 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.243240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 822580385 67.73% 67.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26905566 2.22% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13181581 1.09% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20540967 1.69% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26638083 2.19% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18230799 1.50% 76.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31362370 2.58% 79.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39059510 3.22% 82.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215916013 17.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 818096949 67.93% 67.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26918487 2.24% 70.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 12895052 1.07% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20223867 1.68% 72.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26382325 2.19% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18061341 1.50% 76.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31920988 2.65% 79.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38294164 3.18% 82.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 211501895 17.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214415274 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130364 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.200662 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288243803 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497890873 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274138871 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92508603 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 61633124 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2344113948 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 61633124 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336916939 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124193279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2662 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 304031533 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387637737 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2248223321 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 352 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242707605 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120173474 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2618640021 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5724414358 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5724407502 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6856 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1204295068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129409 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.191055 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 284492311 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 500325603 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 268669661 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92767668 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 58039825 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2310318754 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 58039825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 333414311 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124348906 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3625 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 298566996 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 389921405 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2218156227 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 243059098 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 121762189 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2583430749 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5648758417 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5648752173 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6244 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 731744761 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 86 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731270344 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 531930252 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219281722 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 342004102 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144706308 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1994081706 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1783937479 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 271890 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 372188972 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 760599366 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 219 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214415274 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.468968 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.421626 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 696535489 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 103 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 737453259 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 525280959 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 216617119 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 339037703 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144743699 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1968663502 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 332 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1774132594 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 144752 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 346851970 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 707722705 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1204295068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.473171 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.418728 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360308657 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364274837 30.00% 59.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234367873 19.30% 78.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141282709 11.63% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60755557 5.00% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39735013 3.27% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11052402 0.91% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2038744 0.17% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 599482 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 354010440 29.40% 29.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 362491598 30.10% 59.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234089313 19.44% 78.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 140647652 11.68% 90.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60236623 5.00% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39446291 3.28% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10873538 0.90% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1896665 0.16% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 602948 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214415274 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1204295068 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 457362 15.66% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2260297 77.38% 93.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 203472 6.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 400252 14.21% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2198563 78.06% 92.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 217598 7.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812177 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065743062 59.74% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478833230 26.84% 89.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192549010 10.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812295 2.64% 2.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1058825283 59.68% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 18980 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 398 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 476287231 26.85% 89.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192188407 10.83% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1783937479 # Type of FU issued -system.cpu.iq.rate 1.468531 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2921131 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001637 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4785482838 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2366447244 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1724674774 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 415 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2104 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740046229 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 204 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210002024 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1774132594 # Type of FU issued +system.cpu.iq.rate 1.472719 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2816413 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001587 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4755521042 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2315690389 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1716753140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 379 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1840 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1730136533 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 179 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210301951 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 112888130 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 39196 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 182689 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31095664 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 106238837 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 40588 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 180694 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 28431061 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2329 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 61633124 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1215598 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 109803 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1994081974 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63261504 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 531930252 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219281722 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 53150 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2875 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 182689 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2045744 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24472235 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26517979 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766179614 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474605200 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17757865 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 58039825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1222123 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 102210 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1968663834 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63066910 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 525280959 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 216617119 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49147 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2813 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 180694 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1387767 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24439207 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25826974 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1757694663 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 472697091 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16437931 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666327456 # number of memory reference insts executed -system.cpu.iew.exec_branches 110355440 # Number of branches executed -system.cpu.iew.exec_stores 191722256 # Number of stores executed -system.cpu.iew.exec_rate 1.453913 # Inst execution rate -system.cpu.iew.wb_sent 1725787981 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1724674882 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267085899 # num instructions producing a value -system.cpu.iew.wb_consumers 1828860280 # num instructions consuming a value +system.cpu.iew.exec_refs 664152329 # number of memory reference insts executed +system.cpu.iew.exec_branches 110147604 # Number of branches executed +system.cpu.iew.exec_stores 191455238 # Number of stores executed +system.cpu.iew.exec_rate 1.459074 # Inst execution rate +system.cpu.iew.wb_sent 1717478326 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1716753232 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1259860051 # num instructions producing a value +system.cpu.iew.wb_consumers 1819503625 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.419747 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692828 # average fanout of values written-back +system.cpu.iew.wb_rate 1.425088 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692420 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 372589426 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 347171319 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26388224 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1152782150 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.406592 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.830218 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25699242 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1146255243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.414601 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.834752 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 418160632 36.27% 36.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 415035897 36.00% 72.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86967576 7.54% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122159323 10.60% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24161943 2.10% 92.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25351733 2.20% 94.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16436685 1.43% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12048526 1.05% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32459835 2.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 413178457 36.05% 36.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 412793718 36.01% 72.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87651437 7.65% 79.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122127525 10.65% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23936453 2.09% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25493357 2.22% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16343741 1.43% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12104723 1.06% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32625832 2.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1152782150 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1146255243 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -424,196 +424,196 @@ system.cpu.commit.membars 0 # Nu system.cpu.commit.branches 107161574 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32459835 # number cycles where commit BW limit reached +system.cpu.commit.function_calls 1061692 # Number of function calls committed. +system.cpu.commit.bw_lim_events 32625832 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3114405668 # The number of ROB reads -system.cpu.rob.rob_writes 4049835519 # The number of ROB writes -system.cpu.timesIdled 58880 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 361355 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3082294657 # The number of ROB reads +system.cpu.rob.rob_writes 3995391584 # The number of ROB writes +system.cpu.timesIdled 60284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 369627 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.380388 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.380388 # CPI: Total CPI of All Threads -system.cpu.ipc 0.724434 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.724434 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3542838094 # number of integer regfile reads -system.cpu.int_regfile_writes 1974489722 # number of integer regfile writes -system.cpu.fp_regfile_reads 108 # number of floating regfile reads -system.cpu.misc_regfile_reads 910800153 # number of misc regfile reads +system.cpu.cpi 1.368898 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.368898 # CPI: Total CPI of All Threads +system.cpu.ipc 0.730515 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.730515 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3534938952 # number of integer regfile reads +system.cpu.int_regfile_writes 1966276795 # number of integer regfile writes +system.cpu.fp_regfile_reads 92 # number of floating regfile reads +system.cpu.misc_regfile_reads 906122047 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 816.521748 # Cycle average of tags in use -system.cpu.icache.total_refs 188127242 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 922 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 204042.561822 # Average number of references to valid blocks. +system.cpu.icache.replacements 34 # number of replacements +system.cpu.icache.tagsinuse 799.517991 # Cycle average of tags in use +system.cpu.icache.total_refs 184596362 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 200866.552775 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 816.521748 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.398692 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.398692 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 188127247 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 188127247 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 188127247 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 188127247 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 188127247 # number of overall hits -system.cpu.icache.overall_hits::total 188127247 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1391 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1391 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1391 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1391 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1391 # number of overall misses -system.cpu.icache.overall_misses::total 1391 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66285000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66285000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66285000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66285000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66285000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66285000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 188128638 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 188128638 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 188128638 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 188128638 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 188128638 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 188128638 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 799.517991 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.390390 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.390390 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 184596362 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 184596362 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 184596362 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 184596362 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 184596362 # number of overall hits +system.cpu.icache.overall_hits::total 184596362 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1352 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1352 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1352 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1352 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1352 # number of overall misses +system.cpu.icache.overall_misses::total 1352 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65001000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65001000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65001000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65001000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65001000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65001000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 184597714 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 184597714 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 184597714 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 184597714 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 184597714 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 184597714 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47652.767793 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47652.767793 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47652.767793 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47652.767793 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47652.767793 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47652.767793 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 175 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48077.662722 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48077.662722 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48077.662722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48077.662722 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 463 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 463 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 463 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 463 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 463 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 463 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48200500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 48200500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48200500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 48200500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48200500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 48200500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 430 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 430 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 430 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 430 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 922 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 922 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 922 # 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mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51940.193966 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51940.193966 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51940.193966 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51940.193966 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51940.193966 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51940.193966 # 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average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 27351 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35533995 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273547521 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 309081516 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 859327626 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 859327626 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35533995 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1132875147 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1168409142 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35533995 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1132875147 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1168409142 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.973885 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022344 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088907 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088907 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.973885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058761 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060625 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.973885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058761 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39702.787709 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60041.159131 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56701.800771 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39238.704384 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39238.704384 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39702.787709 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42821.104740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42719.064824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39702.787709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42821.104740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42719.064824 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 446101 # number of replacements -system.cpu.dcache.tagsinuse 4092.714287 # Cycle average of tags in use -system.cpu.dcache.total_refs 452328275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 450197 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1004.734094 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4092.714287 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264388646 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264388646 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939623 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939623 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452328269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452328269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452328269 # number of overall hits -system.cpu.dcache.overall_hits::total 452328269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 211237 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 211237 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246435 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246435 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 457672 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 457672 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 457672 # number of overall misses -system.cpu.dcache.overall_misses::total 457672 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022054000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3022054000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4117738500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4117738500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7139792500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7139792500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7139792500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7139792500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264599883 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264599883 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 446134 # number of replacements +system.cpu.dcache.tagsinuse 4092.678697 # Cycle average of tags in use +system.cpu.dcache.total_refs 450120039 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 450230 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 999.755767 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 862286000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.678697 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999189 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999189 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 262180372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 262180372 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939664 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939664 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 450120036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 450120036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 450120036 # number of overall hits +system.cpu.dcache.overall_hits::total 450120036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211406 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211406 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246394 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246394 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457800 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457800 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457800 # number of overall misses +system.cpu.dcache.overall_misses::total 457800 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3024053500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3024053500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115325499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4115325499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7139378999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7139378999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7139378999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7139378999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 262391778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 262391778 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452785941 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452785941 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452785941 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452785941 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001011 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001011 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.461463 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.461463 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16709.227585 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16709.227585 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15600.238817 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15600.238817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15600.238817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15600.238817 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 450577836 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 450577836 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 450577836 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 450577836 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001016 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001016 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001016 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001016 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14304.482843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14304.482843 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16702.214741 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16702.214741 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15594.973785 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15594.973785 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.023256 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.953488 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 429059 # number of writebacks -system.cpu.dcache.writebacks::total 429059 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7389 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7389 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 79 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 79 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7468 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7468 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7468 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7468 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203848 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203848 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246356 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246356 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450204 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450204 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450204 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450204 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2529010500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2529010500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3624235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3624235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6153246000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6153246000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6153246000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6153246000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 429005 # number of writebacks +system.cpu.dcache.writebacks::total 429005 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7496 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7496 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 71 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 71 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7567 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7567 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7567 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7567 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203910 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203910 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246323 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450233 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450233 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450233 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450233 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2529393000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2529393000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3622096999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3622096999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6151489999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6151489999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6151489999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6151489999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000777 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12406.354244 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12406.354244 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14711.375002 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14711.375002 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13667.683983 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13667.683983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13667.683983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13667.683983 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000999 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000999 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12404.457849 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12404.457849 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14704.664197 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14704.664197 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index da1003d0f..8d09ee016 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu sim_ticks 963992672000 # Number of ticks simulated final_tick 963992672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 595979 # Simulator instruction rate (inst/s) -host_op_rate 1098124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 652844357 # Simulator tick rate (ticks/s) -host_mem_usage 283988 # Number of bytes of host memory used -host_seconds 1476.60 # Real time elapsed on the host +host_inst_rate 988845 # Simulator instruction rate (inst/s) +host_op_rate 1822001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1083195788 # Simulator tick rate (ticks/s) +host_mem_usage 286888 # Number of bytes of host memory used +host_seconds 889.95 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory @@ -41,7 +41,7 @@ system.cpu.committedInsts 880025278 # Nu system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 2123381 # number of times a function call or return occured system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls system.cpu.num_int_insts 1621354440 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 2279afb65..441f669b6 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.800193 # Nu sim_ticks 1800193398000 # Number of ticks simulated final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 392596 # Simulator instruction rate (inst/s) -host_op_rate 723379 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 803099848 # Simulator tick rate (ticks/s) -host_mem_usage 292568 # Number of bytes of host memory used -host_seconds 2241.56 # Real time elapsed on the host +host_inst_rate 510604 # Simulator instruction rate (inst/s) +host_op_rate 940816 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1044499940 # Simulator tick rate (ticks/s) +host_mem_usage 295340 # Number of bytes of host memory used +host_seconds 1723.50 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -42,7 +42,7 @@ system.cpu.committedInsts 880025278 # Nu system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 2123381 # number of times a function call or return occured system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls system.cpu.num_int_insts 1621354440 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 2c4cdb31e..5ca506819 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.066016 # Number of seconds simulated -sim_ticks 66015916000 # Number of ticks simulated -final_tick 66015916000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064955 # Number of seconds simulated +sim_ticks 64955437500 # Number of ticks simulated +final_tick 64955437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35889 # Simulator instruction rate (inst/s) -host_op_rate 63194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14996247 # Simulator tick rate (ticks/s) -host_mem_usage 431068 # Number of bytes of host memory used -host_seconds 4402.16 # Real time elapsed on the host +host_inst_rate 70718 # Simulator instruction rate (inst/s) +host_op_rate 124523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29075113 # Simulator tick rate (ticks/s) +host_mem_usage 434544 # Number of bytes of host memory used +host_seconds 2234.06 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882688 # Number of bytes read from this memory -system.physmem.bytes_read::total 1947520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory -system.physmem.bytes_written::total 10816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29417 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory -system.physmem.num_writes::total 169 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 982066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28518698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29500765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 982066 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 982066 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163839 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163839 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 982066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28518698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29664604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30432 # Total number of read requests seen -system.physmem.writeReqs 169 # Total number of write requests seen -system.physmem.cpureqs 30602 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1947520 # Total number of bytes read from memory -system.physmem.bytesWritten 10816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1947520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1906 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis +system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory +system.physmem.bytes_written::total 10432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30415 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 986276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28981346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29967622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 986276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 986276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 160602 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 160602 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 160602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 986276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28981346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30128224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30415 # Total number of read requests seen +system.physmem.writeReqs 163 # Total number of write requests seen +system.physmem.cpureqs 30578 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1946560 # Total number of bytes read from memory +system.physmem.bytesWritten 10432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946560 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 40 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1903 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1899 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1949 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1933 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1894 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1799 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7 # Track writes on a per bank basis +system.physmem.perBankRdReqs::12 1848 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1827 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 11 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 14 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 66015903000 # Total gap between requests +system.physmem.totGap 64955401000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30432 # Categorize read packet sizes +system.physmem.readPktSize::6 30415 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 169 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -126,12 +126,12 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see @@ -156,266 +156,266 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 14883000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 612849250 # Sum of mem lat for all requests +system.physmem.totQLat 11278750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 610070000 # Sum of mem lat for all requests system.physmem.totBusLat 151875000 # Total cycles spent in databus access -system.physmem.totBankLat 446091250 # Total cycles spent in bank access -system.physmem.avgQLat 489.98 # Average queueing delay per request -system.physmem.avgBankLat 14686.13 # Average bank access latency per request +system.physmem.totBankLat 446916250 # Total cycles spent in bank access +system.physmem.avgQLat 371.32 # Average queueing delay per request +system.physmem.avgBankLat 14713.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20176.11 # Average memory access latency -system.physmem.avgRdBW 29.50 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 20084.61 # Average memory access latency +system.physmem.avgRdBW 29.97 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.50 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.97 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.busUtil 0.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 12.99 # Average write queue length over time -system.physmem.readRowHits 29112 # Number of row buffer hits during reads -system.physmem.writeRowHits 92 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.44 # Row buffer hit rate for writes -system.physmem.avgGap 2157311.95 # Average gap between requests -system.cpu.branchPred.lookups 34543649 # Number of BP lookups -system.cpu.branchPred.condPredicted 34543649 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 911313 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24748799 # Number of BTB lookups -system.cpu.branchPred.BTBHits 24648647 # Number of BTB hits +system.physmem.avgWrQLen 9.38 # Average write queue length over time +system.physmem.readRowHits 29086 # Number of row buffer hits during reads +system.physmem.writeRowHits 90 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 55.21 # Row buffer hit rate for writes +system.physmem.avgGap 2124252.76 # Average gap between requests +system.cpu.branchPred.lookups 33861369 # Number of BP lookups +system.cpu.branchPred.condPredicted 33861369 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 775033 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19294803 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19205281 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.595326 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.536031 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5016068 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5449 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 132031833 # number of cpu cycles simulated +system.cpu.numCycles 129910880 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26608466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 185598145 # Number of instructions fetch has processed -system.cpu.fetch.Branches 34543649 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24648647 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56505869 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6118180 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43668483 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 168 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25960165 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 191907 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131953761 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.484443 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.326412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26135643 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182272269 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33861369 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24221349 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55463274 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5355481 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43685508 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 275 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25577909 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166501 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 129829944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.475075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.321063 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77999092 59.11% 59.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1996445 1.51% 60.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2954879 2.24% 62.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3924320 2.97% 65.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7795201 5.91% 71.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757326 3.61% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2733781 2.07% 77.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1559430 1.18% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28233287 21.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76844002 59.19% 59.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1961117 1.51% 60.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2942078 2.27% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3835155 2.95% 65.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7767567 5.98% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757667 3.66% 75.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2666355 2.05% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316617 1.01% 78.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27739386 21.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131953761 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261631 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.405708 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37450717 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35919295 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44755686 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8657316 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5170747 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 324590135 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 5170747 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43008680 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8572089 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9131 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 47592423 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27600691 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 320189266 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 52468 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25750177 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 322200191 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 849206572 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 849204881 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1691 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 129829944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260651 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.403056 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36820018 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35912600 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43886713 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8665410 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4545203 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318850210 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4545203 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42299380 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8565943 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6540 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46769687 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27643191 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 315014600 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37506 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25780031 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 461 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 317193496 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836529852 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 836528510 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1342 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42987444 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 470 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 464 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62325140 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 102538299 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 35256894 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39591249 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6019659 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 315840251 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1684 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 302185420 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114738 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 37013163 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 54220323 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1239 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131953761 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700741 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37980749 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 473 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 470 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62475342 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101554999 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34779465 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39658435 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5856370 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311474506 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1648 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300268759 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90582 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32704656 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46105854 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1203 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 129829944 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.312785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.693578 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24578254 18.63% 18.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23242336 17.61% 36.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25887812 19.62% 55.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25783281 19.54% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18948095 14.36% 89.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8310182 6.30% 96.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4120126 3.12% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 915829 0.69% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 167846 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23157142 17.84% 17.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23146978 17.83% 35.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25463277 19.61% 55.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25807307 19.88% 75.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18888431 14.55% 89.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8277018 6.38% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3970528 3.06% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 942780 0.73% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 176483 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131953761 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 129829944 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 38358 1.96% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1827997 93.47% 95.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 89360 4.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31372 1.52% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1915002 93.02% 94.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 112311 5.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 171162971 56.64% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97754962 32.35% 89.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33236179 11.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169830588 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11175 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97304104 32.41% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33091251 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 302185420 # Type of FU issued -system.cpu.iq.rate 2.288732 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1955715 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006472 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738394566 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 352887317 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 299540345 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 488 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 781 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 304109629 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54010503 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300268759 # Type of FU issued +system.cpu.iq.rate 2.311344 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2058685 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 732516269 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344212556 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298017233 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 646 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 145 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302295951 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 216 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54147980 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11758914 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26738 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33947 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3817142 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10775614 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30228 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33222 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3339713 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8519 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3234 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8606 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5170747 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1767696 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159609 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 315841935 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 195500 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 102538299 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 35256894 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 4545203 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1761176 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 160180 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311476154 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 195955 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101554999 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34779465 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3164 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73504 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33947 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 522441 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446022 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 968463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 300565656 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97285754 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1619764 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3219 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73682 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33222 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393210 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 428039 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821249 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298868187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891593 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1400572 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 130302195 # number of memory reference insts executed -system.cpu.iew.exec_branches 30889184 # Number of branches executed -system.cpu.iew.exec_stores 33016441 # Number of stores executed -system.cpu.iew.exec_rate 2.276464 # Inst execution rate -system.cpu.iew.wb_sent 299955561 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 299540489 # cumulative count of insts written-back -system.cpu.iew.wb_producers 219513821 # num instructions producing a value -system.cpu.iew.wb_consumers 298021184 # num instructions consuming a value +system.cpu.iew.exec_refs 129818447 # number of memory reference insts executed +system.cpu.iew.exec_branches 30819793 # Number of branches executed +system.cpu.iew.exec_stores 32926854 # Number of stores executed +system.cpu.iew.exec_rate 2.300563 # Inst execution rate +system.cpu.iew.wb_sent 298386144 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298017378 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218312526 # num instructions producing a value +system.cpu.iew.wb_consumers 296857185 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.268699 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736571 # average fanout of values written-back +system.cpu.iew.wb_rate 2.294014 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735413 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 37662479 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33296720 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 911334 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126783014 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.194241 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965349 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 775062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125284741 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.220482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.978635 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58216104 45.92% 45.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19275036 15.20% 61.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11824840 9.33% 70.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9597612 7.57% 78.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1736989 1.37% 79.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2070795 1.63% 81.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1302129 1.03% 82.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 715865 0.56% 82.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22043644 17.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57056182 45.54% 45.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19092863 15.24% 60.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11627505 9.28% 70.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9458661 7.55% 77.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1851635 1.48% 79.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2083324 1.66% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1287468 1.03% 81.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 696184 0.56% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22130919 17.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126783014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125284741 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -425,199 +425,193 @@ system.cpu.commit.membars 0 # Nu system.cpu.commit.branches 29309705 # Number of branches committed system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22043644 # number cycles where commit BW limit reached +system.cpu.commit.function_calls 4237596 # Number of function calls committed. +system.cpu.commit.bw_lim_events 22130919 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 420594313 # The number of ROB reads -system.cpu.rob.rob_writes 636885752 # The number of ROB writes -system.cpu.timesIdled 13744 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78072 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 414643006 # The number of ROB reads +system.cpu.rob.rob_writes 627527392 # The number of ROB writes +system.cpu.timesIdled 13814 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80936 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.835705 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835705 # CPI: Total CPI of All Threads -system.cpu.ipc 1.196594 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.196594 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 592843050 # number of integer regfile reads -system.cpu.int_regfile_writes 300182545 # number of integer regfile writes +system.cpu.cpi 0.822280 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.822280 # CPI: Total CPI of All Threads +system.cpu.ipc 1.216130 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.216130 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 590791400 # number of integer regfile reads +system.cpu.int_regfile_writes 298595306 # number of integer regfile writes system.cpu.fp_regfile_reads 134 # number of floating regfile reads -system.cpu.fp_regfile_writes 63 # number of floating regfile writes -system.cpu.misc_regfile_reads 192703630 # number of misc regfile reads +system.cpu.fp_regfile_writes 70 # number of floating regfile writes +system.cpu.misc_regfile_reads 191828831 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 61 # number of replacements -system.cpu.icache.tagsinuse 834.489266 # Cycle average of tags in use -system.cpu.icache.total_refs 25958820 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1031 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25178.292919 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 820.655975 # Cycle average of tags in use +system.cpu.icache.total_refs 25576619 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1018 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25124.380157 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 834.489266 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.407465 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.407465 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25958820 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25958820 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25958820 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25958820 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25958820 # number of overall hits -system.cpu.icache.overall_hits::total 25958820 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1345 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1345 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1345 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1345 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1345 # number of overall misses -system.cpu.icache.overall_misses::total 1345 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65418500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65418500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65418500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65418500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65418500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65418500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25960165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25960165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25960165 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25960165 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25960165 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25960165 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48638.289963 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48638.289963 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48638.289963 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48638.289963 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48638.289963 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48638.289963 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 820.655975 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352318 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983301 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014165 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014639 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983301 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014165 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014639 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51247.752248 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51452.898551 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51307.773852 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42013.706897 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42013.706897 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51247.752248 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42146.562861 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42446.095676 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51247.752248 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42146.562861 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42446.095676 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -626,168 +620,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37747309 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 880813316 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 918560625 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37747309 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 880813316 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 918560625 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982541 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000211 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000718 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29940.287433 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30184.037362 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 163 # number of writebacks +system.cpu.l2cache.writebacks::total 163 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1001 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 414 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1415 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1001 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29414 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30415 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38886556 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 876785569 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 915672125 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014165 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014639 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014165 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014639 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38847.708292 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39009.304348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38894.987986 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29677.093690 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29677.093690 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38847.708292 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29808.443904 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30105.938682 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38847.708292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29808.443904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30105.938682 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072080 # number of replacements -system.cpu.dcache.tagsinuse 4072.471065 # Cycle average of tags in use -system.cpu.dcache.total_refs 71944468 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076176 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.652394 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21165048000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.471065 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40602724 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40602724 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341737 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341737 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71944461 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71944461 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71944461 # number of overall hits -system.cpu.dcache.overall_hits::total 71944461 # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.522671 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994268 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994268 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40072419 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40072419 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341704 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341704 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71414123 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71414123 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71414123 # number of overall hits +system.cpu.dcache.overall_hits::total 71414123 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2626925 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2626925 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33448316996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33448316996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42699344 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42699344 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74669662 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74669662 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74669662 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74669662 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060772 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060772 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036497 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036497 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036497 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036497 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11926.786684 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11926.786684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21541.187563 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21541.187563 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.579710 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12272.579710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.579710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12272.579710 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32228 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74139096 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74139096 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74139096 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74139096 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061521 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061521 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036755 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036755 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036755 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036755 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.903052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.903052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21486.715649 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21486.715649 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12274.733363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12274.733363 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32679 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9462 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.406045 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.440981 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066214 # number of writebacks -system.cpu.dcache.writebacks::total 2066214 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 633159 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 633159 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15862 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15862 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 649021 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 649021 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 649021 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 649021 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994027 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994027 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82153 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82153 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076180 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076180 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076180 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076180 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983040000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983040000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1837362499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1837362499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23820402499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23820402499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23820402499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23820402499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.444504 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.444504 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22365.129685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22365.129685 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.187536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.187536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.187536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.187536 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2066867 # number of writebacks +system.cpu.dcache.writebacks::total 2066867 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632543 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 632543 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15848 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15848 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 648391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 648391 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 648391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 648391 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994382 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994382 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076582 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076582 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076582 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076582 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833120496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833120496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23820936996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23820936996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23820936996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23820936996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046708 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046708 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028009 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028009 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028009 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028009 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.877130 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.877130 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22300.735961 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22300.735961 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.223865 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.223865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.223865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.223865 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index f4ab1803f..19252022f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540700 # Simulator instruction rate (inst/s) -host_op_rate 952086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 578214744 # Simulator tick rate (ticks/s) -host_mem_usage 420252 # Number of bytes of host memory used -host_seconds 292.19 # Real time elapsed on the host +host_inst_rate 992711 # Simulator instruction rate (inst/s) +host_op_rate 1748005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1061587108 # Simulator tick rate (ticks/s) +host_mem_usage 424044 # Number of bytes of host memory used +host_seconds 159.15 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory @@ -41,7 +41,7 @@ system.cpu.committedInsts 157988548 # Nu system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 8475189 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls system.cpu.num_int_insts 278186175 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index ac797fce6..f8e97e7f1 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 284823 # Simulator instruction rate (inst/s) -host_op_rate 501527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 659807143 # Simulator tick rate (ticks/s) -host_mem_usage 428704 # Number of bytes of host memory used -host_seconds 554.69 # Real time elapsed on the host +host_inst_rate 466388 # Simulator instruction rate (inst/s) +host_op_rate 821234 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1080412484 # Simulator tick rate (ticks/s) +host_mem_usage 431468 # Number of bytes of host memory used +host_seconds 338.75 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory @@ -42,7 +42,7 @@ system.cpu.committedInsts 157988548 # Nu system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 8475189 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls system.cpu.num_int_insts 278186175 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 97c2e1466..2c49dab74 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434544 # Number of seconds simulated -sim_ticks 434543595000 # Number of ticks simulated -final_tick 434543595000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.451833 # Number of seconds simulated +sim_ticks 451832922000 # Number of ticks simulated +final_tick 451832922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65471 # Simulator instruction rate (inst/s) -host_op_rate 121063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34406418 # Simulator tick rate (ticks/s) -host_mem_usage 403752 # Number of bytes of host memory used -host_seconds 12629.72 # Real time elapsed on the host +host_inst_rate 67045 # Simulator instruction rate (inst/s) +host_op_rate 123974 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36635806 # Simulator tick rate (ticks/s) +host_mem_usage 390776 # Number of bytes of host memory used +host_seconds 12333.10 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 207168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24469184 # Number of bytes read from this memory -system.physmem.bytes_read::total 24676352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 207168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 207168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18791424 # Number of bytes written to this memory -system.physmem.bytes_written::total 18791424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3237 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382331 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385568 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293616 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293616 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 476748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56310079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56786827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43244048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43244048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43244048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56310079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100030875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385570 # Total number of read requests seen -system.physmem.writeReqs 293616 # Total number of write requests seen -system.physmem.cpureqs 889416 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24676352 # Total number of bytes read from memory -system.physmem.bytesWritten 18791424 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24676352 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18791424 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 147 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 210200 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 23300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24510 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 22591 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24225 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 24541 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 24693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24144 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24284 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23905 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 17803 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 18814 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18269 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 17556 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18028 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18330 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18773 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18765 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18401 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 18543 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18573 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 17879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18107 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24482112 # Number of bytes read from this memory +system.physmem.bytes_read::total 24684928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18794304 # Number of bytes written to this memory +system.physmem.bytes_written::total 18794304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385702 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293661 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293661 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 448874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54183993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54632867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 448874 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 448874 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41595694 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41595694 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41595694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 448874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54183993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 96228561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385702 # Total number of read requests seen +system.physmem.writeReqs 293661 # Total number of write requests seen +system.physmem.cpureqs 815428 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24684928 # Total number of bytes read from memory +system.physmem.bytesWritten 18794304 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24684928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18794304 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 136028 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23977 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22639 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23451 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24452 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 25055 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24328 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24340 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23420 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24898 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23991 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17770 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18792 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18332 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17557 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18303 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18298 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 19016 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 18563 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 17871 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18115 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry -system.physmem.totGap 434543578000 # Total gap between requests +system.physmem.numWrRetry 37 # Number of times wr buffer was full causing retry +system.physmem.totGap 451832896000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385570 # Categorize read packet sizes +system.physmem.readPktSize::6 385702 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293616 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293661 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,300 +124,299 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31 # What write queue length does an incoming req see -system.physmem.totQLat 3416691250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12001501250 # Sum of mem lat for all requests -system.physmem.totBusLat 1927115000 # Total cycles spent in databus access -system.physmem.totBankLat 6657695000 # Total cycles spent in bank access -system.physmem.avgQLat 8864.78 # Average queueing delay per request -system.physmem.avgBankLat 17273.74 # Average bank access latency per request +system.physmem.wrQLenPdf::28 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 39 # What write queue length does an incoming req see +system.physmem.totQLat 3445991500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12040169000 # Sum of mem lat for all requests +system.physmem.totBusLat 1927820000 # Total cycles spent in databus access +system.physmem.totBankLat 6666357500 # Total cycles spent in bank access +system.physmem.avgQLat 8937.53 # Average queueing delay per request +system.physmem.avgBankLat 17289.89 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31138.52 # Average memory access latency -system.physmem.avgRdBW 56.79 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.24 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.79 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.24 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31227.42 # Average memory access latency +system.physmem.avgRdBW 54.63 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 41.60 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 54.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.60 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.78 # Data bus utilization in percentage +system.physmem.busUtil 0.75 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.11 # Average write queue length over time -system.physmem.readRowHits 331804 # Number of row buffer hits during reads -system.physmem.writeRowHits 191849 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.34 # Row buffer hit rate for writes -system.physmem.avgGap 639800.55 # Average gap between requests -system.cpu.branchPred.lookups 214941297 # Number of BP lookups -system.cpu.branchPred.condPredicted 214941297 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13134170 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150507127 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147849168 # Number of BTB hits +system.physmem.avgWrQLen 8.94 # Average write queue length over time +system.physmem.readRowHits 331871 # Number of row buffer hits during reads +system.physmem.writeRowHits 191829 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes +system.physmem.avgGap 665083.17 # Average gap between requests +system.cpu.branchPred.lookups 205621718 # Number of BP lookups +system.cpu.branchPred.condPredicted 205621718 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9907083 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117077740 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114695478 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.233998 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.965231 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25073647 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1800250 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 869087191 # number of cpu cycles simulated +system.cpu.numCycles 903825131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180529479 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193576474 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214941297 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147849168 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371266839 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83403229 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231605654 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 315081 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 80 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173437780 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3837204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 853761597 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.595537 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389460 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167418043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1132282338 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205621718 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139769125 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352430400 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71153000 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 297148174 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255592 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162064992 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2572532 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 878293133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.398381 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.331165 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 486899007 57.03% 57.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24703220 2.89% 59.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27351293 3.20% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28808692 3.37% 66.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18472602 2.16% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24587756 2.88% 71.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30665646 3.59% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28871909 3.38% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183401472 21.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 529920988 60.34% 60.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23389932 2.66% 63.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25306191 2.88% 65.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27947555 3.18% 69.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17765128 2.02% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22905202 2.61% 73.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29375609 3.34% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26663527 3.04% 80.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175019001 19.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 853761597 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247318 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373368 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 236998203 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188180276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313422880 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45147633 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70012605 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2166855434 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70012605 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270389606 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 53986414 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16429 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322684460 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136672083 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2120106693 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31519 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21337249 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 101081597 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 78 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216557030 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5356293513 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5356152135 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 141378 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 878293133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.227502 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.252767 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222360951 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 252528998 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295744531 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46666559 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60992094 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071948592 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 60992094 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255743691 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 109858014 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17204 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306968990 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 144713140 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035757004 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14813 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25048489 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 104458594 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 180 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2138803025 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5151932301 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5151817228 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 115073 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602516176 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1382 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1352 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330488922 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512705517 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204907925 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196340700 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55518293 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2033906543 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22903 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808080301 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 844129 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499423460 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 818593930 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22351 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 853761597 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.117781 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524762171 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1163 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1096 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 344343454 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 496005535 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194479256 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195803959 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55147463 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975947809 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 16072 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772430246 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 489293 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 442088890 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 735772933 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15520 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 878293133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018040 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.884895 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233333722 27.33% 27.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145354336 17.03% 44.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138354387 16.21% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 133038603 15.58% 76.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96103978 11.26% 87.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58771252 6.88% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34916322 4.09% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11980698 1.40% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1908299 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 263200988 29.97% 29.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 149900664 17.07% 47.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137095286 15.61% 62.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132054982 15.04% 77.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91669420 10.44% 88.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56193413 6.40% 94.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34492530 3.93% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11912661 1.36% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1773189 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 853761597 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 878293133 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4978338 32.41% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7792932 50.73% 83.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2590948 16.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4998230 32.74% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7655755 50.14% 82.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2613853 17.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2717915 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190782663 65.86% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438926011 24.28% 90.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175653712 9.71% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2627910 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165981895 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352516 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880818 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429341212 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170245895 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808080301 # Type of FU issued -system.cpu.iq.rate 2.080436 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15362218 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008496 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4486103997 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533565590 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768588128 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24549 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 46362 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5401 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820713311 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 11293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170590285 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772430246 # Type of FU issued +system.cpu.iq.rate 1.961032 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15267838 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008614 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4438895750 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2418277528 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1745063548 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15006 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 33162 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3630 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1785062995 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7179 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172239839 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128603360 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 477781 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 270908 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55748152 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111903378 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 383433 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 329474 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45320259 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12303 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 614 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14682 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 568 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70012605 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16361207 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2863228 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2033929446 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2371289 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512705517 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204908338 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6072 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1817776 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76759 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 270908 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9111612 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4490464 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13602076 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780387317 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431399251 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27692984 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60992094 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 64075051 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7111223 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975963881 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 801543 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 496005535 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194480445 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3509 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4460880 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83569 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 329474 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5903386 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4417104 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10320490 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753197001 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424204757 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19233245 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602062000 # number of memory reference insts executed -system.cpu.iew.exec_branches 169264678 # Number of branches executed -system.cpu.iew.exec_stores 170662749 # Number of stores executed -system.cpu.iew.exec_rate 2.048572 # Inst execution rate -system.cpu.iew.wb_sent 1775274937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768593529 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341496349 # num instructions producing a value -system.cpu.iew.wb_consumers 1964252976 # num instructions consuming a value +system.cpu.iew.exec_refs 591004689 # number of memory reference insts executed +system.cpu.iew.exec_branches 167488871 # Number of branches executed +system.cpu.iew.exec_stores 166799932 # Number of stores executed +system.cpu.iew.exec_rate 1.939752 # Inst execution rate +system.cpu.iew.wb_sent 1749947599 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1745067178 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1326505641 # num instructions producing a value +system.cpu.iew.wb_consumers 1948512890 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035001 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682955 # average fanout of values written-back +system.cpu.iew.wb_rate 1.930758 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680778 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 504973387 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 447002783 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13165974 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 783748992 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.950865 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458310 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9936450 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 817301039 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.870778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.444599 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 290412107 37.05% 37.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195557118 24.95% 62.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62107499 7.92% 69.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92255388 11.77% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25035287 3.19% 84.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28388589 3.62% 88.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9410992 1.20% 89.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10755720 1.37% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69826292 8.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 326881530 40.00% 40.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 191845418 23.47% 63.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62847977 7.69% 71.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92272413 11.29% 82.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25036529 3.06% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27653799 3.38% 88.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9274477 1.13% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11343051 1.39% 91.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70145845 8.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 783748992 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 817301039 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -427,205 +426,205 @@ system.cpu.commit.membars 0 # Nu system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69826292 # number cycles where commit BW limit reached +system.cpu.commit.function_calls 17673145 # Number of function calls committed. +system.cpu.commit.bw_lim_events 70145845 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2747884788 # The number of ROB reads -system.cpu.rob.rob_writes 4138119354 # The number of ROB writes -system.cpu.timesIdled 343577 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15325594 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2723146678 # The number of ROB reads +system.cpu.rob.rob_writes 4013137574 # The number of ROB writes +system.cpu.timesIdled 3358951 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25531998 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.051048 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.051048 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951432 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951432 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357192668 # number of integer regfile reads -system.cpu.int_regfile_writes 1848351672 # number of integer regfile writes -system.cpu.fp_regfile_reads 5396 # number of floating regfile reads -system.cpu.fp_regfile_writes 7 # number of floating regfile writes -system.cpu.misc_regfile_reads 980175338 # number of misc regfile reads +system.cpu.cpi 1.093059 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.093059 # CPI: Total CPI of All Threads +system.cpu.ipc 0.914864 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.914864 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3313860690 # number of integer regfile reads +system.cpu.int_regfile_writes 1826087017 # number of integer regfile writes +system.cpu.fp_regfile_reads 3611 # number of floating regfile reads +system.cpu.fp_regfile_writes 20 # number of floating regfile writes +system.cpu.misc_regfile_reads 964797382 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 5459 # number of replacements -system.cpu.icache.tagsinuse 1031.272902 # Cycle average of tags in use -system.cpu.icache.total_refs 173201219 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7046 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24581.495742 # Average number of references to valid blocks. +system.cpu.icache.replacements 5491 # number of replacements +system.cpu.icache.tagsinuse 1036.603099 # Cycle average of tags in use +system.cpu.icache.total_refs 161916606 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7071 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 22898.685617 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1031.272902 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.503551 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.503551 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173216530 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173216530 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173216530 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173216530 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173216530 # number of overall hits -system.cpu.icache.overall_hits::total 173216530 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 221250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 221250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 221250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 221250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 221250 # number of overall misses -system.cpu.icache.overall_misses::total 221250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1405122498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1405122498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1405122498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1405122498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1405122498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1405122498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173437780 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173437780 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173437780 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173437780 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173437780 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173437780 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001276 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001276 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001276 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001276 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001276 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001276 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6350.836149 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6350.836149 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6350.836149 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6350.836149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6350.836149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6350.836149 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 511 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1036.603099 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.506154 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.506154 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161918575 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161918575 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161918575 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161918575 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161918575 # number of overall hits +system.cpu.icache.overall_hits::total 161918575 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 146417 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 146417 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 146417 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 146417 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 146417 # number of overall misses +system.cpu.icache.overall_misses::total 146417 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 875142000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 875142000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 875142000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 875142000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 875142000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 875142000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162064992 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162064992 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162064992 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162064992 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162064992 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162064992 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000903 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000903 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000903 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000903 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000903 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000903 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5977.051845 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 5977.051845 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 5977.051845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 5977.051845 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1375 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 34.066667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 229.166667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2445 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2445 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2445 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2445 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2445 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2445 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 218805 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 218805 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 218805 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 218805 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 218805 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 218805 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 886299999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 886299999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 886299999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 886299999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 886299999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 886299999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001262 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001262 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001262 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001262 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992782 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268059 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268059 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461188 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151778 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461188 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151778 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48800.647622 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45226.849026 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45291.555408 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.802373 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.802373 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.537995 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.537995 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48800.647622 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.782613 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41192.213650 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48800.647622 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.782613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41192.213650 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293661 # number of writebacks +system.cpu.l2cache.writebacks::total 293661 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3170 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175625 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178795 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 135999 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 135999 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206937 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206937 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382562 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382562 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385732 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158250747 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7922707780 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8080958527 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1364143324 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1364143324 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7842004636 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7842004636 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158250747 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15764712416 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15922963163 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158250747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15764712416 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15922963163 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099599 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100995 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49921.371293 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45111.503374 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45196.781381 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.539372 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.539372 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37895.613815 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37895.613815 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49921.371293 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41208.254913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41279.860533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49921.371293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41208.254913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41279.860533 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529450 # number of replacements -system.cpu.dcache.tagsinuse 4087.791832 # Cycle average of tags in use -system.cpu.dcache.total_refs 405306727 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533546 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.976068 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1794502000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.791832 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997996 # 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number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3890031 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3890031 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3890031 # number of overall misses -system.cpu.dcache.overall_misses::total 3890031 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 51324442500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 51324442500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23758155000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23758155000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75082597500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75082597500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75082597500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75082597500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259465961 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259465961 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2531750 # number of replacements +system.cpu.dcache.tagsinuse 4088.641557 # Cycle average of tags in use +system.cpu.dcache.total_refs 396440107 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2535846 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 156.334457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1679431000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.641557 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998204 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998204 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 247707841 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247707841 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148233543 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148233543 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395941384 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395941384 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395941384 # number of overall hits +system.cpu.dcache.overall_hits::total 395941384 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2871315 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2871315 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 926659 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 926659 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3797974 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3797974 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3797974 # number of overall misses +system.cpu.dcache.overall_misses::total 3797974 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51373394500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51373394500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21994238500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21994238500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 73367633000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 73367633000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 73367633000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 73367633000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250579156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250579156 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408626163 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408626163 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408626163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408626163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011140 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011140 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006701 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006701 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009520 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009520 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009520 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009520 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17756.508657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17756.508657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23768.304066 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23768.304066 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19301.285131 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19301.285131 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19301.285131 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19301.285131 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6798 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399739358 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399739358 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399739358 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399739358 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011459 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006213 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006213 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009501 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009501 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009501 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009501 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.939582 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.939582 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23734.986117 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23734.986117 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19317.571158 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19317.571158 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6008 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 655 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 680 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.378626 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.835294 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331126 # number of writebacks -system.cpu.dcache.writebacks::total 2331126 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127945 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1127945 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16844 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16844 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1144789 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1144789 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1144789 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1144789 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762513 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 982729 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 982729 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2745242 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2745242 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2745242 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2745242 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27781259000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27781259000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21592303500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21592303500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49373562500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49373562500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49373562500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49373562500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006588 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006588 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006718 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006718 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006718 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006718 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15762.300193 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15762.300193 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21971.778079 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21971.778079 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17985.140290 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17985.140290 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17985.140290 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17985.140290 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331818 # number of writebacks +system.cpu.dcache.writebacks::total 2331818 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1107712 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1107712 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16962 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16962 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1124674 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1124674 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1124674 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1124674 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1763603 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909697 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 909697 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2673300 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2673300 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2673300 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2673300 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27774523500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27774523500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972622500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972622500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47747146000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47747146000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47747146000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47747146000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007038 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007038 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006688 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006688 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15748.739087 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15748.739087 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21955.247187 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21955.247187 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index cadafb39e..6867203d8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229328000 # Number of ticks simulated final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 607816 # Simulator instruction rate (inst/s) -host_op_rate 1123920 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 650709398 # Simulator tick rate (ticks/s) -host_mem_usage 293412 # Number of bytes of host memory used -host_seconds 1360.41 # Real time elapsed on the host +host_inst_rate 1006678 # Simulator instruction rate (inst/s) +host_op_rate 1861461 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1077718973 # Simulator tick rate (ticks/s) +host_mem_usage 296180 # Number of bytes of host memory used +host_seconds 821.39 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory @@ -41,7 +41,7 @@ system.cpu.committedInsts 826877110 # Nu system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 35346287 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317562 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index c3c3c6909..7c0f3a039 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872849000 # Number of ticks simulated final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 379189 # Simulator instruction rate (inst/s) -host_op_rate 701163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 755680972 # Simulator tick rate (ticks/s) -host_mem_usage 300836 # Number of bytes of host memory used -host_seconds 2180.65 # Real time elapsed on the host +host_inst_rate 533286 # Simulator instruction rate (inst/s) +host_op_rate 986105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1062778196 # Simulator tick rate (ticks/s) +host_mem_usage 304632 # Number of bytes of host memory used +host_seconds 1550.53 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory @@ -42,7 +42,7 @@ system.cpu.committedInsts 826877110 # Nu system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 35346287 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317562 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 7cb3ea1a2..545751e41 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 922936 # Simulator instruction rate (inst/s) -host_op_rate 1438019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 873209138 # Simulator tick rate (ticks/s) -host_mem_usage 283960 # Number of bytes of host memory used -host_seconds 3259.25 # Real time elapsed on the host +host_inst_rate 1114602 # Simulator instruction rate (inst/s) +host_op_rate 1736651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1054547884 # Simulator tick rate (ticks/s) +host_mem_usage 286860 # Number of bytes of host memory used +host_seconds 2698.79 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory @@ -41,7 +41,7 @@ system.cpu.committedInsts 3008081022 # Nu system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 33534539 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls system.cpu.num_int_insts 4686862527 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 914311460..225f011f6 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu sim_ticks 5882580526000 # Number of ticks simulated final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 579739 # Simulator instruction rate (inst/s) -host_op_rate 903286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1133733281 # Simulator tick rate (ticks/s) -host_mem_usage 291512 # Number of bytes of host memory used -host_seconds 5188.68 # Real time elapsed on the host +host_inst_rate 548624 # Simulator instruction rate (inst/s) +host_op_rate 854806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1072884756 # Simulator tick rate (ticks/s) +host_mem_usage 295308 # Number of bytes of host memory used +host_seconds 5482.96 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -42,7 +42,7 @@ system.cpu.committedInsts 3008081022 # Nu system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 33534539 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls system.cpu.num_int_insts 4686862527 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index fbc39fbab..682644ea7 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.082784 # Number of seconds simulated -sim_ticks 82784332500 # Number of ticks simulated -final_tick 82784332500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144599 # Number of seconds simulated +sim_ticks 144599413000 # Number of ticks simulated +final_tick 144599413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28862 # Simulator instruction rate (inst/s) -host_op_rate 48376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18091276 # Simulator tick rate (ticks/s) -host_mem_usage 321848 # Number of bytes of host memory used -host_seconds 4575.93 # Real time elapsed on the host +host_inst_rate 53694 # Simulator instruction rate (inst/s) +host_op_rate 89995 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58787129 # Simulator tick rate (ticks/s) +host_mem_usage 325332 # Number of bytes of host memory used +host_seconds 2459.71 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362962 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124352 # Number of bytes read from this memory -system.physmem.bytes_read::total 342080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1943 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5345 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2630063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1502120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4132183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2630063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2630063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2630063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1502120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4132183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5347 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 217792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory +system.physmem.bytes_read::total 343104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5361 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1506175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 866615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2372790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1506175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1506175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1506175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 866615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2372790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5365 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5510 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342080 # Total number of bytes read from memory +system.physmem.cpureqs 5519 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 343104 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342080 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 343104 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 163 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 378 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 356 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 322 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 281 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 374 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 374 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 377 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 366 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 353 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 249 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 82784303000 # Total gap between requests +system.physmem.totGap 144599380000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5347 # Categorize read packet sizes +system.physmem.readPktSize::6 5365 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,267 +149,267 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 15985000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 132177500 # Sum of mem lat for all requests -system.physmem.totBusLat 26735000 # Total cycles spent in databus access -system.physmem.totBankLat 89457500 # Total cycles spent in bank access -system.physmem.avgQLat 2989.53 # Average queueing delay per request -system.physmem.avgBankLat 16730.41 # Average bank access latency per request +system.physmem.totQLat 15365500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 134288000 # Sum of mem lat for all requests +system.physmem.totBusLat 26825000 # Total cycles spent in databus access +system.physmem.totBankLat 92097500 # Total cycles spent in bank access +system.physmem.avgQLat 2864.03 # Average queueing delay per request +system.physmem.avgBankLat 17166.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24719.94 # Average memory access latency -system.physmem.avgRdBW 4.13 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25030.38 # Average memory access latency +system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.13 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4531 # Number of row buffer hits during reads +system.physmem.readRowHits 4467 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15482383.21 # Average gap between requests -system.cpu.branchPred.lookups 19946660 # Number of BP lookups -system.cpu.branchPred.condPredicted 19946660 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2010176 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 13817098 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13100139 # Number of BTB hits +system.physmem.avgGap 26952354.15 # Average gap between requests +system.cpu.branchPred.lookups 18673504 # Number of BP lookups +system.cpu.branchPred.condPredicted 18673504 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1493262 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11432454 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10793701 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.811074 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.412809 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1324082 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 23521 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 165568666 # number of cpu cycles simulated +system.cpu.numCycles 289482612 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25865179 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219003921 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19946660 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13100139 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 57576020 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17616732 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 66658067 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 301 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2079 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 100 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24478210 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 431162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 165440333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.186068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325239 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23502455 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 207109778 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18673504 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12117783 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54283022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15594841 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178283916 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1444 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8051 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22396392 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 221801 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269918552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.268498 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756525 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 109457492 66.16% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3058910 1.85% 68.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2395088 1.45% 69.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2913515 1.76% 71.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3447820 2.08% 73.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3570209 2.16% 75.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4310601 2.61% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2725404 1.65% 79.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33561294 20.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 217073469 80.42% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2850604 1.06% 81.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2315423 0.86% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2639736 0.98% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3229574 1.20% 84.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3384900 1.25% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3844403 1.42% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2562175 0.95% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32018268 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 165440333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.120474 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322738 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38757375 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56681760 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44701919 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9960692 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15338587 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 353512832 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 15338587 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46220216 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14972536 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23135 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46536732 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42349127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 345185267 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 94 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18050300 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22188357 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 104 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 398793355 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 959907307 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 950110032 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9797275 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269918552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064506 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.715448 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36985977 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167209662 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41646466 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10236820 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13839627 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336463810 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13839627 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45047343 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116751427 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 32413 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42745141 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51502601 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 330086802 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10951 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26152362 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22736681 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 382815435 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 919037508 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 910796649 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8240859 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428606 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 139364749 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1689 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1679 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90442233 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 86625401 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31763472 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 57799485 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18862046 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 333525036 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3363 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 267505666 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 256796 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111713410 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 229404022 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2118 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 165440333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.616931 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.504344 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 123386829 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2258 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2296 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105258591 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84679198 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30165066 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58703856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19098571 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 323202869 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4566 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260671940 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116724 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 101460757 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 211331898 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3321 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269918552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.965743 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.342643 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 45064653 27.24% 27.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46696636 28.23% 55.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32890293 19.88% 75.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19781835 11.96% 87.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13196196 7.98% 95.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4792802 2.90% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2338024 1.41% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 533151 0.32% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 146743 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143572602 53.19% 53.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55645964 20.62% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34208859 12.67% 86.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19077068 7.07% 93.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10849323 4.02% 97.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4139320 1.53% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1825268 0.68% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 469630 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130518 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 165440333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269918552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 135867 5.09% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2266939 84.88% 89.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 267901 10.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 131441 4.84% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2279294 83.91% 88.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 305503 11.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212144 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174223829 65.13% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1597035 0.60% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67207754 25.12% 91.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23264904 8.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210514 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162160673 62.21% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 788045 0.30% 62.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035797 2.70% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1444934 0.55% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65461399 25.11% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22570578 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 267505666 # Type of FU issued -system.cpu.iq.rate 1.615678 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2670707 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 698027148 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 440935220 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260272326 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5352020 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4598390 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2575188 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266272654 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2691575 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19010388 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260671940 # Type of FU issued +system.cpu.iq.rate 0.900475 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2716238 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010420 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 789209442 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 421320217 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255304788 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4885952 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3632838 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2349442 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259718878 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2458786 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18858463 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 29975814 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29182 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 297064 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11247755 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 28029611 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25725 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 290431 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9649349 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49364 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49573 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15338587 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 586618 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 254753 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 333528399 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 189186 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 86625401 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31763472 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1668 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 142182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30086 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 297064 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1176748 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 915608 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2092356 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264614762 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66222036 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2890904 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13839627 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 84981347 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5427028 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 323207435 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 136147 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84679198 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30165066 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2231 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2677235 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14355 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 290431 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 637937 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 905599 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1543536 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258899576 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64693791 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1772364 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 89093330 # number of memory reference insts executed -system.cpu.iew.exec_branches 14607419 # Number of branches executed -system.cpu.iew.exec_stores 22871294 # Number of stores executed -system.cpu.iew.exec_rate 1.598218 # Inst execution rate -system.cpu.iew.wb_sent 263675320 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 262847514 # cumulative count of insts written-back -system.cpu.iew.wb_producers 212089133 # num instructions producing a value -system.cpu.iew.wb_consumers 375086159 # num instructions consuming a value +system.cpu.iew.exec_refs 87060323 # number of memory reference insts executed +system.cpu.iew.exec_branches 14273836 # Number of branches executed +system.cpu.iew.exec_stores 22366532 # Number of stores executed +system.cpu.iew.exec_rate 0.894353 # Inst execution rate +system.cpu.iew.wb_sent 258261406 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257654230 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206076672 # num instructions producing a value +system.cpu.iew.wb_consumers 369295783 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.587544 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.565441 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890051 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.558026 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 112202846 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101920014 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2010398 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 150101746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.474753 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.942108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1494473 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 256078925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.864433 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.651734 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50823152 33.86% 33.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57296396 38.17% 72.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13814368 9.20% 81.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12061169 8.04% 89.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4147019 2.76% 92.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2963443 1.97% 94.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1057939 0.70% 94.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1004682 0.67% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6933578 4.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156603135 61.15% 61.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57289650 22.37% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14093127 5.50% 89.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12068952 4.71% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4185763 1.63% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2969218 1.16% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 905577 0.35% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1050426 0.41% 97.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6913077 2.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 150101746 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 256078925 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -419,201 +419,199 @@ system.cpu.commit.membars 0 # Nu system.cpu.commit.branches 12326938 # Number of branches committed system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6933578 # number cycles where commit BW limit reached +system.cpu.commit.function_calls 797818 # Number of function calls committed. +system.cpu.commit.bw_lim_events 6913077 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 476733976 # The number of ROB reads -system.cpu.rob.rob_writes 682504424 # The number of ROB writes -system.cpu.timesIdled 2963 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 128333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 572448824 # The number of ROB reads +system.cpu.rob.rob_writes 660431667 # The number of ROB writes +system.cpu.timesIdled 5928357 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19564060 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.253632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.253632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.797682 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.797682 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 562551000 # number of integer regfile reads -system.cpu.int_regfile_writes 298759078 # number of integer regfile writes -system.cpu.fp_regfile_reads 3525668 # number of floating regfile reads -system.cpu.fp_regfile_writes 2235326 # number of floating regfile writes -system.cpu.misc_regfile_reads 137020971 # number of misc regfile reads +system.cpu.cpi 2.191868 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.191868 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456232 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456232 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554310914 # number of integer regfile reads +system.cpu.int_regfile_writes 293915019 # number of integer regfile writes +system.cpu.fp_regfile_reads 3215317 # number of floating regfile reads +system.cpu.fp_regfile_writes 2009393 # number of floating regfile writes +system.cpu.misc_regfile_reads 133439176 # number of misc regfile reads system.cpu.misc_regfile_writes 845 # number of misc regfile writes -system.cpu.icache.replacements 4809 # number of replacements -system.cpu.icache.tagsinuse 1620.816173 # Cycle average of tags in use -system.cpu.icache.total_refs 24469178 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6775 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3611.686790 # Average number of references to valid blocks. +system.cpu.icache.replacements 4633 # number of replacements +system.cpu.icache.tagsinuse 1627.424900 # Cycle average of tags in use +system.cpu.icache.total_refs 22387705 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6601 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3391.562642 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1620.816173 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.791414 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.791414 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24469178 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24469178 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24469178 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24469178 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24469178 # number of overall hits -system.cpu.icache.overall_hits::total 24469178 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9032 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9032 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9032 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9032 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9032 # number of overall misses -system.cpu.icache.overall_misses::total 9032 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 270256997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 270256997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 270256997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 270256997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 270256997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 270256997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24478210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24478210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24478210 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24478210 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24478210 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24478210 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000369 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000369 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000369 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000369 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000369 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000369 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29922.165301 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29922.165301 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29922.165301 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29922.165301 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29922.165301 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29922.165301 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 940 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1627.424900 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.794641 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.794641 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22387705 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22387705 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22387705 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22387705 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22387705 # number of overall hits +system.cpu.icache.overall_hits::total 22387705 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8687 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8687 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8687 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8687 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8687 # number of overall misses +system.cpu.icache.overall_misses::total 8687 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 264464000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 264464000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 264464000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 264464000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 264464000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 264464000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22396392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22396392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22396392 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22396392 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22396392 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22396392 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30443.651433 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30443.651433 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30443.651433 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30443.651433 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30443.651433 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30443.651433 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 666 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 34.814815 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.625000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2092 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2092 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2092 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2092 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2092 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2092 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6940 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6940 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6940 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6940 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6940 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6940 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204869497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 204869497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204869497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 204869497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204869497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 204869497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000284 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000284 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29520.100432 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29520.100432 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29520.100432 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29520.100432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29520.100432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29520.100432 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1931 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1931 # 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Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.897497 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2558.702101 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3231 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3835 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.842503 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.566236 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2241.747095 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 280.407381 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000048 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.068413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.008557 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 47053208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1433.982512 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.350093 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.350093 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45680422 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45680422 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66194460 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66194460 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66194460 # number of overall hits +system.cpu.dcache.overall_hits::total 66194460 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 872 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 872 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1693 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1693 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2565 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2565 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2565 # number of overall misses +system.cpu.dcache.overall_misses::total 2565 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 43604500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 43604500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76098000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76098000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 119702500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 119702500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 119702500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 119702500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45681294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45681294 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67568939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67568939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67568939 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67568939 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50305.625000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50305.625000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44751.592357 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44751.592357 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46509.893154 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46509.893154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46509.893154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46509.893154 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 66197025 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66197025 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66197025 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66197025 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50005.160550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50005.160550 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44948.611931 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44948.611931 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46667.641326 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46667.641326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46667.641326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46667.641326 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 170 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 382 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 414 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 414 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 383 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 383 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 383 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 383 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 418 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1726 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1726 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73798500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73798500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97858500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 97858500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97858500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 97858500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 415 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 415 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 415 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 415 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1692 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1692 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2150 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2150 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2150 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2150 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26607000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26607000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 72678500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 72678500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 99285500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 99285500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 99285500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 99285500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57559.808612 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57559.808612 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42756.952491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42756.952491 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45642.957090 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45642.957090 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45642.957090 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45642.957090 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58093.886463 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58093.886463 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42954.196217 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42954.196217 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46179.302326 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46179.302326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46179.302326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46179.302326 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index bb0c7510f..817f7471e 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393068000 # Number of ticks simulated final_tick 131393068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 538543 # Simulator instruction rate (inst/s) -host_op_rate 902645 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 535777601 # Simulator tick rate (ticks/s) -host_mem_usage 308992 # Number of bytes of host memory used -host_seconds 245.24 # Real time elapsed on the host +host_inst_rate 929815 # Simulator instruction rate (inst/s) +host_op_rate 1558452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 925040607 # Simulator tick rate (ticks/s) +host_mem_usage 311764 # Number of bytes of host memory used +host_seconds 142.04 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362963 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory @@ -41,7 +41,7 @@ system.cpu.committedInsts 132071193 # Nu system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 1595632 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls system.cpu.num_int_insts 220339554 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 1372cb624..cfc0b5abb 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957000 # Number of ticks simulated final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 308460 # Simulator instruction rate (inst/s) -host_op_rate 517006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 586117013 # Simulator tick rate (ticks/s) -host_mem_usage 316420 # Number of bytes of host memory used -host_seconds 428.16 # Real time elapsed on the host +host_inst_rate 507243 # Simulator instruction rate (inst/s) +host_op_rate 850184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 963833485 # Simulator tick rate (ticks/s) +host_mem_usage 320216 # Number of bytes of host memory used +host_seconds 260.37 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362963 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -35,7 +35,7 @@ system.cpu.committedInsts 132071193 # Nu system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 1595632 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls system.cpu.num_int_insts 220339554 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions |