diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/se | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/se')
24 files changed, 13133 insertions, 13112 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 722ef4fea..7484e6ff9 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269661 # Number of seconds simulated -sim_ticks 269661304500 # Number of ticks simulated -final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269672 # Number of seconds simulated +sim_ticks 269671683500 # Number of ticks simulated +final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98682 # Simulator instruction rate (inst/s) -host_op_rate 98682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44214559 # Simulator tick rate (ticks/s) -host_mem_usage 273520 # Number of bytes of host memory used -host_seconds 6098.93 # Real time elapsed on the host +host_inst_rate 125294 # Simulator instruction rate (inst/s) +host_op_rate 125294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56139844 # Simulator tick rate (ticks/s) +host_mem_usage 224468 # Number of bytes of host memory used +host_seconds 4803.57 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -43,41 +43,41 @@ system.physmem.bytesConsumedRd 1682816 # by system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269661252500 # Total gap between requests +system.physmem.totGap 269671631500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 364261179 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests -system.physmem.totBusLat 105120000 # Total cycles spent in databus access -system.physmem.totBankLat 554778000 # Total cycles spent in bank access -system.physmem.avgQLat 13860.78 # Average queueing delay per request -system.physmem.avgBankLat 21110.27 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38971.05 # Average memory access latency +system.physmem.totQLat 384531397 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests +system.physmem.totBusLat 131400000 # Total cycles spent in databus access +system.physmem.totBankLat 580703750 # Total cycles spent in bank access +system.physmem.avgQLat 14632.09 # Average queueing delay per request +system.physmem.avgBankLat 22096.79 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 41728.89 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 17406 # Number of row buffer hits during reads -system.physmem.writeRowHits 51 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes -system.physmem.avgGap 9874807.84 # Average gap between requests -system.cpu.branchPred.lookups 86405274 # Number of BP lookups -system.cpu.branchPred.condPredicted 81476244 # Number of conditional branches predicted +system.physmem.readRowHits 16315 # Number of row buffer hits during reads +system.physmem.writeRowHits 296 # Number of row buffer hits during writes +system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes +system.physmem.avgGap 9875187.91 # Average gap between requests +system.cpu.branchPred.lookups 86405403 # Number of BP lookups +system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44773910 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.411153 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517568 # DTB read hits +system.cpu.dtb.read_hits 114517881 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520199 # DTB read accesses -system.cpu.dtb.write_hits 39453362 # DTB write hits +system.cpu.dtb.read_accesses 114520512 # DTB read accesses +system.cpu.dtb.write_hits 39453501 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455664 # DTB write accesses -system.cpu.dtb.data_hits 153970930 # DTB hits +system.cpu.dtb.write_accesses 39455803 # DTB write accesses +system.cpu.dtb.data_hits 153971382 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153975863 # DTB accesses -system.cpu.itb.fetch_hits 24997854 # ITB hits +system.cpu.dtb.data_accesses 153976315 # DTB accesses +system.cpu.itb.fetch_hits 24997849 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 24997876 # ITB accesses +system.cpu.itb.fetch_accesses 24997871 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,18 +234,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539322610 # number of cpu cycles simulated +system.cpu.numCycles 539343368 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 154928367 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken). @@ -256,12 +256,12 @@ system.cpu.execution_unit.executions 412128439 # Nu system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed. -system.cpu.activity 90.582759 # Percentage of cycles cpu is active +system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed. +system.cpu.activity 90.579328 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -273,77 +273,77 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use -system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use +system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits -system.cpu.icache.overall_hits::total 24996820 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits +system.cpu.icache.overall_hits::total 24996815 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses system.cpu.icache.overall_misses::total 1034 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -359,38 +359,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 855 system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46086000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46086000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46086000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46086000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46086000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46086000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53901.754386 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53901.754386 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.623478 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698215 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -415,17 +415,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42639500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472401500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 515041000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1150527000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1150527000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42639500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1622928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1665568000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42639500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -450,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114521.575758 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103713.451470 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53944.439235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53944.439235 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 63344.032859 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 63344.032859 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +482,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450997778 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 880714009 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 880714009 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32024355 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1299687432 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1331711787 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32024355 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1299687432 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1331711787 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -504,51 +504,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38078.900119 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101569.314667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90817.111961 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41293.792620 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41293.792620 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.419207 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786016 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use +system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306286 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.419207 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits -system.cpu.dcache.overall_hits::total 151786016 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179347 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179347 # number of overall misses -system.cpu.dcache.overall_misses::total 2179347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991137000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5991137000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22893915500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22893915500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28885052500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28885052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28885052500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28885052500 # number of overall miss cycles +system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120811 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665348 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665348 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786159 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786159 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786159 # number of overall hits +system.cpu.dcache.overall_hits::total 151786159 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393231 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393231 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785973 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785973 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179204 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2179204 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2179204 # number of overall misses +system.cpu.dcache.overall_misses::total 2179204 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -557,40 +557,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 # system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15228.581088 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15228.581088 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12819.022606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12819.022606 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13253.994201 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13253.994201 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 167214 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 552 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5590 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 393ed8f87..fd6611525 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133779 # Number of seconds simulated -sim_ticks 133778696500 # Number of ticks simulated -final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133806 # Number of seconds simulated +sim_ticks 133806308500 # Number of ticks simulated +final_tick 133806308500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160169 # Simulator instruction rate (inst/s) -host_op_rate 160169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37887208 # Simulator tick rate (ticks/s) -host_mem_usage 273648 # Number of bytes of host memory used -host_seconds 3530.97 # Real time elapsed on the host +host_inst_rate 271409 # Simulator instruction rate (inst/s) +host_op_rate 271409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64213833 # Simulator tick rate (ticks/s) +host_mem_usage 226532 # Number of bytes of host memory used +host_seconds 2083.76 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636416 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67008 # Number of bytes written to this memory -system.physmem.bytes_written::total 67008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25569 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26520 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1047 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1047 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 454960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12232262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12687222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 454960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 500887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 500887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 500887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 454960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12232262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13188109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26520 # Total number of read requests seen -system.physmem.writeReqs 1047 # Total number of write requests seen -system.physmem.cpureqs 27567 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697280 # Total number of bytes read from memory -system.physmem.bytesWritten 67008 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697280 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67008 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory +system.physmem.bytes_written::total 67200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26529 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 459649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12229259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12688908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 459649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 459649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 502218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 502218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 502218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 459649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12229259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13191127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26529 # Total number of read requests seen +system.physmem.writeReqs 1050 # Total number of write requests seen +system.physmem.cpureqs 27579 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697856 # Total number of bytes read from memory +system.physmem.bytesWritten 67200 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697856 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1568 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 84 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 57 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133778628000 # Total gap between requests +system.physmem.totGap 133806263000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26520 # Categorize read packet sizes +system.physmem.readPktSize::6 26529 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1047 # categorize write packet sizes +system.physmem.writePktSize::6 1050 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see @@ -150,9 +150,9 @@ system.physmem.wrQLenPdf::8 46 # Wh system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 650833420 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1266537420 # Sum of mem lat for all requests -system.physmem.totBusLat 106020000 # Total cycles spent in databus access -system.physmem.totBankLat 509684000 # Total cycles spent in bank access -system.physmem.avgQLat 24555.12 # Average queueing delay per request -system.physmem.avgBankLat 19229.73 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 47784.85 # Average memory access latency +system.physmem.totQLat 648232398 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1339932398 # Sum of mem lat for all requests +system.physmem.totBusLat 132570000 # Total cycles spent in databus access +system.physmem.totBankLat 559130000 # Total cycles spent in bank access +system.physmem.avgQLat 24448.68 # Average queueing delay per request +system.physmem.avgBankLat 21088.10 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 50536.79 # Average memory access latency system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.37 # Average write queue length over time -system.physmem.readRowHits 18044 # Number of row buffer hits during reads -system.physmem.writeRowHits 53 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes -system.physmem.avgGap 4852854.06 # Average gap between requests -system.cpu.branchPred.lookups 76440222 # Number of BP lookups -system.cpu.branchPred.condPredicted 70864810 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2706098 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43060392 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41933015 # Number of BTB hits +system.physmem.avgWrQLen 10.03 # Average write queue length over time +system.physmem.readRowHits 16972 # Number of row buffer hits during reads +system.physmem.writeRowHits 273 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.00 # Row buffer hit rate for writes +system.physmem.avgGap 4851744.55 # Average gap between requests +system.cpu.branchPred.lookups 76500721 # Number of BP lookups +system.cpu.branchPred.condPredicted 70919742 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2718676 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43116993 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41952631 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.381870 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1604413 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.299529 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1606312 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122603551 # DTB read hits -system.cpu.dtb.read_misses 28565 # DTB read misses +system.cpu.dtb.read_hits 122623794 # DTB read hits +system.cpu.dtb.read_misses 28860 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122632116 # DTB read accesses -system.cpu.dtb.write_hits 40753368 # DTB write hits -system.cpu.dtb.write_misses 25574 # DTB write misses +system.cpu.dtb.read_accesses 122652654 # DTB read accesses +system.cpu.dtb.write_hits 40761180 # DTB write hits +system.cpu.dtb.write_misses 25673 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40778942 # DTB write accesses -system.cpu.dtb.data_hits 163356919 # DTB hits -system.cpu.dtb.data_misses 54139 # DTB misses +system.cpu.dtb.write_accesses 40786853 # DTB write accesses +system.cpu.dtb.data_hits 163384974 # DTB hits +system.cpu.dtb.data_misses 54533 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163411058 # DTB accesses -system.cpu.itb.fetch_hits 65475592 # ITB hits -system.cpu.itb.fetch_misses 42 # ITB misses +system.cpu.dtb.data_accesses 163439507 # DTB accesses +system.cpu.itb.fetch_hits 65534932 # ITB hits +system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65475634 # ITB accesses +system.cpu.itb.fetch_accesses 65534973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,238 +234,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267557394 # number of cpu cycles simulated +system.cpu.numCycles 267612618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43537428 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117782486 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11617306 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73490715 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 67186400 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699453099 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76500721 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43558943 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117852914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11666249 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73358963 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65475592 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 928038 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267274328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.615488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444547 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65534932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 934826 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267314333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.616594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444810 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149491842 55.93% 55.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10342090 3.87% 59.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11847639 4.43% 64.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10563390 3.95% 68.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7011808 2.62% 70.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2869024 1.07% 71.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3576964 1.34% 73.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3101400 1.16% 74.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68470171 25.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149461419 55.91% 55.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10349982 3.87% 59.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11850266 4.43% 64.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10577716 3.96% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7012506 2.62% 70.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2870690 1.07% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3579816 1.34% 73.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3108437 1.16% 74.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68503501 25.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267274328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285697 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.612721 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84240613 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57793701 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102635866 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13724657 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8879491 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3873839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 920 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691093913 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3105 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8879491 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92211740 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12790279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1241 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103054645 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50336932 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 680961604 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 408 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38688874 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5430085 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520709674 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 896990234 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 896987596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2638 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267314333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285864 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.613678 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84322022 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57655855 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102751859 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13670665 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8913932 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3876852 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 942 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691462372 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8913932 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92304341 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12773232 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1346 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103106270 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50215212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681285072 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 434 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38522944 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5472741 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520920645 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897379043 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897376453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2590 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 56854785 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 64 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112289485 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 126970724 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42377686 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14852387 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10147583 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621083354 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604563100 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299815 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 54897951 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29938787 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267274328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.261957 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.823661 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57065756 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 66 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112077327 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127005785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42387861 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14833107 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10089887 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621266103 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 59 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604722021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299730 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55073821 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30009810 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267314333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.262213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.825151 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52499760 19.64% 19.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55875325 20.91% 40.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53442699 20.00% 60.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36269586 13.57% 74.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31423380 11.76% 85.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23799839 8.90% 94.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9996979 3.74% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3415050 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 551710 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52513972 19.65% 19.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55954300 20.93% 40.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53424383 19.99% 60.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36299246 13.58% 74.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31212895 11.68% 85.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23807225 8.91% 94.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10138155 3.79% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3408674 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 555483 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267274328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267314333 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2734710 70.93% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 35 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 729519 18.92% 89.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 391400 10.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2798552 71.38% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 727516 18.56% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 394572 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439055623 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7072 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124323040 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41177317 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439175234 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7035 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124352577 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41187127 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604563100 # Type of FU issued -system.cpu.iq.rate 2.259564 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3855664 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006378 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480552206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 675984537 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596489873 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3801 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2284 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1738 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608416848 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1916 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12282855 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604722021 # Type of FU issued +system.cpu.iq.rate 2.259692 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3920679 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480975025 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676343136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596595322 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3759 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1723 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608640802 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1898 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12279325 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12456682 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 35904 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5518 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2926365 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12491743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36092 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5478 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2936540 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6461 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 52889 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6432 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54776 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8879491 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1456554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 192142 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 663913486 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1691538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 126970724 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42377686 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 144242 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7408 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5518 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1333964 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1804152 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3138116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599464075 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122632263 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5099025 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8913932 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1438086 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 192048 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664143136 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1694587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127005785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42387861 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 59 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 143884 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7497 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5478 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342912 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1811100 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3154012 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599591446 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122652830 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5130575 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42830076 # number of nop insts executed -system.cpu.iew.exec_refs 163429760 # number of memory reference insts executed -system.cpu.iew.exec_branches 66623337 # Number of branches executed -system.cpu.iew.exec_stores 40797497 # Number of stores executed -system.cpu.iew.exec_rate 2.240506 # Inst execution rate -system.cpu.iew.wb_sent 597426155 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596491611 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415927297 # num instructions producing a value -system.cpu.iew.wb_consumers 530215795 # num instructions consuming a value +system.cpu.iew.exec_nop 42876974 # number of nop insts executed +system.cpu.iew.exec_refs 163458157 # number of memory reference insts executed +system.cpu.iew.exec_branches 66641389 # Number of branches executed +system.cpu.iew.exec_stores 40805327 # Number of stores executed +system.cpu.iew.exec_rate 2.240520 # Inst execution rate +system.cpu.iew.wb_sent 597536756 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596597045 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415962909 # num instructions producing a value +system.cpu.iew.wb_consumers 530370743 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229397 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784449 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229331 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784287 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 61932723 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62162261 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2705240 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258394837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.329214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.691172 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2717793 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258400401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.692856 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79550578 30.79% 30.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72525012 28.07% 58.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25515345 9.87% 68.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9289171 3.59% 72.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10288497 3.98% 76.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21029047 8.14% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6874256 2.66% 87.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3694459 1.43% 88.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29628472 11.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79574518 30.80% 30.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72566023 28.08% 58.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25599330 9.91% 68.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9197400 3.56% 72.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10258446 3.97% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20921268 8.10% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6836400 2.65% 87.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3734572 1.45% 88.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29712444 11.50% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258394837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258400401 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29628472 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29712444 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892491662 # The number of ROB reads -system.cpu.rob.rob_writes 1336472901 # The number of ROB writes -system.cpu.timesIdled 34286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 283066 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892642792 # The number of ROB reads +system.cpu.rob.rob_writes 1336966756 # The number of ROB writes +system.cpu.timesIdled 34291 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 298285 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473090 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473090 # CPI: Total CPI of All Threads -system.cpu.ipc 2.113761 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.113761 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 844970192 # number of integer regfile reads -system.cpu.int_regfile_writes 490533624 # number of integer regfile writes -system.cpu.fp_regfile_reads 397 # number of floating regfile reads +system.cpu.cpi 0.473188 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473188 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113325 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113325 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845166386 # number of integer regfile reads +system.cpu.int_regfile_writes 490617161 # number of integer regfile writes +system.cpu.fp_regfile_reads 389 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 825.012562 # Cycle average of tags in use -system.cpu.icache.total_refs 65474211 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67848.923316 # Average number of references to valid blocks. +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 825.582407 # Cycle average of tags in use +system.cpu.icache.total_refs 65533545 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 66939.269663 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.012562 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.402838 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.402838 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65474211 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65474211 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65474211 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65474211 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65474211 # number of overall hits -system.cpu.icache.overall_hits::total 65474211 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses -system.cpu.icache.overall_misses::total 1381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68875500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68875500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68875500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68875500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68875500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68875500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65475592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65475592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65475592 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65475592 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65475592 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65475592 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 825.582407 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.403116 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.403116 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65533545 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65533545 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65533545 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65533545 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65533545 # number of overall hits +system.cpu.icache.overall_hits::total 65533545 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1386 # number of overall misses +system.cpu.icache.overall_misses::total 1386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 74542000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 74542000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 74542000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 74542000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 74542000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 74542000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65534931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65534931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65534931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65534931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65534931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65534931 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.642288 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49873.642288 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49873.642288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49873.642288 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53782.106782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53782.106782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53782.106782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53782.106782 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50216500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50216500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50216500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50216500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50216500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50216500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 407 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 407 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39058.344900 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85735.098422 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77294.407682 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55726.736889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55726.736889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1050 # number of writebacks +system.cpu.l2cache.writebacks::total 1050 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4311 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21257 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21257 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25568 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26529 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25568 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26529 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41447516 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363900322 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405347838 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1236862753 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1236862753 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41447516 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1600763075 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1642210591 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41447516 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1600763075 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1642210591 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020483 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024933 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083503 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083503 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054981 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056927 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054981 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056927 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43129.569199 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84412.044073 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76886.919196 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58186.138825 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58186.138825 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 461041 # number of replacements -system.cpu.dcache.tagsinuse 4090.869171 # Cycle average of tags in use -system.cpu.dcache.total_refs 146891319 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465137 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.802267 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305775000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.869171 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998747 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998747 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109242892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109242892 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648409 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648409 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146891301 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146891301 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146891301 # number of overall hits -system.cpu.dcache.overall_hits::total 146891301 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1026587 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1026587 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802912 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802912 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2829499 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2829499 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2829499 # number of overall misses -system.cpu.dcache.overall_misses::total 2829499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15441177000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15441177000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25867331616 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25867331616 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41308508616 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41308508616 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41308508616 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41308508616 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110269479 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110269479 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 460939 # number of replacements +system.cpu.dcache.tagsinuse 4090.899850 # Cycle average of tags in use +system.cpu.dcache.total_refs 146914514 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 465035 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 315.921412 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 301771000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.899850 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 109265934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109265934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648563 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146914497 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146914497 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146914497 # number of overall hits +system.cpu.dcache.overall_hits::total 146914497 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1025246 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1025246 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802758 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802758 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2828004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2828004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2828004 # number of overall misses +system.cpu.dcache.overall_misses::total 2828004 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15342477500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15342477500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26169777829 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26169777829 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 37000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 37000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41512255329 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41512255329 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41512255329 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41512255329 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110291180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110291180 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149720800 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149720800 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149720800 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149720800 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.142857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.142857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15041.274631 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15041.274631 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14347.528674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14347.528674 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14599.230682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14599.230682 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 277266 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17305 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 149742501 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149742501 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149742501 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149742501 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009296 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009296 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045696 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045696 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.190476 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.190476 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018886 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018886 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018886 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018886 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14964.679209 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14964.679209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14516.522922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14516.522922 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14678.994559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14678.994559 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 301355 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2673 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17784 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.022306 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 83.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.945288 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 243 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445099 # number of writebacks -system.cpu.dcache.writebacks::total 445099 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 816026 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 816026 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548336 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548336 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2364362 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2364362 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2364362 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2364362 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210561 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210561 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254576 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 465137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 465137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 465137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 465137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2703972000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2703972000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4046409990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4046409990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6750381990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6750381990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6750381990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6750381990 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 445006 # number of writebacks +system.cpu.dcache.writebacks::total 445006 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814778 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 814778 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548191 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548191 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2362969 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2362969 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2362969 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2362969 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210468 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210468 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254567 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254567 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 465035 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 465035 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 465035 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 465035 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697344500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697344500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097543997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097543997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6794888497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6794888497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6794888497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6794888497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003107 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003107 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12841.751321 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12841.751321 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15894.703311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15894.703311 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12815.936389 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12815.936389 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16096.131851 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16096.131851 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 08bc3f5b4..e289c0e8e 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164543 # Number of seconds simulated -sim_ticks 164543008000 # Number of ticks simulated -final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164572 # Number of seconds simulated +sim_ticks 164572262000 # Number of ticks simulated +final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116480 # Simulator instruction rate (inst/s) -host_op_rate 123082 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33621508 # Simulator tick rate (ticks/s) -host_mem_usage 289348 # Number of bytes of host memory used -host_seconds 4893.98 # Real time elapsed on the host +host_inst_rate 164809 # Simulator instruction rate (inst/s) +host_op_rate 174150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47579904 # Simulator tick rate (ticks/s) +host_mem_usage 241928 # Number of bytes of host memory used +host_seconds 3458.86 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1700992 # Number of bytes read from this memory -system.physmem.bytes_read::total 1747904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162560 # Number of bytes written to this memory -system.physmem.bytes_written::total 162560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 733 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26578 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27311 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2540 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 285105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10337674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10622779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 285105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 285105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 987948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 987948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 987948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 285105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10337674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11610727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27312 # Total number of read requests seen -system.physmem.writeReqs 2540 # Total number of write requests seen -system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1747904 # Total number of bytes read from memory -system.physmem.bytesWritten 162560 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1747904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162560 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1701952 # Number of bytes read from this memory +system.physmem.bytes_read::total 1749376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162432 # Number of bytes written to this memory +system.physmem.bytes_written::total 162432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 741 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26593 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27334 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2538 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2538 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 288165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10341670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10629835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 288165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 288165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 986995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 986995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 986995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 288165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10341670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11616830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27336 # Total number of read requests seen +system.physmem.writeReqs 2538 # Total number of write requests seen +system.physmem.cpureqs 29874 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1749376 # Total number of bytes read from memory +system.physmem.bytesWritten 162432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1749376 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162432 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1686 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164542992000 # Total gap between requests +system.physmem.totGap 164572246000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27312 # Categorize read packet sizes +system.physmem.readPktSize::6 27336 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2540 # categorize write packet sizes +system.physmem.writePktSize::6 2538 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 785 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,16 +138,16 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,36 +171,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 954202972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1658730972 # Sum of mem lat for all requests -system.physmem.totBusLat 109248000 # Total cycles spent in databus access -system.physmem.totBankLat 595280000 # Total cycles spent in bank access -system.physmem.avgQLat 34937.13 # Average queueing delay per request -system.physmem.avgBankLat 21795.55 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 60732.68 # Average memory access latency -system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 921366434 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1672075184 # Sum of mem lat for all requests +system.physmem.totBusLat 136675000 # Total cycles spent in databus access +system.physmem.totBankLat 614033750 # Total cycles spent in bank access +system.physmem.avgQLat 33705.24 # Average queueing delay per request +system.physmem.avgBankLat 22462.46 # Average bank access latency per request +system.physmem.avgBusLat 4999.82 # Average bus latency per request +system.physmem.avgMemAccLat 61167.51 # Average memory access latency +system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 7.51 # Average write queue length over time -system.physmem.readRowHits 17750 # Number of row buffer hits during reads -system.physmem.writeRowHits 1096 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes -system.physmem.avgGap 5511958.73 # Average gap between requests -system.cpu.branchPred.lookups 85130885 # Number of BP lookups -system.cpu.branchPred.condPredicted 79914937 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2339051 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47115734 # Number of BTB lookups -system.cpu.branchPred.BTBHits 46860934 # Number of BTB hits +system.physmem.avgWrQLen 7.98 # Average write queue length over time +system.physmem.readRowHits 16887 # Number of row buffer hits during reads +system.physmem.writeRowHits 1046 # Number of row buffer hits during writes +system.physmem.readRowHitRate 61.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes +system.physmem.avgGap 5508878.82 # Average gap between requests +system.cpu.branchPred.lookups 85156760 # Number of BP lookups +system.cpu.branchPred.condPredicted 79937555 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2342179 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47221599 # Number of BTB lookups +system.cpu.branchPred.BTBHits 46882126 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.459204 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1427305 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 879 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.281107 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1427254 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1090 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,134 +244,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329086017 # number of cpu cycles simulated +system.cpu.numCycles 329144525 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48288239 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129602885 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13082707 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119327277 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 198 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67069040 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754631 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328130780 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 68500133 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666893560 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85156760 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48309380 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129633878 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13101459 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119325440 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 311 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67084243 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755399 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328191292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198528126 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20911347 6.37% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4965496 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14342607 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8889042 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9432606 2.87% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4398382 1.34% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5787527 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60875647 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198557643 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20911639 6.37% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4968720 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14346044 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8890886 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9446619 2.88% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4399795 1.34% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788532 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60881414 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328130780 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258689 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92913811 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96211222 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107901766 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20387668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10716313 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4735353 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1507 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703148359 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5732 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10716313 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107108772 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14420824 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39598 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114018818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81826455 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694730633 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59350869 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20332423 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 690 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721206841 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230143140 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230143012 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328191292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258721 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026142 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92969239 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96174869 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107931491 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20385682 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10730011 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4738020 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1580 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703286632 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5586 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10730011 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107159029 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14373843 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114052351 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81836170 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694854437 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59359193 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20344162 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721334030 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230715755 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230715627 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93789468 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1631 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1577 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170614097 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172186244 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80451329 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21497797 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28523197 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 679922328 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2842 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645571900 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1371428 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77382290 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193030922 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 138 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328130780 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967423 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726248 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93916657 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1707 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1652 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170570480 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172204690 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80467392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21722432 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29158581 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 680011931 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645607270 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1367531 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77472778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193408701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 215 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328191292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68155781 20.77% 20.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85368264 26.02% 46.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75828661 23.11% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40814489 12.44% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28806063 8.78% 91.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14910916 4.54% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5593541 1.70% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6461751 1.97% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2191314 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85141417 25.94% 46.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76162034 23.21% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40819071 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14914630 4.54% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328130780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328191292 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 217275 5.77% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2690091 71.47% 77.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 856746 22.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 216791 5.75% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2693843 71.39% 77.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 862775 22.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403353378 62.48% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403382320 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued @@ -399,84 +399,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165552451 25.64% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76659500 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165566556 25.65% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76651819 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645571900 # Type of FU issued -system.cpu.iq.rate 1.961712 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3764112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005831 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624410084 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757319559 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637543970 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645607270 # Type of FU issued +system.cpu.iq.rate 1.961470 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3773409 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005845 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624546736 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757499752 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637553210 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649335992 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649380659 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30371258 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30362769 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23233651 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124604 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12357 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10230316 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23252097 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121645 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12371 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10246379 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12884 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32539 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12896 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35853 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10716313 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 798788 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92055 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 679928215 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 686727 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172186244 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80451329 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1514 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33028 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15856 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12357 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1355593 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2815897 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641504035 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163487420 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4067865 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10730011 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 795888 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 91006 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 680017934 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 687807 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172204690 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80467392 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32670 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15237 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12371 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1357657 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460843 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2818500 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641514820 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163491606 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4092450 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3045 # number of nop insts executed -system.cpu.iew.exec_refs 239375677 # number of memory reference insts executed -system.cpu.iew.exec_branches 74669000 # Number of branches executed -system.cpu.iew.exec_stores 75888257 # Number of stores executed -system.cpu.iew.exec_rate 1.949351 # Inst execution rate -system.cpu.iew.wb_sent 638951120 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637543986 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418515101 # num instructions producing a value -system.cpu.iew.wb_consumers 649819096 # num instructions consuming a value +system.cpu.iew.exec_nop 3084 # number of nop insts executed +system.cpu.iew.exec_refs 239364786 # number of memory reference insts executed +system.cpu.iew.exec_branches 74674061 # Number of branches executed +system.cpu.iew.exec_stores 75873180 # Number of stores executed +system.cpu.iew.exec_rate 1.949037 # Inst execution rate +system.cpu.iew.wb_sent 638961643 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637553226 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418732313 # num instructions producing a value +system.cpu.iew.wb_consumers 650059572 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937317 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937001 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644145 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77576557 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77666777 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2337624 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317414467 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897708 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237617 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2340669 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317461281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897428 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237399 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93227454 29.37% 29.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104339541 32.87% 62.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42982023 13.54% 75.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8785495 2.77% 78.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25936003 8.17% 86.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12920810 4.07% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7630828 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1171764 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20420549 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93255759 29.38% 29.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104348924 32.87% 62.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42985847 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8791848 2.77% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25959048 8.18% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12901404 4.06% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7629324 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1168492 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20420635 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317414467 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317461281 # Number of insts commited each cycle system.cpu.commit.committedInsts 570051636 # Number of instructions committed system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,195 +487,195 @@ system.cpu.commit.branches 70892524 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20420549 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20420635 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 976929705 # The number of ROB reads -system.cpu.rob.rob_writes 1370620821 # The number of ROB writes -system.cpu.timesIdled 41180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 955237 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977066653 # The number of ROB reads +system.cpu.rob.rob_writes 1370815087 # The number of ROB writes +system.cpu.timesIdled 44013 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 953233 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570051585 # Number of Instructions Simulated system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated -system.cpu.cpi 0.577292 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577292 # CPI: Total CPI of All Threads -system.cpu.ipc 1.732227 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.732227 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204271897 # number of integer regfile reads -system.cpu.int_regfile_writes 663022837 # number of integer regfile writes +system.cpu.cpi 0.577394 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577394 # CPI: Total CPI of All Threads +system.cpu.ipc 1.731919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.731919 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204307958 # number of integer regfile reads +system.cpu.int_regfile_writes 663049374 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234769906 # number of misc regfile reads +system.cpu.misc_regfile_reads 234758339 # number of misc regfile reads system.cpu.misc_regfile_writes 2656 # number of misc regfile writes -system.cpu.icache.replacements 58 # number of replacements -system.cpu.icache.tagsinuse 683.079303 # Cycle average of tags in use -system.cpu.icache.total_refs 67067899 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 817 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82090.451652 # Average number of references to valid blocks. +system.cpu.icache.replacements 66 # number of replacements +system.cpu.icache.tagsinuse 690.513263 # Cycle average of tags in use +system.cpu.icache.total_refs 67083102 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 830 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 80823.014458 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 683.079303 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.333535 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.333535 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67067899 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67067899 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67067899 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67067899 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67067899 # number of overall hits -system.cpu.icache.overall_hits::total 67067899 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 690.513263 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.337165 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.337165 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67083102 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67083102 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67083102 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67083102 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67083102 # number of overall hits +system.cpu.icache.overall_hits::total 67083102 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses system.cpu.icache.overall_misses::total 1141 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51270999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51270999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51270999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51270999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51270999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51270999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67069040 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67069040 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67069040 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67069040 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67069040 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67069040 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54478999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54478999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54478999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54478999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54478999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54478999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67084243 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67084243 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67084243 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67084243 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67084243 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67084243 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44935.143734 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44935.143734 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44935.143734 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44935.143734 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47746.712533 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47746.712533 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47746.712533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47746.712533 # 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number of writebacks -system.cpu.l2cache.writebacks::total 2540 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 2538 # number of writebacks +system.cpu.l2cache.writebacks::total 2538 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 9 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26579 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27312 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27884656 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 667944528 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695829184 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273842866 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273842866 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27884656 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941787394 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1969672050 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27884656 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941787394 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1969672050 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024247 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027843 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088160 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088160 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061308 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061308 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38041.822647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139474.739612 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126010.355668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58459.975493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58459.975493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 741 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4804 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5545 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310031171 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149679 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937942647 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969092326 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149679 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937942647 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969092326 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088162 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088162 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061347 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061347 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42037.353576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130705.969192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118856.835888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.992336 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.992336 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440572 # number of replacements -system.cpu.dcache.tagsinuse 4091.500520 # Cycle average of tags in use -system.cpu.dcache.total_refs 197561073 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444668 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 444.288937 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 320822000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.500520 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998901 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998901 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131514845 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131514845 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66043576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66043576 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1323 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1323 # number of LoadLockedReq hits +system.cpu.dcache.replacements 440669 # number of replacements +system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use +system.cpu.dcache.total_refs 197567614 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444765 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.206747 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314058000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.484070 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998897 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998897 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131523721 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131523721 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66041240 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66041240 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1324 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1324 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197558421 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197558421 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197558421 # number of overall hits -system.cpu.dcache.overall_hits::total 197558421 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341798 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341798 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3373955 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3373955 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 20 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 20 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3715753 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3715753 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3715753 # number of overall misses -system.cpu.dcache.overall_misses::total 3715753 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5154955000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5154955000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40277017700 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40277017700 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 312000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 312000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45431972700 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45431972700 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45431972700 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45431972700 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131856643 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131856643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 197564961 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197564961 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197564961 # number of overall hits +system.cpu.dcache.overall_hits::total 197564961 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 341919 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 341919 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3376291 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3376291 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3718210 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses +system.cpu.dcache.overall_misses::total 3718210 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45778801266 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45778801266 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45778801266 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45778801266 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201274174 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201274174 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201274174 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201274174 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048604 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048604 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.014892 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.014892 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018461 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018461 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018461 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018461 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15081.875845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15081.875845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11937.627414 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 11937.627414 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15600 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15600 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12226.854880 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12226.854880 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132982 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4828 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.543911 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 201283171 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201283171 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201283171 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201283171 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002593 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002593 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048637 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048637 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016345 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016345 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.521697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.521697 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.930261 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421606 # number of writebacks -system.cpu.dcache.writebacks::total 421606 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144292 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144292 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3126791 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3126791 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 20 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3271083 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3271083 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3271083 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3271083 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197506 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247164 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444670 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444670 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444670 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444670 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2876994000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2876994000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4061058256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4061058256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6938052256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6938052256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938052256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6938052256 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 421643 # number of writebacks +system.cpu.dcache.writebacks::total 421643 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144320 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144320 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3129122 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3129122 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3273442 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3273442 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3273442 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3273442 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197599 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197599 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247169 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247169 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444768 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932840321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6932840321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932840321 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6932840321 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14566.615698 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14566.615698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16430.622000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16430.622000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 6eebaa49a..a9ed274c0 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387280 # Number of seconds simulated -sim_ticks 387279743500 # Number of ticks simulated -final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387316 # Number of seconds simulated +sim_ticks 387315507500 # Number of ticks simulated +final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131929 # Simulator instruction rate (inst/s) -host_op_rate 132344 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36464205 # Simulator tick rate (ticks/s) -host_mem_usage 283820 # Number of bytes of host memory used -host_seconds 10620.82 # Real time elapsed on the host +host_inst_rate 205717 # Simulator instruction rate (inst/s) +host_op_rate 206366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56864239 # Simulator tick rate (ticks/s) +host_mem_usage 235456 # Number of bytes of host memory used +host_seconds 6811.23 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678400 # Number of bytes read from this memory -system.physmem.bytes_read::total 1754816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678528 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76544 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1194 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26227 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4949724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27420 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4333749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4333749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4949928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27424 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1754816 # Total number of bytes read from memory +system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755072 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1754816 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 166 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387279715500 # Total gap between requests +system.physmem.totGap 387315479500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27420 # Categorize read packet sizes +system.physmem.readPktSize::6 27424 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 7981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,267 +171,267 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 724473296 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1405549296 # Sum of mem lat for all requests -system.physmem.totBusLat 109680000 # Total cycles spent in databus access -system.physmem.totBankLat 571396000 # Total cycles spent in bank access -system.physmem.avgQLat 26421.35 # Average queueing delay per request -system.physmem.avgBankLat 20838.66 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51260.00 # Average memory access latency +system.physmem.totQLat 713274952 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1439334952 # Sum of mem lat for all requests +system.physmem.totBusLat 137120000 # Total cycles spent in databus access +system.physmem.totBankLat 588940000 # Total cycles spent in bank access +system.physmem.avgQLat 26009.15 # Average queueing delay per request +system.physmem.avgBankLat 21475.35 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 52484.50 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.06 # Average write queue length over time -system.physmem.readRowHits 18324 # Number of row buffer hits during reads -system.physmem.writeRowHits 1098 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes -system.physmem.avgGap 12929580.19 # Average gap between requests -system.cpu.branchPred.lookups 97757265 # Number of BP lookups -system.cpu.branchPred.condPredicted 88048400 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3615880 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65812942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65493412 # Number of BTB hits +system.physmem.avgWrQLen 16.51 # Average write queue length over time +system.physmem.readRowHits 17585 # Number of row buffer hits during reads +system.physmem.writeRowHits 1048 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes +system.physmem.avgGap 12929047.62 # Average gap between requests +system.cpu.branchPred.lookups 97759655 # Number of BP lookups +system.cpu.branchPred.condPredicted 88050231 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3614520 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65786552 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65492883 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.514488 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1346 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.553603 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1341 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774559488 # number of cpu cycles simulated +system.cpu.numCycles 774631016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65494758 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329201347 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20830567 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263300608 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2484 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 164855721 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642251558 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97759655 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65494224 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329204399 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20834739 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263342259 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2502 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161939590 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 736919 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774350695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126792 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161937023 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 736247 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774398184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146676 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445149348 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74062635 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37899346 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077460 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28106060 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18772938 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11486101 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3791039 0.49% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146005768 18.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445193785 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74062525 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37899229 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077552 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28106227 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772117 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11485912 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3791430 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146009407 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774350695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120227 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215923264 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214411776 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284212483 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42813992 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16989180 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636523306 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16989180 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239767996 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36725834 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52426044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302047092 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126394549 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625641256 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 163 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927570 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73422293 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3124815 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356325471 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746325758 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712253189 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34072569 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774398184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126202 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215922553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214452390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284209898 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42820116 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16993227 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636550752 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16993227 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239771948 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36701097 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52424917 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302039391 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126467604 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625687860 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30927407 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73464560 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3152152 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356365192 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746429093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712307786 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111555032 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2644888 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2664020 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271706062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436927389 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179744218 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254493315 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83217297 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512489363 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2610612 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459355655 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53704 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109193723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130058810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 366941 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774350695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884619 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431536 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2643942 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179754378 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254555015 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82904621 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512542697 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2609193 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459339312 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53583 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109245499 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130204517 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 365522 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774398184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145647727 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184570267 23.84% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209695290 27.08% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131219118 16.95% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70710319 9.13% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20417492 2.64% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8005951 1.03% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3903236 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181295 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145558409 18.80% 18.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184658706 23.85% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209828049 27.10% 69.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131187469 16.94% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70686123 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20416273 2.64% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7987184 1.03% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3894628 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181343 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774350695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774398184 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 116724 6.93% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95410 5.66% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1152580 68.43% 81.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 319525 18.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 118946 7.04% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95273 5.64% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1158517 68.57% 81.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 316903 18.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866464141 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866474644 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644770 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419120072 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171126672 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644797 0.18% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419098125 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171121746 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459355655 # Type of FU issued -system.cpu.iq.rate 1.884110 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1684239 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001154 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676971209 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615339802 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443231270 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17828739 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9193054 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8547507 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451917046 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9122848 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215321036 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459339312 # Type of FU issued +system.cpu.iq.rate 1.883915 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1689639 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676979008 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615425319 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443226704 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17841022 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9210458 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8545776 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451900530 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9128421 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215265115 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34414546 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58846 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 246003 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12896076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34428392 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58884 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245184 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12906236 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3349 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91624 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3305 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 101102 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16989180 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3081240 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 246114 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608786135 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4123964 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436927389 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179744218 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2527628 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 148187 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 246003 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2270880 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473539 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3744419 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454037467 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416573795 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5318188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16993227 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3018866 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247688 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608835504 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4126277 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436941235 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179754378 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2526244 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 149012 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1899 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245184 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2269311 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3742374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454021381 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416550474 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5317931 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93686160 # number of nop insts executed -system.cpu.iew.exec_refs 587024674 # number of memory reference insts executed -system.cpu.iew.exec_branches 89036390 # Number of branches executed -system.cpu.iew.exec_stores 170450879 # Number of stores executed -system.cpu.iew.exec_rate 1.877244 # Inst execution rate -system.cpu.iew.wb_sent 1452666848 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451778777 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153445523 # num instructions producing a value -system.cpu.iew.wb_consumers 1204705379 # num instructions consuming a value +system.cpu.iew.exec_nop 93683614 # number of nop insts executed +system.cpu.iew.exec_refs 586997386 # number of memory reference insts executed +system.cpu.iew.exec_branches 89036634 # Number of branches executed +system.cpu.iew.exec_stores 170446912 # Number of stores executed +system.cpu.iew.exec_rate 1.877050 # Inst execution rate +system.cpu.iew.wb_sent 1452648479 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451772480 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153427719 # num instructions producing a value +system.cpu.iew.wb_consumers 1204682131 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874328 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874147 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957454 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119167265 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119216890 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3615880 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757361515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966727 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509795 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3614520 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757404957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509691 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240009654 31.69% 31.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275743732 36.41% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42570119 5.62% 73.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54687779 7.22% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19671272 2.60% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13286277 1.75% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30573058 4.04% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10535838 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70283786 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 239974569 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275852046 36.42% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42571811 5.62% 73.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54691782 7.22% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19624283 2.59% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13282059 1.75% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30580381 4.04% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10561653 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70266373 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757361515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757404957 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,192 +442,192 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70283786 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70266373 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295703406 # The number of ROB reads -system.cpu.rob.rob_writes 3234392884 # The number of ROB writes -system.cpu.timesIdled 26078 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295813886 # The number of ROB reads +system.cpu.rob.rob_writes 3234496299 # The number of ROB writes +system.cpu.timesIdled 25967 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 232832 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552787 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552787 # CPI: Total CPI of All Threads -system.cpu.ipc 1.809014 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.809014 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979140277 # number of integer regfile reads -system.cpu.int_regfile_writes 1275189089 # number of integer regfile writes -system.cpu.fp_regfile_reads 16965348 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491584 # number of floating regfile writes -system.cpu.misc_regfile_reads 592679771 # number of misc regfile reads +system.cpu.cpi 0.552838 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552838 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808847 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808847 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979103244 # number of integer regfile reads +system.cpu.int_regfile_writes 1275174788 # number of integer regfile writes +system.cpu.fp_regfile_reads 16962430 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491706 # number of floating regfile writes +system.cpu.misc_regfile_reads 592650972 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 200 # number of replacements -system.cpu.icache.tagsinuse 1035.695786 # Cycle average of tags in use -system.cpu.icache.total_refs 161937647 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121029.631540 # Average number of references to valid blocks. +system.cpu.icache.replacements 197 # number of replacements +system.cpu.icache.tagsinuse 1035.237714 # Cycle average of tags in use +system.cpu.icache.total_refs 161935084 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1336 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121208.895210 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.695786 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505711 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505711 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161937647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161937647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161937647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161937647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161937647 # number of overall hits -system.cpu.icache.overall_hits::total 161937647 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses -system.cpu.icache.overall_misses::total 1943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81333500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81333500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81333500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81333500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81333500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81333500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161939590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161939590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161939590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161939590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161939590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161939590 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.237714 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505487 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505487 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161935084 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161935084 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161935084 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161935084 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161935084 # number of overall hits +system.cpu.icache.overall_hits::total 161935084 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1939 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1939 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1939 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1939 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1939 # number of overall misses +system.cpu.icache.overall_misses::total 1939 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84566500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 84566500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 84566500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 84566500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 84566500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 84566500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161937023 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161937023 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161937023 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161937023 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161937023 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161937023 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41859.752959 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41859.752959 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41859.752959 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41859.752959 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43613.460547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43613.460547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43613.460547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43613.460547 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59309500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59309500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59309500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59309500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59309500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59309500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 602 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 602 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 602 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1337 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1337 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1337 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1337 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1337 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1337 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62189000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62189000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62189000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62189000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62189000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62189000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44293.876027 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44293.876027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46513.836948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46513.836948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46513.836948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 46513.836948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46513.836948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 46513.836948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22451.919806 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550398 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24266 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.681859 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22451.693912 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550222 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24270 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.670869 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.013315 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.728994 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 647.177496 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633057 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019750 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685178 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 144 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 196423 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 196567 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443928 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 443928 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240651 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240651 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 144 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437074 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31927965942 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46916057442 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46916057442 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46916057442 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46916057442 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201141784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201141784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2814422 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2814422 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2814422 # number of overall misses +system.cpu.dcache.overall_misses::total 2814422 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14739603500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14739603500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31907348686 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31907348686 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46646952186 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46646952186 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46646952186 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46646952186 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201164550 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201164550 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 367988600 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 367988600 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 367988600 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 367988600 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004612 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004612 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368011366 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368011366 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368011366 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368011366 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004589 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004589 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007661 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007661 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007661 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007661 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16156.340312 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16156.340312 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16881.108261 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16881.108261 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16642.600778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16642.600778 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573681 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35664 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.085717 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007648 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007648 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007648 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007648 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.283038 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.283038 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16869.993336 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16869.993336 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16574.256521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16574.256521 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 590116 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35661 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.547938 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443928 # number of writebacks -system.cpu.dcache.writebacks::total 443928 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726830 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 726830 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628912 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628912 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2355742 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2355742 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2355742 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2355742 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200861 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200861 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262431 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262431 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443933 # number of writebacks +system.cpu.dcache.writebacks::total 443933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722205 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722205 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628938 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628938 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2351143 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2351143 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2351143 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2351143 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200850 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262429 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262429 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463292 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463292 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463292 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463292 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2635998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2635998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319921000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319921000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6955919000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6955919000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6955919000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6955919000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 463279 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463279 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463279 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463279 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2612152000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2612152000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970086500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6970086500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970086500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6970086500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -800,16 +800,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13123.493361 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13123.493361 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16461.168841 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16461.168841 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.486682 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.486682 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 3548dbe1a..dc034cfd1 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.607446 # Number of seconds simulated -sim_ticks 607445544000 # Number of ticks simulated -final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607292 # Number of seconds simulated +sim_ticks 607292111000 # Number of ticks simulated +final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56942 # Simulator instruction rate (inst/s) -host_op_rate 104918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39304494 # Simulator tick rate (ticks/s) -host_mem_usage 295872 # Number of bytes of host memory used -host_seconds 15454.86 # Real time elapsed on the host +host_inst_rate 91190 # Simulator instruction rate (inst/s) +host_op_rate 168022 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62928697 # Simulator tick rate (ticks/s) +host_mem_usage 248736 # Number of bytes of host memory used +host_seconds 9650.48 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory -system.physmem.bytes_read::total 1750912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57728 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 1750848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 57664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57664 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory system.physmem.bytes_written::total 162176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 902 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 901 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27358 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27357 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2787384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2882418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 266980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 266980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 266980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2787384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3149398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 94953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2788088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2883041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 267048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 267048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 267048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2788088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3150089 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 27359 # Total number of read requests seen system.physmem.writeReqs 2534 # Total number of write requests seen system.physmem.cpureqs 29893 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1750912 # Total number of bytes read from memory +system.physmem.bytesRead 1750848 # Total number of bytes read from memory system.physmem.bytesWritten 162176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1750912 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1750848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1701 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis +system.physmem.perBankRdReqs::9 1708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1728 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1735 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 159 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 607445530000 # Total gap between requests +system.physmem.totGap 607292095000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 26894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -171,265 +171,265 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 68456669 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 822256669 # Sum of mem lat for all requests -system.physmem.totBusLat 109436000 # Total cycles spent in databus access -system.physmem.totBankLat 644364000 # Total cycles spent in bank access -system.physmem.avgQLat 2502.16 # Average queueing delay per request -system.physmem.avgBankLat 23552.18 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30054.34 # Average memory access latency +system.physmem.totQLat 90448613 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 895548613 # Sum of mem lat for all requests +system.physmem.totBusLat 136795000 # Total cycles spent in databus access +system.physmem.totBankLat 668305000 # Total cycles spent in bank access +system.physmem.avgQLat 3305.99 # Average queueing delay per request +system.physmem.avgBankLat 24427.25 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32733.24 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 6.29 # Average write queue length over time -system.physmem.readRowHits 17697 # Number of row buffer hits during reads -system.physmem.writeRowHits 1084 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes -system.physmem.avgGap 20320661.36 # Average gap between requests -system.cpu.branchPred.lookups 158385701 # Number of BP lookups -system.cpu.branchPred.condPredicted 158385701 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26390414 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 84292336 # Number of BTB lookups -system.cpu.branchPred.BTBHits 84079165 # Number of BTB hits +system.physmem.avgWrQLen 6.24 # Average write queue length over time +system.physmem.readRowHits 16426 # Number of row buffer hits during reads +system.physmem.writeRowHits 1032 # Number of row buffer hits during writes +system.physmem.readRowHitRate 60.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.73 # Row buffer hit rate for writes +system.physmem.avgGap 20315528.55 # Average gap between requests +system.cpu.branchPred.lookups 158482804 # Number of BP lookups +system.cpu.branchPred.condPredicted 158482804 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 26384558 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 84639114 # Number of BTB lookups +system.cpu.branchPred.BTBHits 84422216 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.747105 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.743738 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1214891089 # number of cpu cycles simulated +system.cpu.numCycles 1214584223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed -system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574634441 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 187842503 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11743851 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214538070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 179034165 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1457747721 # Number of instructions fetch has processed +system.cpu.fetch.Branches 158482804 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84422216 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 399024262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88084887 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574618713 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 188004827 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11985682 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214221440 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252911 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 822675212 67.74% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26639433 2.19% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18282936 1.51% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31338155 2.58% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39109954 3.22% 82.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215850749 17.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822415344 67.73% 67.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26978129 2.22% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13144140 1.08% 71.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20617690 1.70% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26634807 2.19% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18232650 1.50% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31447933 2.59% 79.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39056021 3.22% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215694726 17.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214538070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497953948 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336887109 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124143936 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 304057721 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2248180627 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 354 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242798221 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120202889 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2618438730 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5723603734 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5723598334 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5400 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 288175293 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497913619 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274106217 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92482436 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 336850045 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303948664 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387671631 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242705543 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120202916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5424 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895258 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 731543472 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 87 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731379517 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 532059001 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219301341 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 342202544 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144686488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1994506429 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784080761 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 243450 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 761627172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 239 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214538070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.468938 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.421549 # Number of insts issued each cycle +system.cpu.rename.skidInsts 731406447 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144614488 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274040 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 371594187 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 759078017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 237 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214221440 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360345169 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234287346 19.29% 78.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60702765 5.00% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39742301 3.27% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11032116 0.91% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2048046 0.17% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 597279 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360233763 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364161192 29.99% 59.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234288879 19.30% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141409866 11.65% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60623194 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39782569 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214538070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214221440 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 437572 15.09% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2259609 77.90% 92.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 203424 7.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 459684 15.86% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2241246 77.33% 93.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 197213 6.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812462 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065847679 59.74% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478866421 26.84% 89.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192554199 10.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812327 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065713813 59.74% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478893732 26.84% 89.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192532359 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784080761 # Type of FU issued -system.cpu.iq.rate 1.468511 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4785843297 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1704 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740168733 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209903028 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1783952231 # Type of FU issued +system.cpu.iq.rate 1.468776 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2898143 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001625 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4785297542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2365259636 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1724635094 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1776 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210029942 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113016880 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 39297 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180469 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31115283 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 182684 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31031188 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2481 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2402 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 58 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1142265 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63004482 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 532059001 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219301341 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 54039 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2855 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180469 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2045569 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24474359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26519928 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766291934 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474573600 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17788827 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 61543875 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1219448 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 109755 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1993488848 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63065998 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 531670409 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219217246 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 52970 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2883 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 182684 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2045175 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24468993 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26514168 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766143547 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474612951 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17808684 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666299746 # number of memory reference insts executed -system.cpu.iew.exec_branches 110359604 # Number of branches executed -system.cpu.iew.exec_stores 191726146 # Number of stores executed -system.cpu.iew.exec_rate 1.453869 # Inst execution rate -system.cpu.iew.wb_sent 1725940615 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1724820453 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267203875 # num instructions producing a value -system.cpu.iew.wb_consumers 1829107615 # num instructions consuming a value +system.cpu.iew.exec_refs 666319153 # number of memory reference insts executed +system.cpu.iew.exec_branches 110355146 # Number of branches executed +system.cpu.iew.exec_stores 191706202 # Number of stores executed +system.cpu.iew.exec_rate 1.454114 # Inst execution rate +system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267063012 # num instructions producing a value +system.cpu.iew.wb_consumers 1828799696 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.419733 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692799 # average fanout of values written-back +system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 371996186 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26390469 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1152851077 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.406508 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26384610 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1152677565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.406719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.830300 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 418199687 36.28% 36.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24164674 2.10% 92.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25337442 2.20% 94.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16460362 1.43% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12052065 1.05% 97.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32432091 2.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 418027879 36.27% 36.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 415124601 36.01% 72.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86915055 7.54% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122122398 10.59% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24176868 2.10% 92.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25399940 2.20% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16385768 1.42% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12050207 1.05% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32474849 2.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1152851077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152677565 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,194 +440,194 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354437 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32474849 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3114927129 # The number of ROB reads -system.cpu.rob.rob_writes 4050738571 # The number of ROB writes -system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 353019 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3113692828 # The number of ROB reads +system.cpu.rob.rob_writes 4048559892 # The number of ROB writes +system.cpu.timesIdled 59027 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 362783 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.380518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.380518 # CPI: Total CPI of All Threads -system.cpu.ipc 0.724366 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.724366 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3542903494 # number of integer regfile reads -system.cpu.int_regfile_writes 1974699145 # number of integer regfile writes -system.cpu.fp_regfile_reads 92 # number of floating regfile reads -system.cpu.misc_regfile_reads 910807256 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 815.551450 # Cycle average of tags in use -system.cpu.icache.total_refs 187841113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 206418.805495 # Average number of references to valid blocks. +system.cpu.cpi 1.380170 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.380170 # CPI: Total CPI of All Threads +system.cpu.ipc 0.724549 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.724549 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3542852942 # number of integer regfile reads +system.cpu.int_regfile_writes 1974486988 # number of integer regfile writes +system.cpu.fp_regfile_reads 123 # number of floating regfile reads +system.cpu.misc_regfile_reads 910772207 # number of misc regfile reads +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.tagsinuse 816.669933 # Cycle average of tags in use +system.cpu.icache.total_refs 188003443 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 918 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 204796.778867 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 815.551450 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.398218 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.398218 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 187841119 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 187841119 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 187841119 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 187841119 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 187841119 # number of overall hits -system.cpu.icache.overall_hits::total 187841119 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1384 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1384 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1384 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1384 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1384 # number of overall misses -system.cpu.icache.overall_misses::total 1384 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64353500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64353500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64353500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64353500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64353500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64353500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 187842503 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 187842503 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 187842503 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 187842503 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 187842503 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 187842503 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 816.669933 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.398765 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.398765 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 188003447 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 188003447 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 188003447 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 188003447 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 188003447 # number of overall hits +system.cpu.icache.overall_hits::total 188003447 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1380 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1380 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1380 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1380 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1380 # number of overall misses +system.cpu.icache.overall_misses::total 1380 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65047500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65047500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65047500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65047500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65047500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65047500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 188004827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 188004827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 188004827 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 188004827 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 188004827 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 188004827 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46498.193642 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46498.193642 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46498.193642 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46498.193642 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47135.869565 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47135.869565 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47135.869565 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47135.869565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47135.869565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47135.869565 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 34.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 918 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46138000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46138000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46138000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46138000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46138000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46138000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 455 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 455 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 455 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 455 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 455 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 455 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 925 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 925 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 925 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 925 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 925 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47382000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47382000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47382000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47382000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47382000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47382000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50259.259259 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50259.259259 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50259.259259 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50259.259259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50259.259259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50259.259259 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51223.783784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51223.783784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51223.783784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51223.783784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51223.783784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51223.783784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22259.528577 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531228 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24191 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.959737 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22259.325739 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531319 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24190 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.964407 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20782.488903 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 799.212802 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 677.826873 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634231 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024390 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020686 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.679307 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 199209 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 199217 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428963 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428963 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 8 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224450 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024398 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020714 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.679301 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 199250 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 199267 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 429018 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 429018 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224476 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224476 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4063849999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4063849999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7079925999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7079925999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7079925999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7079925999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 446086 # number of replacements +system.cpu.dcache.tagsinuse 4092.713768 # Cycle average of tags in use +system.cpu.dcache.total_refs 452307982 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 450182 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1004.722494 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.713768 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264368372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264368372 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939603 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939603 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452307975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452307975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452307975 # number of overall hits +system.cpu.dcache.overall_hits::total 452307975 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246455 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246455 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457736 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457736 # number of overall misses +system.cpu.dcache.overall_misses::total 457736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022618500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3022618500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119755500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4119755500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7142374000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7142374000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7142374000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7142374000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264579653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264579653 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452853166 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452853166 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 452765711 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452765711 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452765711 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452765711 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000799 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000799 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.059322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.059322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.622232 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.622232 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15472.914465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15472.914465 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.001011 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001011 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.055669 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.055669 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks -system.cpu.dcache.writebacks::total 428963 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570238499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570238499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6093778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6093778999 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 429018 # number of writebacks +system.cpu.dcache.writebacks::total 429018 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 81 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 81 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7545 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7545 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7545 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7545 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203817 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203817 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246374 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246374 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450191 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450191 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450191 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626209000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626209000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154623500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6154623500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154623500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6154623500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -782,14 +782,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.016116 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.016116 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.545155 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.545155 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.310374 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.310374 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 5f270b948..b0849c006 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026773 # Number of seconds simulated -sim_ticks 26773408500 # Number of ticks simulated -final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026779 # Number of seconds simulated +sim_ticks 26779468500 # Number of ticks simulated +final_tick 26779468500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111467 # Simulator instruction rate (inst/s) -host_op_rate 112267 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32943427 # Simulator tick rate (ticks/s) -host_mem_usage 421388 # Number of bytes of host memory used -host_seconds 812.71 # Real time elapsed on the host +host_inst_rate 196675 # Simulator instruction rate (inst/s) +host_op_rate 198087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58139571 # Simulator tick rate (ticks/s) +host_mem_usage 373976 # Number of bytes of host memory used +host_seconds 460.61 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory -system.physmem.bytes_read::total 992576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15509 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1680473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35392729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37073203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1680473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1680473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1680473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35392729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37073203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15509 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory +system.physmem.bytes_read::total 993088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15517 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1689653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35394280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37083932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1689653 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1689653 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1689653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35394280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37083932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15517 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15512 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 992576 # Total number of bytes read from memory +system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 993088 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992576 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 993088 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1011 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 933 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 976 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1002 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26773229500 # Total gap between requests +system.physmem.totGap 26779289500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15509 # Categorize read packet sizes +system.physmem.readPktSize::6 15517 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 3 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 45602981 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 279992981 # Sum of mem lat for all requests -system.physmem.totBusLat 62036000 # Total cycles spent in databus access -system.physmem.totBankLat 172354000 # Total cycles spent in bank access -system.physmem.avgQLat 2940.42 # Average queueing delay per request -system.physmem.avgBankLat 11113.16 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18053.58 # Average memory access latency -system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 52084984 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 311719984 # Sum of mem lat for all requests +system.physmem.totBusLat 77585000 # Total cycles spent in databus access +system.physmem.totBankLat 182050000 # Total cycles spent in bank access +system.physmem.avgQLat 3356.64 # Average queueing delay per request +system.physmem.avgBankLat 11732.29 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 20088.93 # Average memory access latency +system.physmem.avgRdBW 37.08 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 37.08 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15086 # Number of row buffer hits during reads +system.physmem.readRowHits 14783 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1726302.76 # Average gap between requests -system.cpu.branchPred.lookups 26672080 # Number of BP lookups -system.cpu.branchPred.condPredicted 21992542 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842598 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11362388 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11268059 # Number of BTB hits +system.physmem.avgGap 1725803.28 # Average gap between requests +system.cpu.branchPred.lookups 26678818 # Number of BP lookups +system.cpu.branchPred.condPredicted 21998913 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 842318 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11366409 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11281153 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.169814 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70167 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.249930 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69723 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 201 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,134 +237,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53546818 # number of cpu cycles simulated +system.cpu.numCycles 53558938 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11338226 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24008993 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4747196 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11262084 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14172731 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127871641 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26678818 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11350876 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24033181 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4760167 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11226793 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13843627 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 330314 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53334178 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.412341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13844867 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 331224 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53334396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.414044 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215935 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29363698 55.06% 55.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3375400 6.33% 61.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2026423 3.80% 65.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1553443 2.91% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668565 3.13% 71.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2920644 5.48% 76.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1511002 2.83% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1091875 2.05% 81.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9823128 18.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29339451 55.01% 55.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389540 6.36% 61.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028066 3.80% 65.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1555662 2.92% 68.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667100 3.13% 71.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2918330 5.47% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1510510 2.83% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090066 2.04% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9835671 18.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53334178 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498108 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.386304 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16944806 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9096910 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22405465 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1004110 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3882887 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4441553 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8682 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125956281 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42689 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3882887 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18731656 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3549082 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 155235 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21520684 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5494634 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123060237 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 429079 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4593412 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1240 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143474506 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536032151 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536027496 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4655 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53334396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498121 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.387494 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16935376 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9075535 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22432463 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 998016 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3893006 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442432 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126044255 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42607 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3893006 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18714710 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3545279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 156066 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21549370 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5475965 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123134352 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 422701 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4592939 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1259 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143588919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536358187 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536353466 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4721 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36060320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4617 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4615 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12531131 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29463379 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5514746 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2152870 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1249780 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118072720 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8484 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105142122 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 71988 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26643181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65222929 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 266 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53334178 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.971384 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.909777 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36174733 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12509318 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29470006 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5522308 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2104178 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1264650 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118149095 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8470 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105144375 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78107 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26722736 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65554797 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 252 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53334396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.971418 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.910922 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15298443 28.68% 28.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11631181 21.81% 50.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8279084 15.52% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6786399 12.72% 78.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4950529 9.28% 88.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2953624 5.54% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2464815 4.62% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 526374 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443729 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15312252 28.71% 28.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11634281 21.81% 50.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8274633 15.51% 66.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6753758 12.66% 78.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4949297 9.28% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2972831 5.57% 93.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2466224 4.62% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 528093 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 443027 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53334178 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53334396 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 44991 6.81% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 339313 51.37% 58.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276174 41.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 44474 6.73% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340155 51.46% 58.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 276363 41.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74410825 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10970 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74414194 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10982 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -385,91 +385,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 146 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 143 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 182 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 186 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25604346 24.35% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5115650 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25601639 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5117225 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105142122 # Type of FU issued -system.cpu.iq.rate 1.963555 # Inst issue rate -system.cpu.iq.fu_busy_cnt 660505 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006282 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264350195 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144728935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102671361 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 720 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1005 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105802266 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 442877 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105144375 # Type of FU issued +system.cpu.iq.rate 1.963153 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661019 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006287 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264361545 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144884747 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102673470 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 727 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1011 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 322 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105805031 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 444404 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6889413 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6770 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6285 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 769902 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6896040 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6651 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 777464 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 27948 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31327 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3882887 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 927098 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127053 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118093920 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309711 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29463379 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5514746 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4596 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66094 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6965 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6285 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446526 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892658 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104164248 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25284832 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 977874 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3893006 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 929576 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127351 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118170277 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309597 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29470006 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5522308 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4582 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66448 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6858 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446675 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445546 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892221 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104166430 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25281924 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 977945 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12716 # number of nop insts executed -system.cpu.iew.exec_refs 30343472 # number of memory reference insts executed -system.cpu.iew.exec_branches 21324084 # Number of branches executed -system.cpu.iew.exec_stores 5058640 # Number of stores executed -system.cpu.iew.exec_rate 1.945293 # Inst execution rate -system.cpu.iew.wb_sent 102950061 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102671670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62244850 # num instructions producing a value -system.cpu.iew.wb_consumers 104302213 # num instructions consuming a value +system.cpu.iew.exec_nop 12712 # number of nop insts executed +system.cpu.iew.exec_refs 30342174 # number of memory reference insts executed +system.cpu.iew.exec_branches 21323986 # Number of branches executed +system.cpu.iew.exec_stores 5060250 # Number of stores executed +system.cpu.iew.exec_rate 1.944893 # Inst execution rate +system.cpu.iew.wb_sent 102951824 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102673792 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62219945 # num instructions producing a value +system.cpu.iew.wb_consumers 104261628 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.917419 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596774 # average fanout of values written-back +system.cpu.iew.wb_rate 1.917024 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596767 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26843909 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26920302 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834006 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49451291 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.845310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541193 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833747 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49441390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.845680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541256 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19963736 40.37% 40.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13137085 26.57% 66.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4166734 8.43% 75.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3433201 6.94% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1540600 3.12% 85.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 738938 1.49% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 946959 1.91% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 248344 0.50% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275694 10.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19945415 40.34% 40.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13149428 26.60% 66.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4162611 8.42% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3435070 6.95% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1540295 3.12% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 748484 1.51% 86.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 932633 1.89% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 245930 0.50% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5281524 10.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49451291 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49441390 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -480,200 +480,200 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275694 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5281524 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162266732 # The number of ROB reads -system.cpu.rob.rob_writes 240096387 # The number of ROB writes -system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 212640 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162327394 # The number of ROB reads +system.cpu.rob.rob_writes 240259263 # The number of ROB writes +system.cpu.timesIdled 43763 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 224542 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.591091 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.591091 # CPI: Total CPI of All Threads -system.cpu.ipc 1.691787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.691787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495496065 # number of integer regfile reads -system.cpu.int_regfile_writes 120529637 # number of integer regfile writes -system.cpu.fp_regfile_reads 153 # number of floating regfile reads -system.cpu.fp_regfile_writes 387 # number of floating regfile writes -system.cpu.misc_regfile_reads 29090556 # number of misc regfile reads +system.cpu.cpi 0.591225 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.591225 # CPI: Total CPI of All Threads +system.cpu.ipc 1.691404 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.691404 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495495273 # number of integer regfile reads +system.cpu.int_regfile_writes 120530797 # number of integer regfile writes +system.cpu.fp_regfile_reads 175 # number of floating regfile reads +system.cpu.fp_regfile_writes 405 # number of floating regfile writes +system.cpu.misc_regfile_reads 29088840 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.icache.replacements 5 # number of replacements -system.cpu.icache.tagsinuse 628.046446 # Cycle average of tags in use -system.cpu.icache.total_refs 13842647 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 730 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18962.530137 # Average number of references to valid blocks. +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 630.551988 # Cycle average of tags in use +system.cpu.icache.total_refs 13843878 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 733 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18886.600273 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 628.046446 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306663 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306663 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13842647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13842647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13842647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13842647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13842647 # number of overall hits -system.cpu.icache.overall_hits::total 13842647 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 979 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 979 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 979 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 979 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 979 # number of overall misses -system.cpu.icache.overall_misses::total 979 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47680999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47680999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47680999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47680999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47680999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47680999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13843626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13843626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13843626 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13843626 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13843626 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13843626 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 630.551988 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.307887 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.307887 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13843878 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015639 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016373 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965894 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015639 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016373 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52311.440678 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55667.259786 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53264.914055 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43007.497077 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43007.497077 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52311.440678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43247.537112 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 43660.806285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52311.440678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43247.537112 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 43660.806285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,184 +691,184 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15509 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15509 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26990085 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10560900 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37550985 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15517 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15517 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28010860 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11866667 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39877527 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 421398919 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 421398919 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26990085 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431959819 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 458949904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26990085 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431959819 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 458949904 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001072 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.334007 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.334007 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016354 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016354 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38392.724040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39553.932584 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38712.355670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 445060185 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 445060185 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28010860 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 456926852 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 484937712 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28010860 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 456926852 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 484937712 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001081 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333570 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333570 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016362 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016362 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39619.321075 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43788.439114 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40774.567485 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28984.037348 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28984.037348 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30611.471559 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30611.471559 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39619.321075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30852.589602 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31252.027583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39619.321075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30852.589602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31252.027583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943481 # number of replacements -system.cpu.dcache.tagsinuse 3674.468837 # Cycle average of tags in use -system.cpu.dcache.total_refs 28144290 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947577 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.701322 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7935444000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3674.468837 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.897087 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.897087 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23599200 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23599200 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4537276 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4537276 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits +system.cpu.dcache.replacements 943534 # number of replacements +system.cpu.dcache.tagsinuse 3674.806480 # Cycle average of tags in use +system.cpu.dcache.total_refs 28135871 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947630 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.690777 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7938358000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3674.806480 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.897170 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.897170 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23591287 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23591287 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4536767 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4536767 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3920 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3920 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28136476 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28136476 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28136476 # 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number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28128054 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28128054 # number of overall hits +system.cpu.dcache.overall_hits::total 28128054 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173096 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173096 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 198214 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 198214 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1371310 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1371310 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1371310 # number of overall misses +system.cpu.dcache.overall_misses::total 1371310 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884435000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13884435000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5574763392 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5574763392 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19459198392 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19459198392 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19459198392 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19459198392 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24764383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24764383 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29507217 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29507217 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29507217 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29507217 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047353 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047353 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041754 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046454 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046454 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046454 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046454 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.933363 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.933363 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27191.593136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27191.593136 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29214.285714 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29214.285714 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14052.425601 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14052.425601 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132657 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29499364 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29499364 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29499364 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29499364 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047370 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047370 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041862 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041862 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001528 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001528 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046486 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046486 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046486 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046486 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.719327 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.719327 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28124.972969 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28124.972969 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14190.225691 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14190.225691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14190.225691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14190.225691 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152485 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23814 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23871 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.570547 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.387877 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks -system.cpu.dcache.writebacks::total 942884 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268972 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 268972 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154186 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154186 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 423158 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 423158 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 423158 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 423158 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904064 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904064 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43519 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43519 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947583 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947583 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947583 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947583 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9987518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9987518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 958248463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 958248463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945766463 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10945766463 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945766463 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10945766463 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036495 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036495 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009191 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009191 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032114 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032114 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11047.357267 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11047.357267 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22019.082768 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22019.082768 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942924 # number of writebacks +system.cpu.dcache.writebacks::total 942924 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269038 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269038 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154638 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154638 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 423676 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423676 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423676 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423676 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904058 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904058 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43576 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43576 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947634 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947634 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947634 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947634 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990434000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990434000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 980693945 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 980693945 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10971127945 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10971127945 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10971127945 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10971127945 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009203 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009203 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032124 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.656042 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.656042 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22505.368666 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22505.368666 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 860f57b09..8e442dc5d 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065983 # Number of seconds simulated -sim_ticks 65982862500 # Number of ticks simulated -final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066005 # Number of seconds simulated +sim_ticks 66004575000 # Number of ticks simulated +final_tick 66004575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72483 # Simulator instruction rate (inst/s) -host_op_rate 127630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30271870 # Simulator tick rate (ticks/s) -host_mem_usage 430980 # Number of bytes of host memory used -host_seconds 2179.68 # Real time elapsed on the host +host_inst_rate 124260 # Simulator instruction rate (inst/s) +host_op_rate 218802 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51913433 # Simulator tick rate (ticks/s) +host_mem_usage 384868 # Number of bytes of host memory used +host_seconds 1271.44 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory -system.physmem.bytes_read::total 1948288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11136 # Number of bytes written to this memory -system.physmem.bytes_written::total 11136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 174 # Number of write requests responded to by this memory -system.physmem.num_writes::total 174 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 988378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28538804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29527182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 988378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 988378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 168771 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 168771 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 168771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 988378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28538804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29695953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30444 # Total number of read requests seen -system.physmem.writeReqs 174 # Total number of write requests seen -system.physmem.cpureqs 30619 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1948288 # Total number of bytes read from memory -system.physmem.bytesWritten 11136 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1948288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 11136 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882560 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory +system.physmem.bytes_written::total 10816 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30432 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory +system.physmem.num_writes::total 169 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 986113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28521659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29507773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 986113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 986113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 986113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28521659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29671640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30434 # Total number of read requests seen +system.physmem.writeReqs 169 # Total number of write requests seen +system.physmem.cpureqs 30604 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1947648 # Total number of bytes read from memory +system.physmem.bytesWritten 10816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1947648 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 2031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1870 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1859 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1827 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1881 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1910 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1876 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1972 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1932 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1891 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 93 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 11 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 9 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65982843000 # Total gap between requests +system.physmem.totGap 66004558000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30444 # Categorize read packet sizes +system.physmem.readPktSize::6 30434 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 174 # categorize write packet sizes +system.physmem.writePktSize::6 169 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 1 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 29860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 405 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -146,11 +146,11 @@ system.physmem.wrQLenPdf::4 8 # Wh system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see @@ -171,161 +171,160 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 10445857 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests -system.physmem.totBusLat 121544000 # Total cycles spent in databus access -system.physmem.totBankLat 439614000 # Total cycles spent in bank access -system.physmem.avgQLat 343.77 # Average queueing delay per request -system.physmem.avgBankLat 14467.65 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18811.42 # Average memory access latency -system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.17 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.19 # Data bus utilization in percentage +system.physmem.totQLat 12335337 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 610214087 # Sum of mem lat for all requests +system.physmem.totBusLat 151870000 # Total cycles spent in databus access +system.physmem.totBankLat 446008750 # Total cycles spent in bank access +system.physmem.avgQLat 406.11 # Average queueing delay per request +system.physmem.avgBankLat 14683.90 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 20090.01 # Average memory access latency +system.physmem.avgRdBW 29.51 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.24 # Average write queue length over time -system.physmem.readRowHits 29640 # Number of row buffer hits during reads -system.physmem.writeRowHits 45 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes -system.physmem.avgGap 2155034.39 # Average gap between requests -system.cpu.branchPred.lookups 34537566 # Number of BP lookups -system.cpu.branchPred.condPredicted 34537566 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 909846 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24744786 # Number of BTB lookups -system.cpu.branchPred.BTBHits 24642661 # Number of BTB hits +system.physmem.avgWrQLen 1.18 # Average write queue length over time +system.physmem.readRowHits 29113 # Number of row buffer hits during reads +system.physmem.writeRowHits 87 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 51.48 # Row buffer hit rate for writes +system.physmem.avgGap 2156800.25 # Average gap between requests +system.cpu.branchPred.lookups 34551755 # Number of BP lookups +system.cpu.branchPred.condPredicted 34551755 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 910403 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24766802 # Number of BTB lookups +system.cpu.branchPred.BTBHits 24665055 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.587287 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.589180 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 131965726 # number of cpu cycles simulated +system.cpu.numCycles 132009151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed -system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26590977 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 185543024 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34551755 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24665055 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 56499392 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6118358 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43667810 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 138 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25944504 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 189453 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131930197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.484743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326414 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77942049 59.10% 59.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1996023 1.51% 60.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2954192 2.24% 62.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3924230 2.98% 65.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7791327 5.91% 71.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757391 3.61% 75.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2730462 2.07% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1561040 1.18% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28230029 21.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77978275 59.11% 59.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1995894 1.51% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2955143 2.24% 62.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3921314 2.97% 65.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7795304 5.91% 71.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757842 3.61% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2730359 2.07% 77.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1578596 1.20% 78.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28217470 21.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131886743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261716 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.406198 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37433496 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35884188 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44759605 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8645670 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5163784 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 324546222 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 5163784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42999384 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8526748 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9161 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 47575820 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27611846 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 320149985 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 225 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 53569 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25749083 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 361 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 322162823 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 849088667 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 849086832 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1835 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131930197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261738 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.405532 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37427999 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35920173 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44744893 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8665277 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5171855 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 324565548 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5171855 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42969195 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8593654 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9092 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 47590664 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27595737 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 320190802 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 211 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 56984 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25724332 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 322194206 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 849198017 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 849196232 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1785 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42950078 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62353215 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 102529083 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 35255084 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39579305 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5971941 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 315806334 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1679 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 302165189 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115128 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 36987116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 54145851 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131886743 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.291096 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700528 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 42981461 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62356862 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 102568377 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35231338 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39589479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6005074 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 315870239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1674 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 302163622 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115310 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37046058 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 54286160 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1229 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131930197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700150 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24537309 18.60% 18.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23216690 17.60% 36.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25879367 19.62% 55.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25801755 19.56% 75.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18920728 14.35% 89.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8321327 6.31% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4137839 3.14% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 905905 0.69% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 165823 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24515615 18.58% 18.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23292289 17.66% 36.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25896464 19.63% 55.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25797972 19.55% 75.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18916380 14.34% 89.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8292938 6.29% 96.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4139203 3.14% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 915627 0.69% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 163709 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131886743 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131930197 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 38358 1.96% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1830721 93.50% 95.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88976 4.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 38493 1.98% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1820587 93.51% 95.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 87813 4.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31295 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 171151869 56.64% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 171146899 56.64% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued @@ -354,84 +353,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97747173 32.35% 89.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33234817 11.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97755630 32.35% 89.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33229776 11.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 302165189 # Type of FU issued -system.cpu.iq.rate 2.289725 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1958055 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738289800 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 352827074 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 299525455 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 863 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 304091716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 233 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54002404 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 302163622 # Type of FU issued +system.cpu.iq.rate 2.288960 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1946893 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006443 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738319072 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 352950108 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 299522625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 572 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 867 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 304078975 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 53992768 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11749699 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26201 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33919 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3815332 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11788993 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26852 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33996 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3791586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3226 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8521 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3239 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8506 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5163784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1727826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159628 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 315808013 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197001 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 102529083 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 35255084 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 5171855 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1763635 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159728 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 315871913 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 195728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 102568377 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35231338 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3215 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73485 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33919 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 521490 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445155 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 966645 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 300546126 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97278076 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1619063 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3188 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33996 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 522451 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 444817 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 967268 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 300543939 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97286160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1619683 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 130293374 # number of memory reference insts executed -system.cpu.iew.exec_branches 30888175 # Number of branches executed -system.cpu.iew.exec_stores 33015298 # Number of stores executed -system.cpu.iew.exec_rate 2.277456 # Inst execution rate -system.cpu.iew.wb_sent 299954363 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 299525609 # cumulative count of insts written-back -system.cpu.iew.wb_producers 219474385 # num instructions producing a value -system.cpu.iew.wb_consumers 297941322 # num instructions consuming a value +system.cpu.iew.exec_refs 130298049 # number of memory reference insts executed +system.cpu.iew.exec_branches 30887567 # Number of branches executed +system.cpu.iew.exec_stores 33011889 # Number of stores executed +system.cpu.iew.exec_rate 2.276690 # Inst execution rate +system.cpu.iew.wb_sent 299950982 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 299522787 # cumulative count of insts written-back +system.cpu.iew.wb_producers 219513248 # num instructions producing a value +system.cpu.iew.wb_consumers 298024509 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.269723 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736636 # average fanout of values written-back +system.cpu.iew.wb_rate 2.268955 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736561 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 37628513 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 37692291 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 909867 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126722959 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.195281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965844 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 910422 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126758342 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.194668 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965617 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58163271 45.90% 45.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19278050 15.21% 61.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11813019 9.32% 70.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9592484 7.57% 78.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1741744 1.37% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2072615 1.64% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1297671 1.02% 82.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 717994 0.57% 82.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22046111 17.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58200495 45.91% 45.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19281721 15.21% 61.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11800672 9.31% 70.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9590531 7.57% 78.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1751465 1.38% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2073903 1.64% 81.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1296843 1.02% 82.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 720324 0.57% 82.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22042388 17.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126722959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126758342 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,197 +441,197 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22046111 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22042388 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 420497824 # The number of ROB reads -system.cpu.rob.rob_writes 636810847 # The number of ROB writes -system.cpu.timesIdled 13700 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78983 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 420600708 # The number of ROB reads +system.cpu.rob.rob_writes 636946432 # The number of ROB writes +system.cpu.timesIdled 13762 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78954 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.835287 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835287 # CPI: Total CPI of All Threads -system.cpu.ipc 1.197194 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.197194 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 592820364 # number of integer regfile reads -system.cpu.int_regfile_writes 300190131 # number of integer regfile writes -system.cpu.fp_regfile_reads 138 # number of floating regfile reads -system.cpu.fp_regfile_writes 78 # number of floating regfile writes -system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads -system.cpu.icache.replacements 68 # number of replacements -system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use -system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1039 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks. +system.cpu.cpi 0.835562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835562 # CPI: Total CPI of All Threads +system.cpu.ipc 1.196800 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.196800 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 592847791 # number of integer regfile reads +system.cpu.int_regfile_writes 300194164 # number of integer regfile writes +system.cpu.fp_regfile_reads 150 # number of floating regfile reads +system.cpu.fp_regfile_writes 76 # number of floating regfile writes +system.cpu.misc_regfile_reads 192689354 # number of misc regfile reads +system.cpu.icache.replacements 61 # number of replacements +system.cpu.icache.tagsinuse 835.847711 # Cycle average of tags in use +system.cpu.icache.total_refs 25943160 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1033 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25114.385286 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25950700 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25950700 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25950700 # number of overall hits -system.cpu.icache.overall_hits::total 25950700 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses -system.cpu.icache.overall_misses::total 1351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 835.847711 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.408129 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.408129 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25943160 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25943160 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25943160 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25943160 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25943160 # number of overall hits +system.cpu.icache.overall_hits::total 25943160 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1344 # number of overall misses +system.cpu.icache.overall_misses::total 1344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65684000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65684000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65684000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65684000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65684000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65684000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25944504 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25944504 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25944504 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25944504 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25944504 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25944504 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48370.836417 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48370.836417 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48370.836417 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48370.836417 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48872.023810 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48872.023810 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48872.023810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48872.023810 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.600000 # 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number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1040 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1040 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1040 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52081000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 52081000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52081000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 52081000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52081000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 52081000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 488 # number of replacements -system.cpu.l2cache.tagsinuse 20806.359941 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4028768 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30421 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.433779 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 480 # number of replacements +system.cpu.l2cache.tagsinuse 20802.892196 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4028440 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30411 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.466542 # 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number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984511 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000209 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352690 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352690 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980751 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014173 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014656 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980751 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014173 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 41754.582184 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352592 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352592 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984511 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014651 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984511 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014651 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49786.627335 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50455.635492 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49981.171548 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42062.431034 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42062.431034 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42435.549057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42435.549057 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,168 +640,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 174 # number of writebacks -system.cpu.l2cache.writebacks::total 174 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1443 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 169 # number of writebacks +system.cpu.l2cache.writebacks::total 169 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1017 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38000083 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880649 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53880732 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29417 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30434 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29417 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30434 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38011868 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15869892 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53881760 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38000083 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840076044 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 878076127 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 915973896 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38011868 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877962028 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 915973896 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352690 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352592 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352592 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014651 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37376.468043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38057.294964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37574.449093 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29727.315034 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29727.315034 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072071 # number of replacements -system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use -system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341476 # 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Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076191 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.661567 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21154875000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.471954 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40622570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40622570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341456 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341456 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71964026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71964026 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2109058498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33426889498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33426889498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33426889498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33426889498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43248005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43248005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74687757 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74687757 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74687757 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74687757 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060706 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060706 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036468 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036468 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036468 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036468 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.625542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.625542 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21456.198604 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21456.198604 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12272.463580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12272.463580 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32211 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9475 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.399578 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks -system.cpu.dcache.writebacks::total 2066432 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2066104 # number of writebacks +system.cpu.dcache.writebacks::total 2066104 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631384 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631384 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 647536 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647536 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647536 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647536 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994051 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994051 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076195 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076195 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076195 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076195 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987856500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987856500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833812998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833812998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23821669498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23821669498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23821669498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23821669498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027798 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027798 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.727250 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.727250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.369376 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.369376 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index a996ac821..c3d2ef3b8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.199845 # Number of seconds simulated -sim_ticks 199845137000 # Number of ticks simulated -final_tick 199845137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.199960 # Number of seconds simulated +sim_ticks 199959919500 # Number of ticks simulated +final_tick 199959919500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125858 # Simulator instruction rate (inst/s) -host_op_rate 141897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49782690 # Simulator tick rate (ticks/s) -host_mem_usage 271600 # Number of bytes of host memory used -host_seconds 4014.35 # Real time elapsed on the host +host_inst_rate 164124 # Simulator instruction rate (inst/s) +host_op_rate 185039 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64955915 # Simulator tick rate (ticks/s) +host_mem_usage 268876 # Number of bytes of host memory used +host_seconds 3078.39 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9264064 # Number of bytes read from this memory -system.physmem.bytes_read::total 9480896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6248064 # Number of bytes written to this memory -system.physmem.bytes_written::total 6248064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3388 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144751 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148139 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97626 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97626 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1085000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46356214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47441214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1085000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1085000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31264529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31264529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31264529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1085000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46356214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78705743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148141 # Total number of read requests seen -system.physmem.writeReqs 97626 # Total number of write requests seen -system.physmem.cpureqs 245778 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9480896 # Total number of bytes read from memory -system.physmem.bytesWritten 6248064 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9480896 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6248064 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9221 # Track reads on a per bank basis +system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9260800 # Number of bytes read from this memory +system.physmem.bytes_read::total 9477568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6246592 # Number of bytes written to this memory +system.physmem.bytes_written::total 6246592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144700 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148087 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97603 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97603 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1084057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46313281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47397339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1084057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1084057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31239220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31239220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31239220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1084057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46313281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78636559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148088 # Total number of read requests seen +system.physmem.writeReqs 97603 # Total number of write requests seen +system.physmem.cpureqs 247534 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9477568 # Total number of bytes read from memory +system.physmem.bytesWritten 6246592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9477568 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6246592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 77 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 6 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9156 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9245 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9113 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 9691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8950 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9023 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8762 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6376 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5947 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6637 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6064 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5787 # Track writes on a per bank basis +system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9506 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9385 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9094 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9054 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9284 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5987 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6476 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6222 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6195 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5980 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6048 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6101 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 199845120000 # Total gap between requests +system.physmem.numWrRetry 1837 # Number of times wr buffer was full causing retry +system.physmem.totGap 199959894000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148141 # Categorize read packet sizes +system.physmem.readPktSize::6 148088 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 97626 # categorize write packet sizes +system.physmem.writePktSize::6 99440 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11 # categorize neither packet sizes +system.physmem.neitherpktsize::6 6 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,69 +138,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1637260686 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4709936686 # Sum of mem lat for all requests -system.physmem.totBusLat 592324000 # Total cycles spent in databus access -system.physmem.totBankLat 2480352000 # Total cycles spent in bank access -system.physmem.avgQLat 11056.52 # Average queueing delay per request -system.physmem.avgBankLat 16749.97 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31806.49 # Average memory access latency -system.physmem.avgRdBW 47.44 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 31.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.44 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 31.26 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.49 # Data bus utilization in percentage +system.physmem.totQLat 1699469983 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4970281233 # Sum of mem lat for all requests +system.physmem.totBusLat 740055000 # Total cycles spent in databus access +system.physmem.totBankLat 2530756250 # Total cycles spent in bank access +system.physmem.avgQLat 11482.05 # Average queueing delay per request +system.physmem.avgBankLat 17098.43 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 33580.49 # Average memory access latency +system.physmem.avgRdBW 47.40 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 31.24 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.40 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 31.24 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.64 # Average write queue length over time -system.physmem.readRowHits 128534 # Number of row buffer hits during reads -system.physmem.writeRowHits 35160 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.01 # Row buffer hit rate for writes -system.physmem.avgGap 813148.71 # Average gap between requests -system.cpu.branchPred.lookups 182820446 # Number of BP lookups -system.cpu.branchPred.condPredicted 143128871 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7268870 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 92944153 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87230072 # Number of BTB hits +system.physmem.avgWrQLen 8.80 # Average write queue length over time +system.physmem.readRowHits 125322 # Number of row buffer hits during reads +system.physmem.writeRowHits 52822 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.12 # Row buffer hit rate for writes +system.physmem.avgGap 813867.39 # Average gap between requests +system.cpu.branchPred.lookups 182791909 # Number of BP lookups +system.cpu.branchPred.condPredicted 143104920 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7263448 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93100856 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87211306 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.852135 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12684982 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116077 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.674011 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12676660 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116192 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,136 +244,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 399690275 # number of cpu cycles simulated +system.cpu.numCycles 399919840 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119371931 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761680364 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182820446 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99915054 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170174199 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35702256 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75350704 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 616 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119359242 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761526244 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182791909 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99887966 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170136962 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35675847 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75471629 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114527354 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2441016 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 392530086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.176527 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.990721 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114518172 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2437097 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 392580882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.175648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.990337 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222368477 56.65% 56.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14183765 3.61% 60.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22901577 5.83% 66.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22747664 5.80% 71.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20903604 5.33% 77.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11591587 2.95% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13062137 3.33% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11992821 3.06% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52778454 13.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222456572 56.67% 56.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14184957 3.61% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22893267 5.83% 66.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22743461 5.79% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20901253 5.32% 77.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11599327 2.95% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13055185 3.33% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11991563 3.05% 86.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52755297 13.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392530086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457405 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.905676 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129024913 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70885415 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158884550 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6176695 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27558513 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26126183 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76772 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825683046 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296199 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27558513 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135608190 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9588825 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46459719 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158300780 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15014059 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800754331 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1065 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3044118 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8771537 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 204 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954467105 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3501224581 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3501223353 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1228 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 392580882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457071 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.904197 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129017942 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70989640 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158833179 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6202041 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27538080 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26128135 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 77010 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825507648 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295471 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27538080 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135602175 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9653631 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46459749 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158272352 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15054895 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800579867 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1059 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3045560 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8808243 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 238 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954266949 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500439750 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500438390 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288214814 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293021 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293019 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41499614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170286842 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73502565 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28542432 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15757224 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755181384 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775400 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665429696 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1394216 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187494219 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479993782 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797768 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 392530086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.695232 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.736006 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288014658 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292979 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292975 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41576680 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170252258 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73485876 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28570132 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15813364 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755065776 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775319 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665331498 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1369025 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187382058 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479835806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797687 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 392580882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.694763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735550 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 137153831 34.94% 34.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69768231 17.77% 52.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71497423 18.21% 70.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53360624 13.59% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31181551 7.94% 92.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16101363 4.10% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8735003 2.23% 98.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2914770 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1817290 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 137175345 34.94% 34.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69848009 17.79% 52.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71421264 18.19% 70.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53409606 13.60% 84.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31213744 7.95% 92.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16052398 4.09% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8748856 2.23% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2891239 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1820421 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392530086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392580882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 481185 5.01% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6545421 68.20% 73.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2570325 26.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 477908 5.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6514153 68.18% 73.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2562402 26.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447832117 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383268 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447790588 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383397 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 86 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 96 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -399,84 +399,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153411814 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63802408 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153366793 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63790621 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665429696 # Type of FU issued -system.cpu.iq.rate 1.664863 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9596931 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1734380418 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947258082 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646140584 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 274 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665331498 # Type of FU issued +system.cpu.iq.rate 1.663662 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9554463 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014360 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1734167139 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947029128 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646060992 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 675026522 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 105 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8582869 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674885846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 115 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8559648 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44257287 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42197 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 811123 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16642088 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44222703 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810061 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16625399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4090 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19536 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4374 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27558513 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4987467 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372691 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760516980 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1117257 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170286842 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73502565 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286858 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219486 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11052 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 811123 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4340984 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4003792 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8344776 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 656001968 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150122200 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9427728 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27538080 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5027706 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 374233 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760399793 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1113000 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170252258 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73485876 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286777 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218846 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12338 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810061 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4335774 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4000856 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8336630 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655910156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150087379 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9421342 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1560196 # number of nop insts executed -system.cpu.iew.exec_refs 212633148 # number of memory reference insts executed -system.cpu.iew.exec_branches 138504923 # Number of branches executed -system.cpu.iew.exec_stores 62510948 # Number of stores executed -system.cpu.iew.exec_rate 1.641276 # Inst execution rate -system.cpu.iew.wb_sent 651119979 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646140600 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374813030 # num instructions producing a value -system.cpu.iew.wb_consumers 646558310 # num instructions consuming a value +system.cpu.iew.exec_nop 1558698 # number of nop insts executed +system.cpu.iew.exec_refs 212584480 # number of memory reference insts executed +system.cpu.iew.exec_branches 138500041 # Number of branches executed +system.cpu.iew.exec_stores 62497101 # Number of stores executed +system.cpu.iew.exec_rate 1.640104 # Inst execution rate +system.cpu.iew.wb_sent 651032473 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646061008 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374768785 # num instructions producing a value +system.cpu.iew.wb_consumers 646479955 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616603 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579705 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615476 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579707 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189575186 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189458167 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7194795 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 364971573 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.564418 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233675 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7189194 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 365042802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.564113 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233409 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157304822 43.10% 43.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98491978 26.99% 70.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33807803 9.26% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18748044 5.14% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16202992 4.44% 88.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7453577 2.04% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6993904 1.92% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3174450 0.87% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22794003 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157342257 43.10% 43.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98505195 26.98% 70.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33835922 9.27% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18767828 5.14% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16196095 4.44% 88.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7449740 2.04% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6969572 1.91% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3172412 0.87% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22803781 6.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 364971573 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 365042802 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,199 +487,199 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22794003 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22803781 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1102713785 # The number of ROB reads -system.cpu.rob.rob_writes 1548767048 # The number of ROB writes -system.cpu.timesIdled 306858 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7160189 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1102658217 # The number of ROB reads +system.cpu.rob.rob_writes 1548511592 # The number of ROB writes +system.cpu.timesIdled 308911 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7338958 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.791093 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791093 # CPI: Total CPI of All Threads -system.cpu.ipc 1.264073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.264073 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3059184222 # number of integer regfile reads -system.cpu.int_regfile_writes 752090779 # number of integer regfile writes +system.cpu.cpi 0.791548 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.791548 # CPI: Total CPI of All Threads +system.cpu.ipc 1.263347 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.263347 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058721385 # number of integer regfile reads +system.cpu.int_regfile_writes 752002162 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210880028 # number of misc regfile reads +system.cpu.misc_regfile_reads 210835812 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.icache.replacements 15058 # number of replacements -system.cpu.icache.tagsinuse 1101.681539 # Cycle average of tags in use -system.cpu.icache.total_refs 114506253 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16915 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6769.509489 # Average number of references to valid blocks. +system.cpu.icache.replacements 15017 # number of replacements +system.cpu.icache.tagsinuse 1100.275071 # Cycle average of tags in use +system.cpu.icache.total_refs 114497128 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16875 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6785.014993 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.681539 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537930 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537930 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114506253 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114506253 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114506253 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114506253 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114506253 # number of overall hits -system.cpu.icache.overall_hits::total 114506253 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21101 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21101 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21101 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21101 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21101 # number of overall misses -system.cpu.icache.overall_misses::total 21101 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 452371500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 452371500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 452371500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 452371500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 452371500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 452371500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114527354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114527354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114527354 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114527354 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114527354 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114527354 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1100.275071 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537244 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537244 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114497128 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114497128 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114497128 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114497128 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114497128 # number of overall hits +system.cpu.icache.overall_hits::total 114497128 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21044 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21044 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21044 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21044 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21044 # number of overall misses +system.cpu.icache.overall_misses::total 21044 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 498168000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 498168000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 498168000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 498168000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 498168000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 498168000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114518172 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114518172 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114518172 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114518172 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114518172 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114518172 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21438.391545 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21438.391545 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21438.391545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21438.391545 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23672.685801 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23672.685801 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23672.685801 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23672.685801 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 35.700000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38.100000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4104 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4104 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4104 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4104 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4104 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4104 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16997 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16997 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16997 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16997 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16997 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16997 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 339326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 339326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339326500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 339326500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4078 # 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mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19963.905395 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19963.905395 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21831.339149 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21831.339149 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115392 # number of replacements -system.cpu.l2cache.tagsinuse 27104.061391 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1781385 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146645 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.147601 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 100645092000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23030.603679 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 365.807656 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3707.650056 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.702838 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011164 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.113149 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.827150 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13507 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804164 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817671 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1110730 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1110730 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 70 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 70 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247532 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290408 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122016 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122016 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51828.516529 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54312.306076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54132.454423 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39138.165234 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39138.165234 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192376 # number of replacements -system.cpu.dcache.tagsinuse 4058.257289 # Cycle average of tags in use -system.cpu.dcache.total_refs 190193687 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196472 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.962088 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4128824000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.257289 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990785 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990785 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136223717 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136223717 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50992367 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50992367 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488803 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488803 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1192712 # number of replacements +system.cpu.dcache.tagsinuse 4058.214665 # Cycle average of tags in use +system.cpu.dcache.total_refs 190183804 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196808 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.909202 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4058.214665 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990775 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990775 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136214217 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136214217 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50991947 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50991947 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488812 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488812 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187216084 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187216084 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187216084 # number of overall hits -system.cpu.dcache.overall_hits::total 187216084 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1697690 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1697690 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3246939 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3246939 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4944629 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4944629 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4944629 # number of overall misses -system.cpu.dcache.overall_misses::total 4944629 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26054770000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26054770000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58807860452 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58807860452 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 537000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 537000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84862630452 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84862630452 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84862630452 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84862630452 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137921407 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137921407 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187206164 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187206164 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187206164 # number of overall hits +system.cpu.dcache.overall_hits::total 187206164 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1696297 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1696297 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3247359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3247359 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4943656 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4943656 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4943656 # number of overall misses +system.cpu.dcache.overall_misses::total 4943656 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26545297500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26545297500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57237294950 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57237294950 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 659000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 659000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83782592450 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83782592450 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83782592450 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83782592450 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137910514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137910514 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488838 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488838 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488853 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488853 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192160713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192160713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192160713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192160713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012309 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012309 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059863 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059863 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025732 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025732 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025732 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025732 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15347.189416 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15347.189416 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18111.784808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18111.784808 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15342.857143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15342.857143 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17162.588023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17162.588023 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16266 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14829 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1654 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 595 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.834341 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24.922689 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192149820 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192149820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192149820 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192149820 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012300 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012300 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059871 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059871 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15648.968017 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15648.968017 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17625.798364 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17625.798364 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16073.170732 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16073.170732 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16947.496438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16947.496438 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18139 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17902 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1666 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 610 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.887755 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 29.347541 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110730 # number of writebacks -system.cpu.dcache.writebacks::total 1110730 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 849485 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 849485 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898590 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2898590 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3748075 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3748075 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3748075 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3748075 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848205 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348349 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348349 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196554 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196554 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196554 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196554 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11474356500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11474356500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8274514996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8274514996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19748871496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19748871496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19748871496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19748871496 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13527.810494 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13527.810494 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23753.520165 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23753.520165 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1111113 # number of writebacks +system.cpu.dcache.writebacks::total 1111113 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847762 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 847762 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898994 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2898994 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3746756 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3746756 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3746756 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3746756 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848535 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848535 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348365 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348365 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196900 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196900 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196900 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196900 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11831456500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11831456500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8103165495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8103165495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19934621995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19934621995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19934621995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19934621995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.392435 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.392435 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23260.561466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23260.561466 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 2768ee697..f32034add 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434475 # Number of seconds simulated -sim_ticks 434474519000 # Number of ticks simulated -final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434532 # Number of seconds simulated +sim_ticks 434531908500 # Number of ticks simulated +final_tick 434531908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63257 # Simulator instruction rate (inst/s) -host_op_rate 116969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33237666 # Simulator tick rate (ticks/s) -host_mem_usage 473612 # Number of bytes of host memory used -host_seconds 13071.75 # Real time elapsed on the host +host_inst_rate 91853 # Simulator instruction rate (inst/s) +host_op_rate 169847 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48269802 # Simulator tick rate (ticks/s) +host_mem_usage 425632 # Number of bytes of host memory used +host_seconds 9002.15 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24478784 # Number of bytes read from this memory -system.physmem.bytes_read::total 24687552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 208768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 208768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18796800 # Number of bytes written to this memory -system.physmem.bytes_written::total 18796800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382481 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385743 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293700 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293700 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 480507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56341127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56821634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43263297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43263297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43263297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56341127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100084930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385745 # Total number of read requests seen -system.physmem.writeReqs 293700 # Total number of write requests seen -system.physmem.cpureqs 892876 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24687552 # Total number of bytes read from memory -system.physmem.bytesWritten 18796800 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24687552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18796800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 153 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 213431 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24700 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 23020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 25312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24893 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 23866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23594 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 23428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 24149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24148 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 19119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18933 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18994 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 19037 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 17461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 17937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 17747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18446 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 18298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18336 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24475072 # Number of bytes read from this memory +system.physmem.bytes_read::total 24681728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18793472 # Number of bytes written to this memory +system.physmem.bytes_written::total 18793472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382423 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385652 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293648 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 475583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56325143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56800726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 475583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 475583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43249924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43249924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43249924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 475583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56325143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100050650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385654 # Total number of read requests seen +system.physmem.writeReqs 293648 # Total number of write requests seen +system.physmem.cpureqs 897087 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24681728 # Total number of bytes read from memory +system.physmem.bytesWritten 18793472 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24681728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18793472 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 151 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 214401 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24649 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23427 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23990 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17780 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18330 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17563 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18009 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18307 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18746 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18443 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 17877 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18109 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 434474502000 # Total gap between requests +system.physmem.numWrRetry 3384 # Number of times wr buffer was full causing retry +system.physmem.totGap 434531891500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385745 # Categorize read packet sizes +system.physmem.readPktSize::6 385654 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 293700 # categorize write packet sizes +system.physmem.writePktSize::6 297032 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes +system.physmem.neitherpktsize::6 214401 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,195 +138,194 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 30 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3519643685 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11592955685 # Sum of mem lat for all requests -system.physmem.totBusLat 1542368000 # Total cycles spent in databus access -system.physmem.totBankLat 6530944000 # Total cycles spent in bank access -system.physmem.avgQLat 9127.90 # Average queueing delay per request -system.physmem.avgBankLat 16937.45 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30065.34 # Average memory access latency -system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.63 # Data bus utilization in percentage +system.physmem.totQLat 3414434563 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12002683313 # Sum of mem lat for all requests +system.physmem.totBusLat 1927515000 # Total cycles spent in databus access +system.physmem.totBankLat 6660733750 # Total cycles spent in bank access +system.physmem.avgQLat 8857.09 # Average queueing delay per request +system.physmem.avgBankLat 17278.03 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 31135.12 # Average memory access latency +system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.78 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.43 # Average write queue length over time -system.physmem.readRowHits 340663 # Number of row buffer hits during reads -system.physmem.writeRowHits 151214 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 51.49 # Row buffer hit rate for writes -system.physmem.avgGap 639455.00 # Average gap between requests -system.cpu.branchPred.lookups 215014033 # Number of BP lookups -system.cpu.branchPred.condPredicted 215014033 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13139181 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150598539 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147901505 # Number of BTB hits +system.physmem.avgWrQLen 9.81 # Average write queue length over time +system.physmem.readRowHits 331850 # Number of row buffer hits during reads +system.physmem.writeRowHits 191739 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.30 # Row buffer hit rate for writes +system.physmem.avgGap 639674.09 # Average gap between requests +system.cpu.branchPred.lookups 214985170 # Number of BP lookups +system.cpu.branchPred.condPredicted 214985170 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13134974 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 150557498 # Number of BTB lookups +system.cpu.branchPred.BTBHits 147831953 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.209123 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.189698 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 868949039 # number of cpu cycles simulated +system.cpu.numCycles 869063818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed -system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 232782979 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173495457 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3828584 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 855065277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180571756 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193203975 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214985170 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147831953 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371215101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83387755 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231673075 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 322843 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173439567 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3823649 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 853812868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389323 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 488192536 57.09% 57.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18484631 2.16% 68.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24605565 2.88% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30659669 3.59% 75.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28862609 3.38% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183354461 21.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 486992667 57.04% 57.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24704335 2.89% 59.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27327411 3.20% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28832283 3.38% 66.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18475468 2.16% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24603692 2.88% 71.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30623589 3.59% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28857730 3.38% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183395693 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 855065277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 236982267 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 189423372 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270449085 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55242479 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2120157955 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31600 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21404699 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 100960761 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 90 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216593007 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5356094891 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5355960834 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 134057 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 853812868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247376 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372976 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237064473 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 188186572 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313399146 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45165837 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69996840 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2166788008 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 69996840 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270473923 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 53975472 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17892 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322682449 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136666292 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2119871980 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 32012 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21236600 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101165935 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 102 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216234467 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5355317387 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5355179179 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 138208 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602552155 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1359 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330141203 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512720290 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204905378 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196472643 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55515054 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2034068735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808313369 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 844321 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 855065277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602193615 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 330022122 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512693840 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204894369 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196280742 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55580246 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2033860002 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23240 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808188122 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 845695 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499369913 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 817987835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22688 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 853812868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.117780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887735 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 234637728 27.44% 27.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145403732 17.00% 44.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138360216 16.18% 60.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132907885 15.54% 76.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58823757 6.88% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34984722 4.09% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233534658 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145245329 17.01% 44.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138299025 16.20% 60.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133036648 15.58% 76.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 95993641 11.24% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58825628 6.89% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34908775 4.09% 98.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12073867 1.41% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1895297 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 855065277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 853812868 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7763763 50.73% 83.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2595950 16.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4968961 32.44% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7761394 50.67% 83.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2587769 16.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718674 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190900507 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2719358 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190817504 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued @@ -355,84 +354,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438963543 24.27% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175730645 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438925166 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175726094 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808313369 # Type of FU issued -system.cpu.iq.rate 2.081035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4487818749 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43013 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5176 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820889036 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10538 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170573463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1808188122 # Type of FU issued +system.cpu.iq.rate 2.080616 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15318124 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008472 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4486330411 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2533466617 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768665835 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22520 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43644 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4990 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820776414 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10474 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170620885 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128618134 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 471778 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 270529 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55745634 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128591684 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 469733 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 268884 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55734548 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12450 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 553 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12443 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 683 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70029976 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17665795 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2858627 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2034091928 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2374153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512720290 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204905820 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6054 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1808225 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 77432 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 270529 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9117470 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4488132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13605602 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780566222 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431424657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27747147 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69996840 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16364844 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2884009 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2033883242 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2403682 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512693840 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204894734 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6182 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1820537 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 77063 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 268884 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9113160 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4488782 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13601942 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780436006 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431388742 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27752116 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602146985 # number of memory reference insts executed -system.cpu.iew.exec_branches 169282711 # Number of branches executed -system.cpu.iew.exec_stores 170722328 # Number of stores executed -system.cpu.iew.exec_rate 2.049103 # Inst execution rate -system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341647639 # num instructions producing a value -system.cpu.iew.wb_consumers 1964496615 # num instructions consuming a value +system.cpu.iew.exec_refs 602101798 # number of memory reference insts executed +system.cpu.iew.exec_branches 169273677 # Number of branches executed +system.cpu.iew.exec_stores 170713056 # Number of stores executed +system.cpu.iew.exec_rate 2.048683 # Inst execution rate +system.cpu.iew.wb_sent 1775376016 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768670825 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341566013 # num instructions producing a value +system.cpu.iew.wb_consumers 1964312147 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035145 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682970 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 504930562 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 785035301 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13167809 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 783816028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.950698 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458733 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 291749780 37.16% 37.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195656650 24.92% 62.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62029975 7.90% 69.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25075017 3.19% 84.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10844977 1.38% 91.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290605318 37.08% 37.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195507197 24.94% 62.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61957017 7.90% 69.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92299201 11.78% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25131164 3.21% 84.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28287004 3.61% 88.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9364104 1.19% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10794618 1.38% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69870405 8.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 785035301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 783816028 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -443,203 +442,203 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69870405 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2749272924 # The number of ROB reads -system.cpu.rob.rob_writes 4138465929 # The number of ROB writes -system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13883762 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2747864885 # The number of ROB reads +system.cpu.rob.rob_writes 4138016116 # The number of ROB writes +system.cpu.timesIdled 327647 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15250950 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.050881 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.050881 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951583 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951583 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357585069 # number of integer regfile reads -system.cpu.int_regfile_writes 1848487641 # number of integer regfile writes -system.cpu.fp_regfile_reads 5173 # number of floating regfile reads +system.cpu.cpi 1.051019 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051019 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951457 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951457 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357381544 # number of integer regfile reads +system.cpu.int_regfile_writes 1848396157 # number of integer regfile writes +system.cpu.fp_regfile_reads 4985 # number of floating regfile reads system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads -system.cpu.icache.replacements 5393 # number of replacements -system.cpu.icache.tagsinuse 1034.711169 # Cycle average of tags in use -system.cpu.icache.total_refs 173255660 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24803.959914 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 980232069 # number of misc regfile reads +system.cpu.icache.replacements 5428 # number of replacements +system.cpu.icache.tagsinuse 1035.426880 # Cycle average of tags in use +system.cpu.icache.total_refs 173198733 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7017 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24682.732364 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.711169 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505230 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173271214 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173271214 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173271214 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173271214 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173271214 # number of overall hits -system.cpu.icache.overall_hits::total 173271214 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 224243 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 224243 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 224243 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 224243 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 224243 # number of overall misses -system.cpu.icache.overall_misses::total 224243 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1406797999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1406797999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1406797999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1406797999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1406797999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1406797999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173495457 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173495457 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173495457 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173495457 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173495457 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173495457 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001293 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001293 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001293 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001293 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001293 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001293 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6273.542536 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6273.542536 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6273.542536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6273.542536 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1035.426880 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505580 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505580 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173214256 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173214256 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173214256 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173214256 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173214256 # number of overall hits +system.cpu.icache.overall_hits::total 173214256 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 225311 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 225311 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 225311 # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.815974 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256525921 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256525921 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148156323 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148156323 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404682244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404682244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404682244 # number of overall hits +system.cpu.dcache.overall_hits::total 404682244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2897766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2897766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1003879 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1003879 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3901645 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3901645 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3901645 # number of overall misses +system.cpu.dcache.overall_misses::total 3901645 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51407808000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51407808000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23879895000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23879895000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75287703000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75287703000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75287703000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75287703000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259423687 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259423687 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17316.051222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17316.051222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.477478 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.477478 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19132.497885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19132.497885 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 408583889 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408583889 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408583889 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408583889 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011170 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011170 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006730 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006730 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009549 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009549 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009549 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009549 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17740.496645 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17740.496645 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23787.622811 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23787.622811 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19296.400108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19296.400108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6861 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 663 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.348416 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks -system.cpu.dcache.writebacks::total 2331225 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198810500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49198810500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198810500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49198810500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.158497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.158497 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.506223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.506223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331178 # number of writebacks +system.cpu.dcache.writebacks::total 2331178 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1135254 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1135254 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16862 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16862 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1152116 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1152116 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1152116 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1152116 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762512 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987017 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 987017 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2749529 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2749529 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2749529 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2749529 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27769073500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27769073500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21705384500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21705384500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49474458000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49474458000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49474458000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49474458000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006729 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006729 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15755.395424 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15755.395424 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21990.892254 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21990.892254 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 7980de17a..6c858f4a6 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139847 # Number of seconds simulated -sim_ticks 139846906500 # Number of ticks simulated -final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139855 # Number of seconds simulated +sim_ticks 139855372500 # Number of ticks simulated +final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94955 # Simulator instruction rate (inst/s) -host_op_rate 94955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33309069 # Simulator tick rate (ticks/s) -host_mem_usage 278532 # Number of bytes of host memory used -host_seconds 4198.46 # Real time elapsed on the host +host_inst_rate 164436 # Simulator instruction rate (inst/s) +host_op_rate 164436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57685897 # Simulator tick rate (ticks/s) +host_mem_usage 230388 # Number of bytes of host memory used +host_seconds 2424.43 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1816276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3353407 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 468992 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 466 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 509 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139846854500 # Total gap between requests +system.physmem.totGap 139855320500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 230 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39390791 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests -system.physmem.totBusLat 29312000 # Total cycles spent in databus access -system.physmem.totBankLat 105924000 # Total cycles spent in bank access -system.physmem.avgQLat 5375.38 # Average queueing delay per request -system.physmem.avgBankLat 14454.69 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23830.08 # Average memory access latency +system.physmem.totQLat 47661305 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 197340055 # Sum of mem lat for all requests +system.physmem.totBusLat 36640000 # Total cycles spent in databus access +system.physmem.totBankLat 113038750 # Total cycles spent in bank access +system.physmem.avgQLat 6504.00 # Average queueing delay per request +system.physmem.avgBankLat 15425.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26929.59 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6444 # Number of row buffer hits during reads +system.physmem.readRowHits 6132 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19083904.82 # Average gap between requests -system.cpu.branchPred.lookups 53489670 # Number of BP lookups -system.cpu.branchPred.condPredicted 30685393 # Number of conditional branches predicted +system.physmem.avgGap 19085060.11 # Average gap between requests +system.cpu.branchPred.lookups 53489671 # Number of BP lookups +system.cpu.branchPred.condPredicted 30685392 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754613 # DTB read hits +system.cpu.dtb.read_hits 94754610 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754634 # DTB read accesses -system.cpu.dtb.write_hits 73521103 # DTB write hits +system.cpu.dtb.read_accesses 94754631 # DTB read accesses +system.cpu.dtb.write_hits 73521101 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521138 # DTB write accesses -system.cpu.dtb.data_hits 168275716 # DTB hits +system.cpu.dtb.write_accesses 73521136 # DTB write accesses +system.cpu.dtb.data_hits 168275711 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275772 # DTB accesses -system.cpu.itb.fetch_hits 48611354 # ITB hits +system.cpu.dtb.data_accesses 168275767 # DTB accesses +system.cpu.itb.fetch_hits 48611339 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655874 # ITB accesses +system.cpu.itb.fetch_accesses 48655859 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279693814 # number of cpu cycles simulated +system.cpu.numCycles 279710746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 280386586 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722445 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484559 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400729 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400786 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13387179 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306635 # Number of cycles cpu stages are processed. -system.cpu.activity 95.213631 # Percentage of cycles cpu is active +system.cpu.timesIdled 7707 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13404116 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306630 # Number of cycles cpu stages are processed. +system.cpu.activity 95.207865 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -266,124 +266,124 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701577 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701619 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701577 # CPI: Total CPI of All Threads -system.cpu.ipc 1.425361 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701619 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425275 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.425361 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 77946120 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747694 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.131625 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107042067 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651747 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.728840 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102478598 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215216 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.360435 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 180949238 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.425275 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 77963056 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747690 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.127257 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107059011 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651735 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.725099 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102495582 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215164 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.356581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 180966170 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.304526 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90225845 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467969 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.741208 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 35.302389 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90242832 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467914 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.737088 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.tagsinuse 1831.257835 # Cycle average of tags in use -system.cpu.icache.total_refs 48606847 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1831.214739 # Cycle average of tags in use +system.cpu.icache.total_refs 48606831 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12453.714322 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12453.710223 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.257835 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894169 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894169 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606847 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606847 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606847 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606847 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606847 # number of overall hits -system.cpu.icache.overall_hits::total 48606847 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4507 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4507 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4507 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4507 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4507 # number of overall misses -system.cpu.icache.overall_misses::total 4507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 195448500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 195448500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 195448500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 195448500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 195448500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 195448500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611354 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611354 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611354 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611354 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1831.214739 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894148 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894148 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606831 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606831 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606831 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606831 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606831 # number of overall hits +system.cpu.icache.overall_hits::total 48606831 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses +system.cpu.icache.overall_misses::total 4508 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 205410000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 205410000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 205410000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 205410000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 205410000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 205410000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611339 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611339 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611339 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611339 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43365.542489 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43365.542489 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43365.542489 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43365.542489 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45565.661047 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45565.661047 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45565.661047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45565.661047 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 206 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 605 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 605 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 605 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 605 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 605 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 605 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170297500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170297500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170297500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170297500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170297500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170297500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179905000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 179905000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179905000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 179905000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179905000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 179905000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43632.462209 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43632.462209 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46094.030233 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46094.030233 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3907.773744 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3907.659379 # Cycle average of tags in use system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.670185 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2909.388487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.715072 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.655862 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2909.305713 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.697804 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088787 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088785 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119256 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119252 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -408,17 +408,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160908500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45014500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 205923000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151967500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 151967500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 160908500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 196982000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 357890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 160908500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 196982000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 357890500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 170516000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45771500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 216287500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 159323000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 159323000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 170516000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 205094500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 375610500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 170516000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 205094500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 375610500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -443,17 +443,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47903.691575 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54629.247573 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49228.544107 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48320.349762 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48320.349762 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48838.769105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48838.769105 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50763.917833 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55547.936893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51706.311260 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50659.141494 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50659.141494 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51256.891376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51256.891376 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118404553 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34670717 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153075270 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112966799 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112966799 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118404553 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147637516 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 266042069 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118404553 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147637516 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 266042069 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128897344 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549956 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164447300 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120759327 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120759327 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128897344 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156309283 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 285206627 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128897344 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156309283 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 285206627 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -495,51 +495,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35249.941352 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42076.112864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.613913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35919.490938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35919.490938 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38373.725514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43143.150485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39313.244083 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38397.242289 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38397.242289 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3285.615449 # Cycle average of tags in use -system.cpu.dcache.total_refs 168254423 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use +system.cpu.dcache.total_refs 168254397 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40523.704961 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40523.698699 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3285.615449 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802152 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802152 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501238 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501238 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254423 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254423 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254423 # number of overall hits -system.cpu.dcache.overall_hits::total 168254423 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19491 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19491 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20795 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20795 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20795 # number of overall misses -system.cpu.dcache.overall_misses::total 20795 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64310000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64310000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 715525500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 715525500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 779835500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 779835500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 779835500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 779835500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 3285.521075 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802129 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802129 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753186 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753186 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501211 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501211 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254397 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254397 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254397 # number of overall hits +system.cpu.dcache.overall_hits::total 168254397 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1303 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1303 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19518 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19518 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20821 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20821 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20821 # number of overall misses +system.cpu.dcache.overall_misses::total 20821 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65740000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65740000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 753340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 753340000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 819080000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 819080000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 819080000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 819080000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -556,32 +556,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49317.484663 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49317.484663 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36710.558719 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36710.558719 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37501.106035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37501.106035 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16708 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50452.801228 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50452.801228 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38597.192335 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38597.192335 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39339.128764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39339.128764 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18390 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 537 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.245810 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 353 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 353 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16316 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16316 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16669 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16669 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16669 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16669 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -590,14 +590,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48200500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48200500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163094000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 163094000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211294500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211294500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211294500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211294500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -606,14 +606,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50737.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50737.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50935.040600 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50935.040600 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 078219244..f63466b63 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077336 # Number of seconds simulated -sim_ticks 77336466500 # Number of ticks simulated -final_tick 77336466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077334 # Number of seconds simulated +sim_ticks 77333663500 # Number of ticks simulated +final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141610 # Simulator instruction rate (inst/s) -host_op_rate 141610 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29159685 # Simulator tick rate (ticks/s) -host_mem_usage 279556 # Number of bytes of host memory used -host_seconds 2652.17 # Real time elapsed on the host +host_inst_rate 196388 # Simulator instruction rate (inst/s) +host_op_rate 196388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40437661 # Simulator tick rate (ticks/s) +host_mem_usage 232448 # Number of bytes of host memory used +host_seconds 1912.42 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory -system.physmem.bytes_read::total 476288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2855057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3303590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6158647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2855057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2855057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2855057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3303590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6158647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7442 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255552 # Number of bytes read from this memory +system.physmem.bytes_read::total 476672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3993 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7448 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2859298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3304538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6163836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2859298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2859298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2859298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3304538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6163836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7448 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 476288 # Total number of bytes read from memory +system.physmem.cpureqs 7448 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476672 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476672 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 386 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 545 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 462 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 590 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 518 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 519 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77336398000 # Total gap between requests +system.physmem.totGap 77333595000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7442 # Categorize read packet sizes +system.physmem.readPktSize::6 7448 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40921923 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 178783923 # Sum of mem lat for all requests -system.physmem.totBusLat 29768000 # Total cycles spent in databus access -system.physmem.totBankLat 108094000 # Total cycles spent in bank access -system.physmem.avgQLat 5498.78 # Average queueing delay per request -system.physmem.avgBankLat 14524.86 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24023.64 # Average memory access latency +system.physmem.totQLat 53873160 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 207011910 # Sum of mem lat for all requests +system.physmem.totBusLat 37240000 # Total cycles spent in databus access +system.physmem.totBankLat 115898750 # Total cycles spent in bank access +system.physmem.avgQLat 7233.24 # Average queueing delay per request +system.physmem.avgBankLat 15561.06 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27794.30 # Average memory access latency system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6502 # Number of row buffer hits during reads +system.physmem.readRowHits 6188 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.37 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10391883.63 # Average gap between requests -system.cpu.branchPred.lookups 50254079 # Number of BP lookups -system.cpu.branchPred.condPredicted 29238788 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1202354 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26185724 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23237791 # Number of BTB hits +system.physmem.avgGap 10383135.74 # Average gap between requests +system.cpu.branchPred.lookups 50250166 # Number of BP lookups +system.cpu.branchPred.condPredicted 29237479 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1200857 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25926395 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23227731 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.742213 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9009650 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1041 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.591056 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9011908 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1071 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101791760 # DTB read hits -system.cpu.dtb.read_misses 77689 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 101869449 # DTB read accesses -system.cpu.dtb.write_hits 78414713 # DTB write hits -system.cpu.dtb.write_misses 1485 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78416198 # DTB write accesses -system.cpu.dtb.data_hits 180206473 # DTB hits -system.cpu.dtb.data_misses 79174 # DTB misses -system.cpu.dtb.data_acv 48607 # DTB access violations -system.cpu.dtb.data_accesses 180285647 # DTB accesses -system.cpu.itb.fetch_hits 50234226 # ITB hits -system.cpu.itb.fetch_misses 374 # ITB misses +system.cpu.dtb.read_hits 101791406 # DTB read hits +system.cpu.dtb.read_misses 78057 # DTB read misses +system.cpu.dtb.read_acv 48605 # DTB read access violations +system.cpu.dtb.read_accesses 101869463 # DTB read accesses +system.cpu.dtb.write_hits 78427886 # DTB write hits +system.cpu.dtb.write_misses 1487 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 78429373 # DTB write accesses +system.cpu.dtb.data_hits 180219292 # DTB hits +system.cpu.dtb.data_misses 79544 # DTB misses +system.cpu.dtb.data_acv 48609 # DTB access violations +system.cpu.dtb.data_accesses 180298836 # DTB accesses +system.cpu.itb.fetch_hits 50219857 # ITB hits +system.cpu.itb.fetch_misses 371 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50234600 # ITB accesses +system.cpu.itb.fetch_accesses 50220228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,238 +227,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 154672935 # number of cpu cycles simulated +system.cpu.numCycles 154667329 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51121474 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448760218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50254079 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32247441 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78789768 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6120508 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19691338 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 51106120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19721587 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9175 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50234226 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 409224 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154491833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.904750 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75702065 49.00% 49.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4283300 2.77% 51.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6877325 4.45% 56.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5367764 3.47% 59.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11752749 7.61% 67.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7805511 5.05% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5606089 3.63% 75.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1832349 1.19% 77.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35264681 22.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75708532 49.01% 49.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11737510 7.60% 67.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7816086 5.06% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5610591 3.63% 75.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1829118 1.18% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35257809 22.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154491833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324905 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.901349 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56470400 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15041439 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74166392 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3937938 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4875664 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9475904 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4278 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 444843868 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12237 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4875664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59604786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4871643 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 401502 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75064420 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9673818 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440376827 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19255 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7994088 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287328410 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 578957076 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306311574 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272645502 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56459553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15066363 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9471001 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4302 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59590768 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4877628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9691222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440325296 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8008636 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272621523 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27796081 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36810 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27798585 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104665260 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80564409 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8907082 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6393839 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408148309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401749536 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 973581 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32442077 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15221672 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 73 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154491833 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.600458 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27858963 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408090088 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 966818 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32383170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154473509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28272588 18.30% 18.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25828142 16.72% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25544882 16.53% 51.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24283906 15.72% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21283015 13.78% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15483551 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8467826 5.48% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4000243 2.59% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1327680 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28241568 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25850506 16.73% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25557985 16.55% 51.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24263587 15.71% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21289313 13.78% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8473783 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154491833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154473509 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34079 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57868 0.49% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5831 0.05% 0.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5354 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1930027 16.34% 17.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1748928 14.81% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5061323 42.85% 74.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2967669 25.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 56920 0.48% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5994 0.05% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5359 0.05% 0.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1948290 16.45% 17.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748478 14.77% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5072339 42.83% 74.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155748072 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126114 0.53% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32812204 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7499410 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793875 0.70% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556840 4.12% 54.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1578743 0.39% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103369723 25.73% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79230974 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155713729 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7493329 1.87% 49.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2792591 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16555292 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1575667 0.39% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103367731 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401749536 # Type of FU issued -system.cpu.iq.rate 2.597413 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11811079 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029399 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634008068 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260192564 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234721556 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336767497 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180447135 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161345688 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241449037 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172077997 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15060402 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued +system.cpu.iq.rate 2.597191 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11841746 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 633918884 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260111127 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234694704 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241419354 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9910773 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 111367 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49045 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7043680 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9904869 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112431 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48930 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7055780 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2589 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260879 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4875664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2512017 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 367237 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432932337 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125430 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104665260 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80564409 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 288 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 94 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49045 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 948042 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 404840 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1352882 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398223090 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101918095 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3526446 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2513908 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367539 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432875837 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130046 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 95 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48930 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 945508 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101918110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24783740 # number of nop insts executed -system.cpu.iew.exec_refs 180334326 # number of memory reference insts executed -system.cpu.iew.exec_branches 46552042 # Number of branches executed -system.cpu.iew.exec_stores 78416231 # Number of stores executed -system.cpu.iew.exec_rate 2.574614 # Inst execution rate -system.cpu.iew.wb_sent 396695169 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396067244 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193570018 # num instructions producing a value -system.cpu.iew.wb_consumers 271138332 # num instructions consuming a value +system.cpu.iew.exec_nop 24785464 # number of nop insts executed +system.cpu.iew.exec_refs 180347520 # number of memory reference insts executed +system.cpu.iew.exec_branches 46544583 # Number of branches executed +system.cpu.iew.exec_stores 78429410 # Number of stores executed +system.cpu.iew.exec_rate 2.574493 # Inst execution rate +system.cpu.iew.wb_sent 396666494 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396036593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193534236 # num instructions producing a value +system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.560676 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713916 # average fanout of values written-back +system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34296903 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34241397 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1198153 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149616169 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.664582 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.996061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149606522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55282421 36.95% 36.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22517619 15.05% 52.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13057157 8.73% 60.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11465050 7.66% 68.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8178831 5.47% 73.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5460295 3.65% 77.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5171821 3.46% 80.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3274025 2.19% 83.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25208950 16.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55299818 36.96% 36.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22506360 15.04% 52.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13038976 8.72% 60.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8182427 5.47% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5460458 3.65% 77.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3276425 2.19% 83.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25215066 16.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149616169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149606522 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -469,192 +469,192 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25208950 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25215066 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557365728 # The number of ROB reads -system.cpu.rob.rob_writes 870806965 # The number of ROB writes -system.cpu.timesIdled 3403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 181102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557294459 # The number of ROB reads +system.cpu.rob.rob_writes 870687579 # The number of ROB writes +system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 193820 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.411830 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.411830 # CPI: Total CPI of All Threads -system.cpu.ipc 2.428187 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.428187 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398054965 # number of integer regfile reads -system.cpu.int_regfile_writes 170113807 # number of integer regfile writes -system.cpu.fp_regfile_reads 156515246 # number of floating regfile reads -system.cpu.fp_regfile_writes 104037972 # number of floating regfile writes +system.cpu.cpi 0.411815 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.411815 # CPI: Total CPI of All Threads +system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398027050 # number of integer regfile reads +system.cpu.int_regfile_writes 170092718 # number of integer regfile writes +system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads +system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2129 # number of replacements -system.cpu.icache.tagsinuse 1832.082194 # Cycle average of tags in use -system.cpu.icache.total_refs 50228789 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4056 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12383.823718 # Average number of references to valid blocks. +system.cpu.icache.replacements 2144 # number of replacements +system.cpu.icache.tagsinuse 1832.992748 # Cycle average of tags in use +system.cpu.icache.total_refs 50214380 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12334.654876 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1832.082194 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894571 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894571 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50228789 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50228789 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50228789 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50228789 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50228789 # number of overall hits -system.cpu.icache.overall_hits::total 50228789 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5437 # number of overall misses -system.cpu.icache.overall_misses::total 5437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 226400000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 226400000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 226400000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 226400000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 226400000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 226400000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50234226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50234226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50234226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50234226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50234226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50234226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41640.610631 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41640.610631 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41640.610631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41640.610631 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1832.992748 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.895016 # 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miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50615.774240 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59849.012776 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.715477 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.524904 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.524904 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52331.901182 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52331.901182 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,146 +663,146 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3450 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3455 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 861 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4311 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3992 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7442 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 122247748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38514499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 160762247 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112485998 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112485998 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122247748 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151000497 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273248245 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122247748 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151000497 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273248245 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868819 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.854171 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981197 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981197 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903375 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903375 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35434.129855 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44732.286876 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37291.173046 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35926.540402 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35926.540402 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35434.129855 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37825.775802 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36717.044477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35434.129855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37825.775802 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36717.044477 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 4316 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3455 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3993 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7448 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3455 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3993 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7448 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131818904 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40942458 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172761362 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125001233 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125001233 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131818904 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943691 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 297762595 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131818904 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943691 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 297762595 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869697 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981203 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981203 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902460 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902460 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38153.083647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47552.216028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40028.119092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.993934 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.993934 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 780 # number of replacements -system.cpu.dcache.tagsinuse 3297.205890 # Cycle average of tags in use -system.cpu.dcache.total_refs 159967351 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3297.047040 # Cycle average of tags in use +system.cpu.dcache.total_refs 159960718 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38251.399091 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 38249.813008 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.205890 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804982 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804982 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86466482 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86466482 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500862 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 159967344 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 159967344 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 159967344 # number of overall hits -system.cpu.dcache.overall_hits::total 159967344 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19867 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19867 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21677 # number of overall misses -system.cpu.dcache.overall_misses::total 21677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83400000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83400000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 721598130 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 721598130 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 804998130 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 804998130 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 804998130 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 804998130 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86468292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86468292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3297.047040 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86459752 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86459752 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 159960712 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159960712 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159960712 # number of overall hits +system.cpu.dcache.overall_hits::total 159960712 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19769 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21580 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses +system.cpu.dcache.overall_misses::total 21580 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 779488110 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 779488110 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 869475610 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 869475610 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 869475610 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 869475610 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86461563 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86461563 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159989021 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159989021 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159989021 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159989021 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 159982292 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159982292 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159982292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159982292 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46077.348066 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46077.348066 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36321.444103 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36321.444103 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37136.048807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37136.048807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37136.048807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37136.048807 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23923 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39429.819920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39429.819920 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40290.806766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40290.806766 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28165 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.912837 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.635499 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 657 # number of writebacks system.cpu.dcache.writebacks::total 657 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 819 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 819 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16676 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16676 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17495 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17495 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17495 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17495 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 991 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 991 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16577 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16577 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17398 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 990 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 990 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3192 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155023000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 155023000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 206573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206573500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 206573500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53863000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53863000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221119500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 221119500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221119500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 221119500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -811,14 +811,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52018.668012 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52018.668012 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48581.322469 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48581.322469 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54407.070707 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54407.070707 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index cecd350a2..c2e0aed87 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068072 # Number of seconds simulated -sim_ticks 68071881000 # Number of ticks simulated -final_tick 68071881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068358 # Number of seconds simulated +sim_ticks 68358106500 # Number of ticks simulated +final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102151 # Simulator instruction rate (inst/s) -host_op_rate 130595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25467625 # Simulator tick rate (ticks/s) -host_mem_usage 296712 # Number of bytes of host memory used -host_seconds 2672.88 # Real time elapsed on the host +host_inst_rate 148173 # Simulator instruction rate (inst/s) +host_op_rate 189432 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37097000 # Simulator tick rate (ticks/s) +host_mem_usage 250340 # Number of bytes of host memory used +host_seconds 1842.69 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory -system.physmem.bytes_read::total 466240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2846873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4002357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6849230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2846873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2846873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2846873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4002357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6849230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7286 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory +system.physmem.bytes_read::total 465728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193152 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7277 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2825590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3987471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6813062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2825590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2825590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2825590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3987471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6813062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7278 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7288 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 466240 # Total number of bytes read from memory +system.physmem.cpureqs 7280 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 465728 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466240 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 465728 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 504 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 557 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 478 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 546 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 585 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 451 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68071860500 # Total gap between requests +system.physmem.totGap 68358086000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7286 # Categorize read packet sizes +system.physmem.readPktSize::6 7278 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 38841760 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 170087760 # Sum of mem lat for all requests -system.physmem.totBusLat 29144000 # Total cycles spent in databus access -system.physmem.totBankLat 102102000 # Total cycles spent in bank access -system.physmem.avgQLat 5331.01 # Average queueing delay per request -system.physmem.avgBankLat 14013.45 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23344.46 # Average memory access latency -system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 46727256 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests +system.physmem.totBusLat 36390000 # Total cycles spent in databus access +system.physmem.totBankLat 109065000 # Total cycles spent in bank access +system.physmem.avgQLat 6420.34 # Average queueing delay per request +system.physmem.avgBankLat 14985.57 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26405.92 # Average memory access latency +system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6372 # Number of row buffer hits during reads +system.physmem.readRowHits 6070 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9342830.15 # Average gap between requests -system.cpu.branchPred.lookups 41692065 # Number of BP lookups -system.cpu.branchPred.condPredicted 21046025 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1612310 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25558633 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16675018 # Number of BTB hits +system.physmem.avgGap 9392427.32 # Average gap between requests +system.cpu.branchPred.lookups 41732744 # Number of BP lookups +system.cpu.branchPred.condPredicted 21038238 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1652729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26040996 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16764116 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.242214 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6736046 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 7190 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.375863 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6744035 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 7274 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,100 +237,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136143763 # number of cpu cycles simulated +system.cpu.numCycles 136716214 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38720751 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 316654874 # Number of instructions fetch has processed -system.cpu.fetch.Branches 41692065 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23411064 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70618145 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6665842 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21550456 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1364 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 38933938 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317883912 # Number of instructions fetch has processed +system.cpu.fetch.Branches 41732744 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23508151 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70884226 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6817030 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21520624 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1371 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37376595 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 521732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 135933121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.990728 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.456678 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37551869 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 523991 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136493185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.988959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456313 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65940392 48.51% 48.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6730475 4.95% 53.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5637804 4.15% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5998950 4.41% 62.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4879102 3.59% 65.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4141679 3.05% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3188425 2.35% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4149669 3.05% 74.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35266625 25.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66238954 48.53% 48.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6780831 4.97% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5636861 4.13% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6036296 4.42% 62.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4884969 3.58% 65.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4157247 3.05% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3216539 2.36% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4148137 3.04% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35393351 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 135933121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.306236 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325886 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45271721 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16691056 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66469199 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2527476 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4973669 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7265289 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69057 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 400237870 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218381 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4973669 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50782794 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1926905 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 308736 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63418534 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14522483 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 392567341 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 52 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1667501 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10227766 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1022 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 431145358 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2325492453 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1253893551 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1071598902 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136493185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305251 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325137 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45460656 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16697353 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66694244 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2556726 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5084206 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7272433 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69135 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401643990 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 218444 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5084206 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50968262 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1914523 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 308341 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63676495 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14541358 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393775984 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1667283 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10312278 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1126 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432122953 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2331950900 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259654779 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072296121 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46579165 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11899 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11898 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36419091 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103284417 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91190896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4278404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5313371 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 383399978 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22859 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373603209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1225399 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 33612220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 83720105 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 135933121 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.748434 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.022451 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47556760 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11781 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11780 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36361756 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103536184 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91503384 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4302647 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5369286 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384225176 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22747 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374106691 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1237893 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34434852 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 85933398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 627 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136493185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.740845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023746 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24617806 18.11% 18.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19905628 14.64% 32.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20463769 15.05% 47.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18134866 13.34% 61.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 23975475 17.64% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15748338 11.59% 90.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8799560 6.47% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3376937 2.48% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 910742 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24947846 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19979954 14.64% 32.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20599928 15.09% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18110176 13.27% 61.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23967090 17.56% 78.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15779150 11.56% 90.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8840932 6.48% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3358221 2.46% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 909888 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 135933121 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136493185 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9041 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8903 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -349,127 +349,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46127 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46069 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7573 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 401 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 189986 1.07% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6027 0.03% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241589 1.36% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9303270 52.42% 55.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7940124 44.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7541 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 384 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 189821 1.07% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6023 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241770 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9327128 52.38% 55.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7975640 44.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126062452 33.74% 33.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174186 0.58% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6778330 1.81% 36.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126244558 33.75% 33.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174203 0.58% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6782034 1.81% 36.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8468082 2.27% 38.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3426363 0.92% 39.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600385 0.43% 39.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20905129 5.60% 45.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7170133 1.92% 47.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133112 1.91% 49.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101416985 27.15% 76.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88292763 23.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8468832 2.26% 38.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426641 0.92% 39.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600511 0.43% 39.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20905751 5.59% 45.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7170121 1.92% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133236 1.91% 49.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101536664 27.14% 76.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88488853 23.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373603209 # Type of FU issued -system.cpu.iq.rate 2.744182 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17748829 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047507 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 652552700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 286781782 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249670215 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249561067 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130267469 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118091463 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262665125 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128686913 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11143467 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374106691 # Type of FU issued +system.cpu.iq.rate 2.736374 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17807974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047601 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654078451 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288293032 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250000264 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249673983 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130403978 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118157993 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263169120 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128745545 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11104268 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8635669 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 113833 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14304 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8815313 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8887436 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 113793 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14364 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9127801 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 179767 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 171663 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1472 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4973669 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 290169 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 43007 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 383424336 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 947805 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103284417 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91190896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11825 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 376 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14304 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1257323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 355165 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1612488 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 369752091 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100205261 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3851118 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5084206 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 279212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42812 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384249465 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 945099 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103536184 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91503384 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11713 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 308 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14364 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1301821 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 354554 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1656375 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370204175 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100335709 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3902516 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1499 # number of nop insts executed -system.cpu.iew.exec_refs 187415465 # number of memory reference insts executed -system.cpu.iew.exec_branches 38269539 # Number of branches executed -system.cpu.iew.exec_stores 87210204 # Number of stores executed -system.cpu.iew.exec_rate 2.715894 # Inst execution rate -system.cpu.iew.wb_sent 368418252 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 367761678 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182872307 # num instructions producing a value -system.cpu.iew.wb_consumers 363527613 # num instructions consuming a value +system.cpu.iew.exec_nop 1542 # number of nop insts executed +system.cpu.iew.exec_refs 187704225 # number of memory reference insts executed +system.cpu.iew.exec_branches 38278467 # Number of branches executed +system.cpu.iew.exec_stores 87368516 # Number of stores executed +system.cpu.iew.exec_rate 2.707829 # Inst execution rate +system.cpu.iew.wb_sent 368827623 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368158257 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183056844 # num instructions producing a value +system.cpu.iew.wb_consumers 364050324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.701275 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503049 # average fanout of values written-back +system.cpu.iew.wb_rate 2.692865 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502834 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34359338 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35184491 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1543637 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130959452 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.665444 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.660816 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1583973 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131408979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.656326 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.660791 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34245793 26.15% 26.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28403736 21.69% 47.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13297993 10.15% 57.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11400251 8.71% 66.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13789663 10.53% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417902 5.66% 82.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3851196 2.94% 85.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3914096 2.99% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14638822 11.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34626776 26.35% 26.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28501850 21.69% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13315357 10.13% 58.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11364955 8.65% 66.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13794993 10.50% 77.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7395322 5.63% 82.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3829564 2.91% 85.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3937630 3.00% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14642532 11.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130959452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131408979 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -480,198 +480,198 @@ system.cpu.commit.branches 36546710 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14638822 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14642532 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 499742506 # The number of ROB reads -system.cpu.rob.rob_writes 771826211 # The number of ROB writes -system.cpu.timesIdled 6299 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 210642 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501013476 # The number of ROB reads +system.cpu.rob.rob_writes 773587232 # The number of ROB writes +system.cpu.timesIdled 6387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 223029 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.498628 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.498628 # CPI: Total CPI of All Threads -system.cpu.ipc 2.005503 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.005503 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1767787991 # number of integer regfile reads -system.cpu.int_regfile_writes 232574551 # number of integer regfile writes -system.cpu.fp_regfile_reads 188239368 # number of floating regfile reads -system.cpu.fp_regfile_writes 132566541 # number of floating regfile writes -system.cpu.misc_regfile_reads 566998882 # number of misc regfile reads +system.cpu.cpi 0.500725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500725 # CPI: Total CPI of All Threads +system.cpu.ipc 1.997106 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.997106 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769939132 # number of integer regfile reads +system.cpu.int_regfile_writes 232882500 # number of integer regfile writes +system.cpu.fp_regfile_reads 188356577 # number of floating regfile reads +system.cpu.fp_regfile_writes 132592082 # number of floating regfile writes +system.cpu.misc_regfile_reads 567391435 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.icache.replacements 13918 # number of replacements -system.cpu.icache.tagsinuse 1846.260886 # Cycle average of tags in use -system.cpu.icache.total_refs 37359528 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15804 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2363.928626 # Average number of references to valid blocks. +system.cpu.icache.replacements 13893 # number of replacements +system.cpu.icache.tagsinuse 1849.968594 # Cycle average of tags in use +system.cpu.icache.total_refs 37534809 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15782 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2378.330313 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1846.260886 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.901495 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.901495 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37359528 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37359528 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37359528 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37359528 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37359528 # number of overall hits -system.cpu.icache.overall_hits::total 37359528 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17066 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17066 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17066 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17066 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17066 # number of overall misses -system.cpu.icache.overall_misses::total 17066 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 359194498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 359194498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 359194498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 359194498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 359194498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 359194498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37376594 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37376594 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37376594 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37376594 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37376594 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37376594 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21047.374780 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21047.374780 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21047.374780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21047.374780 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 550 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1849.968594 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.903305 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.903305 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37534809 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37534809 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37534809 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37534809 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37534809 # number of overall hits +system.cpu.icache.overall_hits::total 37534809 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17059 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17059 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17059 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17059 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17059 # number of overall misses +system.cpu.icache.overall_misses::total 17059 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 362452498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 362452498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 362452498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 362452498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 362452498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 362452498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37551868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37551868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37551868 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37551868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37551868 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37551868 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000454 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000454 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000454 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21246.995603 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21246.995603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21246.995603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21246.995603 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 477 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.947368 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.058824 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1259 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1259 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1259 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1259 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1259 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1259 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15807 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15807 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15807 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15807 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15807 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15807 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293030998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 293030998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293030998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 293030998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293030998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 293030998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55451199 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 166202287 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2792 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2792 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94361392 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94361392 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110751088 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149812591 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 260563679 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110751088 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149812591 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 260563679 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812918 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993959 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993959 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356894 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356894 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36563.581380 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37980.273288 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37024.345511 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33736.643547 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33736.643547 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1413 # number of replacements -system.cpu.dcache.tagsinuse 3109.588822 # Cycle average of tags in use -system.cpu.dcache.total_refs 170749767 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use +system.cpu.dcache.total_refs 170925187 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37038.995011 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 37077.047072 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3109.588822 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.759177 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.759177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88696383 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88696383 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031533 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031533 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 3109.949983 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.759265 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.759265 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88871803 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88871803 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031525 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031525 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170727916 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170727916 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170727916 # number of overall hits -system.cpu.dcache.overall_hits::total 170727916 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21132 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21132 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170903328 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170903328 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170903328 # number of overall hits +system.cpu.dcache.overall_hits::total 170903328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4023 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4023 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21140 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21140 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25173 # number of overall misses -system.cpu.dcache.overall_misses::total 25173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164980000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164980000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 832721164 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 832721164 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 997701164 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 997701164 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 997701164 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 997701164 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88700424 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88700424 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25163 # number of overall misses +system.cpu.dcache.overall_misses::total 25163 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177641500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177641500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 874574146 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 874574146 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 116000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1052215646 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1052215646 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1052215646 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1052215646 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88875826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88875826 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170753089 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170753089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170753089 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170753089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 170928491 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170928491 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170928491 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170928491 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses @@ -805,52 +805,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40826.528087 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40826.528087 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39405.695817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39405.695817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39633.780797 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39633.780797 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13427 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 430 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.225581 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44156.475267 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44156.475267 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41370.584011 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41370.584011 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41815.985614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41815.985614 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15531 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 796 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 449 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.590200 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.230769 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks -system.cpu.dcache.writebacks::total 1039 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2244 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2244 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18317 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks +system.cpu.dcache.writebacks::total 1043 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2222 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2222 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18329 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18329 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20561 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20561 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20561 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20561 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1797 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1797 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2815 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2815 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20551 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20551 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20551 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20551 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1801 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1801 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2811 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2811 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80314500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 80314500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 132089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 132089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212404000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212404000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87720000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 87720000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 138213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225933500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 225933500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225933500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 225933500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -859,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44693.656093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44693.656093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46923.445826 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46923.445826 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48706.274292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48706.274292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49168.801138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49168.801138 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 8443dfdcb..5cf480155 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.626365 # Number of seconds simulated -sim_ticks 626365181000 # Number of ticks simulated -final_tick 626365181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629815 # Number of seconds simulated +sim_ticks 629814900000 # Number of ticks simulated +final_tick 629814900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114572 # Simulator instruction rate (inst/s) -host_op_rate 114572 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39364843 # Simulator tick rate (ticks/s) -host_mem_usage 295992 # Number of bytes of host memory used -host_seconds 15911.79 # Real time elapsed on the host +host_inst_rate 180734 # Simulator instruction rate (inst/s) +host_op_rate 180734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62438874 # Simulator tick rate (ticks/s) +host_mem_usage 248904 # Number of bytes of host memory used +host_seconds 10086.90 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30294656 # Number of bytes read from this memory -system.physmem.bytes_read::total 30470720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295232 # Number of bytes read from this memory +system.physmem.bytes_read::total 30471488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473354 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473363 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476117 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 281088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48365805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48646893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 281088 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 281088 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6836446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6836446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6836446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 281088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48365805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55483340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476105 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 279854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48101803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48381656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 279854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 279854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6799001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6799001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6799001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 279854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48101803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55180657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476117 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543013 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30470720 # Total number of bytes read from memory +system.physmem.cpureqs 543025 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30471488 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30470720 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30471488 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 93 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 84 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29984 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29806 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29835 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29791 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4199 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4202 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4109 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4160 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 29663 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29817 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29819 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4110 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4171 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4205 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 626365119500 # Total gap between requests +system.physmem.totGap 629814837500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476105 # Categorize read packet sizes +system.physmem.readPktSize::6 476117 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 406602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 406568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2899 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2909 # Wh system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2248288249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 16547544249 # Sum of mem lat for all requests -system.physmem.totBusLat 1904048000 # Total cycles spent in databus access -system.physmem.totBankLat 12395208000 # Total cycles spent in bank access -system.physmem.avgQLat 4723.18 # Average queueing delay per request -system.physmem.avgBankLat 26039.70 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34762.87 # Average memory access latency -system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.totQLat 2509077325 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20518523575 # Sum of mem lat for all requests +system.physmem.totBusLat 2380165000 # Total cycles spent in databus access +system.physmem.totBankLat 15629281250 # Total cycles spent in bank access +system.physmem.avgQLat 5270.81 # Average queueing delay per request +system.physmem.avgBankLat 32832.35 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 43103.15 # Average memory access latency +system.physmem.avgRdBW 48.38 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.80 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time system.physmem.avgWrQLen 11.00 # Average write queue length over time -system.physmem.readRowHits 265467 # Number of row buffer hits during reads -system.physmem.writeRowHits 48790 # Number of row buffer hits during writes -system.physmem.readRowHitRate 55.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.92 # Row buffer hit rate for writes -system.physmem.avgGap 1153499.31 # Average gap between requests -system.cpu.branchPred.lookups 388924238 # Number of BP lookups -system.cpu.branchPred.condPredicted 255857711 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25855826 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 319270007 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258448229 # Number of BTB hits +system.physmem.readRowHits 143855 # Number of row buffer hits during reads +system.physmem.writeRowHits 46184 # Number of row buffer hits during writes +system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.03 # Row buffer hit rate for writes +system.physmem.avgGap 1159826.60 # Average gap between requests +system.cpu.branchPred.lookups 389306486 # Number of BP lookups +system.cpu.branchPred.condPredicted 255918117 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25837227 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 318716729 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258426851 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.949736 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57345473 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6929 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.083554 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57314223 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6830 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522560373 # DTB read hits -system.cpu.dtb.read_misses 588728 # DTB read misses +system.cpu.dtb.read_hits 523161150 # DTB read hits +system.cpu.dtb.read_misses 589917 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 523149101 # DTB read accesses -system.cpu.dtb.write_hits 283071161 # DTB write hits -system.cpu.dtb.write_misses 50270 # DTB write misses +system.cpu.dtb.read_accesses 523751067 # DTB read accesses +system.cpu.dtb.write_hits 283054328 # DTB write hits +system.cpu.dtb.write_misses 50219 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283121431 # DTB write accesses -system.cpu.dtb.data_hits 805631534 # DTB hits -system.cpu.dtb.data_misses 638998 # DTB misses +system.cpu.dtb.write_accesses 283104547 # DTB write accesses +system.cpu.dtb.data_hits 806215478 # DTB hits +system.cpu.dtb.data_misses 640136 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 806270532 # DTB accesses -system.cpu.itb.fetch_hits 395323042 # ITB hits -system.cpu.itb.fetch_misses 713 # ITB misses +system.cpu.dtb.data_accesses 806855614 # DTB accesses +system.cpu.itb.fetch_hits 394785394 # ITB hits +system.cpu.itb.fetch_misses 699 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 395323755 # ITB accesses +system.cpu.itb.fetch_accesses 394786093 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,98 +234,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1252730363 # number of cpu cycles simulated +system.cpu.numCycles 1259629801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410516643 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3276851782 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388924238 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315793702 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630639053 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158095234 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 69542401 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6974 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 395323042 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11287657 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1242455631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.637399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 410360591 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3276218906 # Number of instructions fetch has processed +system.cpu.fetch.Branches 389306486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315741074 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630494032 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 158021665 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72839727 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 148 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7225 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394785394 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10887979 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1245397368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.630661 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141486 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 611816578 49.24% 49.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57562553 4.63% 53.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43380535 3.49% 57.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71885087 5.79% 63.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129158557 10.40% 73.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46353903 3.73% 77.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41221359 3.32% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7475471 0.60% 81.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233601588 18.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614903336 49.37% 49.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57906135 4.65% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43369742 3.48% 57.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71861713 5.77% 63.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 128784934 10.34% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45918421 3.69% 77.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41219044 3.31% 80.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7530301 0.60% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233903742 18.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1242455631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310461 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.615768 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438637304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56111569 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606899212 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9069214 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131738332 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31728331 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12429 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3195294876 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46495 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131738332 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467849375 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21501203 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 26667 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 586406570 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 34933484 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3096787172 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15151 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28695106 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2055570524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3581032022 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3460282692 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120749330 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1245397368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309064 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.600938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438252598 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 59249665 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 607151892 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9059684 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131683529 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32106155 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12464 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3195982000 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46456 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131683529 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467489876 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24458626 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586624719 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35112981 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3097789893 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15390 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28842141 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2055592035 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3582007579 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3461235411 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120772168 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 670601454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4229 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 95 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109203185 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 744330520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351486216 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69160897 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8862018 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2624452005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 84 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2160789811 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17925786 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 801345385 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726874664 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1242455631 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.739128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803652 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670622965 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109569448 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 744863024 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351426191 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68774306 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8838853 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2625568629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 106 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2161657606 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17941272 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 802459111 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 727402983 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 67 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1245397368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.735717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803838 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 445618907 35.87% 35.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 197093468 15.86% 51.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251212495 20.22% 71.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120765174 9.72% 81.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104645405 8.42% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79514591 6.40% 96.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24185782 1.95% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17651908 1.42% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767901 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 448194916 35.99% 35.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197399515 15.85% 51.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251498314 20.19% 72.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120129049 9.65% 81.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104781180 8.41% 90.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79785428 6.41% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24208472 1.94% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17632328 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1768166 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1242455631 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1245397368 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146234 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146254 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available @@ -354,118 +354,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25650345 69.73% 72.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9987945 27.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25630359 69.68% 72.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10007683 27.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234634682 57.14% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851271 1.29% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589669482 27.29% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293155183 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235285403 57.15% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17096 0.00% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851426 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589902835 27.29% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293138748 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2160789811 # Type of FU issued -system.cpu.iq.rate 1.724864 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36784524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017024 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5467643878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3337715121 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990557348 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101685 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88155822 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73610149 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2120121697 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449886 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62086371 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2161657606 # Type of FU issued +system.cpu.iq.rate 1.716105 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36784296 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017017 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5472336078 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3339899399 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1991115322 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151102070 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88201964 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73610146 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2120988960 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77450190 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62844771 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 233260494 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21308 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76027 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140691320 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 233792998 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 726346 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76067 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140631295 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2184 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2432 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131738332 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7963688 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 401158 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2987881141 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 737486 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 744330520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351486216 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 191221 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1459 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76027 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25850018 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 29386 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25879404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066687986 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 523149239 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94101825 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131683529 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10419712 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 524131 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2988971416 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 730880 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 744863024 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351426191 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 106 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195253 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1467 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76067 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25831488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 28075 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25859563 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2067932709 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 523751206 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 93724897 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363429052 # number of nop insts executed -system.cpu.iew.exec_refs 806271170 # number of memory reference insts executed -system.cpu.iew.exec_branches 277685226 # Number of branches executed -system.cpu.iew.exec_stores 283121931 # Number of stores executed -system.cpu.iew.exec_rate 1.649747 # Inst execution rate -system.cpu.iew.wb_sent 2066566988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2064167497 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1181646251 # num instructions producing a value -system.cpu.iew.wb_consumers 1754266128 # num instructions consuming a value +system.cpu.iew.exec_nop 363402681 # number of nop insts executed +system.cpu.iew.exec_refs 806856273 # number of memory reference insts executed +system.cpu.iew.exec_branches 278042301 # Number of branches executed +system.cpu.iew.exec_stores 283105067 # Number of stores executed +system.cpu.iew.exec_rate 1.641699 # Inst execution rate +system.cpu.iew.wb_sent 2067106315 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2064725468 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181149065 # num instructions producing a value +system.cpu.iew.wb_consumers 1753530061 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.647735 # insts written-back per cycle +system.cpu.iew.wb_rate 1.639153 # insts written-back per cycle system.cpu.iew.wb_fanout 0.673584 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 961921272 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 963038308 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25843781 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1110717299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.808730 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509348 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25825176 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1113713839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.803863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507965 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 491335332 44.24% 44.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228930715 20.61% 64.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119800633 10.79% 75.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58838434 5.30% 80.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50772069 4.57% 85.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24138536 2.17% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19157540 1.72% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16738195 1.51% 90.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101005845 9.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 494406511 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228855545 20.55% 64.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119827890 10.76% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58850017 5.28% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50714183 4.55% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24146625 2.17% 87.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19124586 1.72% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16719001 1.50% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101069481 9.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1110717299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1113713839 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101005845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101069481 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3974983920 # The number of ROB reads -system.cpu.rob.rob_writes 6073558017 # The number of ROB writes -system.cpu.timesIdled 212495 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10274732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3979033860 # The number of ROB reads +system.cpu.rob.rob_writes 6075737407 # The number of ROB writes +system.cpu.timesIdled 331555 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14232433 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.687164 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.687164 # CPI: Total CPI of All Threads -system.cpu.ipc 1.455256 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.455256 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2628560765 # number of integer regfile reads -system.cpu.int_regfile_writes 1497106363 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811457 # number of floating regfile reads -system.cpu.fp_regfile_writes 52660996 # number of floating regfile writes +system.cpu.cpi 0.690949 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.690949 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447285 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447285 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2629419671 # number of integer regfile reads +system.cpu.int_regfile_writes 1497304474 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811610 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661263 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 8336 # number of replacements -system.cpu.icache.tagsinuse 1656.236510 # Cycle average of tags in use -system.cpu.icache.total_refs 395310182 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1655.843165 # Cycle average of tags in use +system.cpu.icache.total_refs 394772509 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10048 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39342.175756 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 39288.665307 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1656.236510 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.808709 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.808709 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 395310182 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 395310182 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 395310182 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 395310182 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 395310182 # number of overall hits -system.cpu.icache.overall_hits::total 395310182 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12860 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12860 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12860 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12860 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12860 # number of overall misses -system.cpu.icache.overall_misses::total 12860 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 302484999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 302484999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 302484999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 302484999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 302484999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 302484999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 395323042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 395323042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 395323042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 395323042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 395323042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 395323042 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1655.843165 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.808517 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.808517 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394772509 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394772509 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394772509 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394772509 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394772509 # number of overall hits +system.cpu.icache.overall_hits::total 394772509 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12885 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12885 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12885 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12885 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12885 # number of overall misses +system.cpu.icache.overall_misses::total 12885 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310466999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310466999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310466999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310466999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310466999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310466999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394785394 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394785394 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394785394 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394785394 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394785394 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394785394 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23521.384059 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23521.384059 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23521.384059 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476106 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2752 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473354 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476106 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109781392 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18848561489 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18958342881 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2750782112 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2750782112 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109781392 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21599343601 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21709124993 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109781392 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21599343601 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21709124993 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.273858 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278380 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278349 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933192 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933192 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.273858 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308773 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.273858 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308773 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39891.494186 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46367.696811 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46324.148038 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41147.342069 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41147.342069 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39891.494186 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45630.423744 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 45597.251438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39891.494186 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45630.423744 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 45597.251438 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406509 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409264 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473363 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476118 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473363 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476118 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116276173 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22528768631 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22645044804 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2972753104 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2972753104 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116276173 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25501521735 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25617797908 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116276173 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25501521735 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25617797908 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278353 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308777 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308777 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42205.507441 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55420.098032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55331.142744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44466.346127 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44466.346127 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527785 # number of replacements -system.cpu.dcache.tagsinuse 4094.883301 # Cycle average of tags in use -system.cpu.dcache.total_refs 668274960 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531881 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 436.244695 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 304908000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.883301 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999727 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999727 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 458541726 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458541726 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733214 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 668274940 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 668274940 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 668274940 # number of overall hits -system.cpu.dcache.overall_hits::total 668274940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925848 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925848 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061682 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061682 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2987530 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987530 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987530 # number of overall misses -system.cpu.dcache.overall_misses::total 2987530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59762661000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59762661000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33641566357 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33641566357 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93404227357 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93404227357 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93404227357 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93404227357 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 460467574 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460467574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1527805 # number of replacements +system.cpu.dcache.tagsinuse 4094.859699 # Cycle average of tags in use +system.cpu.dcache.total_refs 668117069 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531901 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 436.135931 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314208000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.859699 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999722 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999722 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458383895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458383895 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733146 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733146 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 28 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 28 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 668117041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 668117041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 668117041 # number of overall hits +system.cpu.dcache.overall_hits::total 668117041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925777 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925777 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061750 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061750 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2987527 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987527 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987527 # number of overall misses +system.cpu.dcache.overall_misses::total 2987527 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64904546500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64904546500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35420882879 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35420882879 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 100325429379 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 100325429379 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 100325429379 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 100325429379 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460309672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460309672 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 671262470 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 671262470 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 671262470 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 671262470 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004182 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004182 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 671104568 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 671104568 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 671104568 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 671104568 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004184 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004184 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004451 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004451 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004451 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004451 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31031.868039 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31031.868039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31687.045986 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31687.045986 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31264.699386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31264.699386 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11600 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 365 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33703.043758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33703.043758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33360.850369 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33360.850369 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33581.430186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33581.430186 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14466 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 388 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.780822 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 137 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.283505 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95985 # number of writebacks -system.cpu.dcache.writebacks::total 95985 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465605 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465605 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990044 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990044 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455649 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455649 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455649 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455649 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460243 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460243 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531881 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531881 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531881 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531881 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35985859000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35985859000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676864000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676864000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39662723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39662723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39662723000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39662723000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks +system.cpu.dcache.writebacks::total 95989 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465519 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465519 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990108 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455627 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455627 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455627 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455627 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460258 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460258 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531900 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531900 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531900 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531900 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39601531500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39601531500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899018500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899018500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43500550000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43500550000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43500550000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43500550000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003172 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002282 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002282 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24643.746965 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24643.746965 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51325.609313 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51325.609313 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.034483 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.034483 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27119.544286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27119.544286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54423.641160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54423.641160 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 96fe6f71c..2843a5b3f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.625047 # Number of seconds simulated -sim_ticks 625047295000 # Number of ticks simulated -final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.627778 # Number of seconds simulated +sim_ticks 627777658000 # Number of ticks simulated +final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72768 # Simulator instruction rate (inst/s) -host_op_rate 99100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32855066 # Simulator tick rate (ticks/s) -host_mem_usage 309740 # Number of bytes of host memory used -host_seconds 19024.38 # Real time elapsed on the host +host_inst_rate 102547 # Simulator instruction rate (inst/s) +host_op_rate 139655 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46502403 # Simulator tick rate (ticks/s) +host_mem_usage 263380 # Number of bytes of host memory used +host_seconds 13499.90 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory -system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155456 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 30397824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474966 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 248711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48384947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48633657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6767923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6767923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6767923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48384947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55401580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474974 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 246813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48174508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48421322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 246813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6738488 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6738488 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6738488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 246813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48174508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474966 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545412 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30398336 # Total number of bytes read from memory +system.physmem.cpureqs 545370 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30397824 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4340 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29731 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29624 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29606 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis +system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4306 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29627 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29652 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 625047219500 # Total gap between requests +system.physmem.totGap 627777588500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474974 # Categorize read packet sizes +system.physmem.readPktSize::6 474966 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4340 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4306 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2873 # Wh system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,36 +171,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3340611483 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18115671483 # Sum of mem lat for all requests -system.physmem.totBusLat 1899232000 # Total cycles spent in databus access -system.physmem.totBankLat 12875828000 # Total cycles spent in bank access -system.physmem.avgQLat 7035.71 # Average queueing delay per request -system.physmem.avgBankLat 27117.97 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38153.68 # Average memory access latency -system.physmem.avgRdBW 48.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.totQLat 3183088396 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 21162955896 # Sum of mem lat for all requests +system.physmem.totBusLat 2374030000 # Total cycles spent in databus access +system.physmem.totBankLat 15605837500 # Total cycles spent in bank access +system.physmem.avgQLat 6703.98 # Average queueing delay per request +system.physmem.avgBankLat 32867.82 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 44571.80 # Average memory access latency +system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 17.44 # Average write queue length over time -system.physmem.readRowHits 249146 # Number of row buffer hits during reads -system.physmem.writeRowHits 48036 # Number of row buffer hits during writes -system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes -system.physmem.avgGap 1155201.56 # Average gap between requests -system.cpu.branchPred.lookups 438808047 # Number of BP lookups -system.cpu.branchPred.condPredicted 349805436 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30625316 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 249957064 # Number of BTB lookups -system.cpu.branchPred.BTBHits 227370417 # Number of BTB hits +system.physmem.avgWrQLen 17.42 # Average write queue length over time +system.physmem.readRowHits 143321 # Number of row buffer hits during reads +system.physmem.writeRowHits 45521 # Number of row buffer hits during writes +system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes +system.physmem.avgGap 1160264.94 # Average gap between requests +system.cpu.branchPred.lookups 438315949 # Number of BP lookups +system.cpu.branchPred.condPredicted 349727895 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30635218 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 247833729 # Number of BTB lookups +system.cpu.branchPred.BTBHits 226959272 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.963789 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52357585 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806128 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806740 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,238 +244,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1250094591 # number of cpu cycles simulated +system.cpu.numCycles 1255555317 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 279728002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 600743262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158308312 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133148695 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11515 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333206369 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10414827 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1215386936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.189306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 353470069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2285596028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438315949 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 279264186 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 600835407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 132516295 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 333121638 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10719820 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1213960668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614688205 50.58% 50.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42445352 3.49% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 95116159 7.83% 61.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55675580 4.58% 66.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 72776602 5.99% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42276531 3.48% 75.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31131234 2.56% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31565180 2.60% 81.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 229712093 18.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 613169619 50.51% 50.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42771995 3.52% 54.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71974347 5.93% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42167025 3.47% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30997749 2.55% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 230060885 18.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1215386936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351020 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.829826 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 402796361 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 106301870 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561862491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16807396 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 127618818 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44638184 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3046676123 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27895 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 127618818 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 438124604 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 35349497 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 425259 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 541326873 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72541885 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2975830632 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4806802 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56918075 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2945274289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14167459331 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13596684512 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570774819 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1213960668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 402973564 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105163486 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561876522 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16833920 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 127113176 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44705456 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3047243338 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 127113176 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 438520822 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34436909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 439020 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 541081767 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72368974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2975054938 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4810929 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 57090218 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2946030157 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14164065012 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13593632114 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570432898 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 952134199 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23805 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 21281 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 197120926 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 972834043 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 492760757 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36385181 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 42690468 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2809386355 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28039 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2437787250 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13304140 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 911537771 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2374413817 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6655 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1215386936 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.005770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875210 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 952890067 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25235 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 195466607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 973207419 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 490834558 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40613994 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2806590548 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2437414927 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13391010 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 908731725 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2361150738 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1213960668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875088 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 379434397 31.22% 31.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183109361 15.07% 46.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 202931100 16.70% 62.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 170113731 14.00% 76.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132526126 10.90% 87.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 93839529 7.72% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37911750 3.12% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12465689 1.03% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3055253 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 377941740 31.13% 31.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183591562 15.12% 46.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 202672032 16.70% 62.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169721528 13.98% 76.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132842997 10.94% 87.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 93759242 7.72% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37926001 3.12% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12454015 1.03% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1215386936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1213960668 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 714674 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24388 0.03% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55116913 62.89% 63.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31779800 36.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55152383 62.89% 63.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1108876695 45.49% 45.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11224297 0.46% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502220 0.23% 46.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23416324 0.96% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838276108 34.39% 81.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442239839 18.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1108357182 45.47% 45.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502589 0.23% 46.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23405387 0.96% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838249114 34.39% 81.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442425362 18.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2437787250 # Type of FU issued -system.cpu.iq.rate 1.950082 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87635775 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6069393440 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3638225906 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2254362609 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122507911 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82793715 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56449336 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2462106345 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63316680 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84343916 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2437414927 # Type of FU issued +system.cpu.iq.rate 1.941304 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87694307 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6067361460 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3632711634 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2254358298 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122514379 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82707337 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56439823 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2461788389 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63320845 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84306518 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341446862 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7743 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429272 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 215765460 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341820238 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8584 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429957 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 213839261 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 127618818 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13752826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1562574 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2809426795 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1398231 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 972834043 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 492760757 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18053 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1558945 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429272 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32529008 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1513965 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34042973 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2363631235 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792642751 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 74156015 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 127113176 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12638060 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1558330 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2806632420 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 973207419 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 490834558 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1554339 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1429957 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32461973 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33956379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2363518803 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792548176 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12401 # number of nop insts executed -system.cpu.iew.exec_refs 1216279993 # number of memory reference insts executed -system.cpu.iew.exec_branches 322475744 # Number of branches executed -system.cpu.iew.exec_stores 423637242 # Number of stores executed -system.cpu.iew.exec_rate 1.890762 # Inst execution rate -system.cpu.iew.wb_sent 2336496726 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310811945 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347866502 # num instructions producing a value -system.cpu.iew.wb_consumers 2524860722 # num instructions consuming a value +system.cpu.iew.exec_nop 12468 # number of nop insts executed +system.cpu.iew.exec_refs 1216269109 # number of memory reference insts executed +system.cpu.iew.exec_branches 322574295 # Number of branches executed +system.cpu.iew.exec_stores 423720933 # Number of stores executed +system.cpu.iew.exec_rate 1.882449 # Inst execution rate +system.cpu.iew.wb_sent 2336489279 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2310798121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347631532 # num instructions producing a value +system.cpu.iew.wb_consumers 2523967593 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.848510 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533838 # average fanout of values written-back +system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 924090552 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 921296208 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30613261 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1087768118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.733215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398367 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30621417 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1086847492 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398806 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 447474994 41.14% 41.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288616071 26.53% 67.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95091930 8.74% 76.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70192926 6.45% 82.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46475898 4.27% 87.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22197093 2.04% 89.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15849951 1.46% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10985154 1.01% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884101 8.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 446547765 41.09% 41.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288590720 26.55% 67.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95114963 8.75% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46461872 4.27% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22187807 2.04% 89.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15847038 1.46% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10983680 1.01% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884052 8.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1087768118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1086847492 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -486,200 +487,200 @@ system.cpu.commit.branches 299634395 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884101 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884052 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3806292582 # The number of ROB reads -system.cpu.rob.rob_writes 5746483501 # The number of ROB writes -system.cpu.timesIdled 353075 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34707655 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3802577661 # The number of ROB reads +system.cpu.rob.rob_writes 5740389540 # The number of ROB writes +system.cpu.timesIdled 353175 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41594649 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.903006 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.903006 # CPI: Total CPI of All Threads -system.cpu.ipc 1.107413 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.107413 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11775193288 # number of integer regfile reads -system.cpu.int_regfile_writes 2227107160 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795849 # number of floating regfile reads -system.cpu.fp_regfile_writes 49561296 # number of floating regfile writes -system.cpu.misc_regfile_reads 1363965830 # number of misc regfile reads +system.cpu.cpi 0.906950 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11774707522 # number of integer regfile reads +system.cpu.int_regfile_writes 2226782313 # number of integer regfile writes +system.cpu.fp_regfile_reads 68797358 # number of floating regfile reads +system.cpu.fp_regfile_writes 49551948 # number of floating regfile writes +system.cpu.misc_regfile_reads 1364040381 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.icache.replacements 22468 # number of replacements -system.cpu.icache.tagsinuse 1641.255803 # Cycle average of tags in use -system.cpu.icache.total_refs 333171598 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24150 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13795.925383 # Average number of references to valid blocks. +system.cpu.icache.replacements 22740 # number of replacements +system.cpu.icache.tagsinuse 1642.119595 # Cycle average of tags in use +system.cpu.icache.total_refs 333085984 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13639.884685 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1641.255803 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801394 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801394 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 333175666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 333175666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 333175666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 333175666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 333175666 # number of overall hits -system.cpu.icache.overall_hits::total 333175666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30702 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30702 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30702 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30702 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30702 # number of overall misses -system.cpu.icache.overall_misses::total 30702 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 468488500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 468488500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 468488500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 468488500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 468488500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 468488500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333206368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333206368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333206368 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333206368 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333206368 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333206368 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15259.217641 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15259.217641 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15259.217641 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15259.217641 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1109 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1642.119595 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 333090009 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 333090009 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 333090009 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 333090009 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 333090009 # number of overall hits +system.cpu.icache.overall_hits::total 333090009 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31628 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31628 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31628 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31628 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31628 # number of overall misses +system.cpu.icache.overall_misses::total 31628 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 481224999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 481224999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 481224999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 481224999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 481224999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 481224999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333121637 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333121637 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333121637 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333121637 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333121637 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333121637 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15215.157424 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15215.157424 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15215.157424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15215.157424 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.607143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 32.692308 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2210 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2210 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2210 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2210 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2210 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2210 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28492 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2899 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2899 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28729 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28729 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28729 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28729 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28729 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28729 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13455.410874 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13455.410874 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13455.410874 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13455.410874 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442192 # number of replacements -system.cpu.l2cache.tagsinuse 32688.738823 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1109575 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.336242 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 442184 # number of replacements +system.cpu.l2cache.tagsinuse 32692.569161 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67561.596957 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -690,193 +691,193 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23110733226 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23206984521 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277545 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274674 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999309 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999309 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103136612 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729331565 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26189400189 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999304 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999304 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304239 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304239 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39625.893372 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50968.210980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50900.833732 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35670.556368 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35670.556368 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.765942 # 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Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999664 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693909081 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693909081 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276100966 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276100966 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1533127 # number of replacements +system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use +system.cpu.dcache.total_refs 969988260 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.000356 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 693861551 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693861551 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093814 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093814 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 970010047 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 970010047 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 970010047 # number of overall hits -system.cpu.dcache.overall_hits::total 970010047 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953320 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953320 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 834712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 834712 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 969955365 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969955365 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969955365 # number of overall hits +system.cpu.dcache.overall_hits::total 969955365 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 841864 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 841864 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2788032 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2788032 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2788032 # number of overall misses -system.cpu.dcache.overall_misses::total 2788032 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 67394089000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 67394089000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39986185470 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39986185470 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 171500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 107380274470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 107380274470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 107380274470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 107380274470 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695862401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695862401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2795405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795405 # number of overall misses +system.cpu.dcache.overall_misses::total 2795405 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66482799000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66482799000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39425610969 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39425610969 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105908409969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105908409969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105908409969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105908409969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695815092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695815092 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972798079 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972798079 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972798079 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972798079 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972750770 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972750770 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972750770 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972750770 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003040 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34502.328855 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34502.328855 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47904.169905 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47904.169905 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38514.720947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38514.720947 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2182 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 795 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 88 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.964286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.034091 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34031.944556 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34031.944556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46831.330202 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46831.330202 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37886.606760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37886.606760 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 90 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807018 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.300000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96308 # number of writebacks -system.cpu.dcache.writebacks::total 96308 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488800 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488800 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757854 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 757854 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks +system.cpu.dcache.writebacks::total 96321 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765039 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765039 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1246654 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1246654 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1246654 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1246654 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464520 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464520 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76858 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76858 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541378 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541378 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541378 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541378 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37907812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37907812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3481886500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3481886500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41389699000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41389699000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41389699000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41389699000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1253873 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1253873 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1253873 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1253873 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76825 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541532 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541532 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831551000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831551000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240718500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44240718500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240718500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44240718500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25884.120736 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25884.120736 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45302.850712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45302.850712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.941259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.941259 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44375.756590 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44375.756590 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 8052f41c2..2f98c15fc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043266 # Number of seconds simulated -sim_ticks 43266024500 # Number of ticks simulated -final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042726 # Number of seconds simulated +sim_ticks 42726055500 # Number of ticks simulated +final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92573 # Simulator instruction rate (inst/s) -host_op_rate 92573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45339086 # Simulator tick rate (ticks/s) -host_mem_usage 308556 # Number of bytes of host memory used -host_seconds 954.28 # Real time elapsed on the host +host_inst_rate 156388 # Simulator instruction rate (inst/s) +host_op_rate 156388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75637274 # Simulator tick rate (ticks/s) +host_mem_usage 259292 # Number of bytes of host memory used +host_seconds 564.88 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 10593088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454720 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165517 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10509863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 234326313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 244836176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10509863 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10509863 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 168626725 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 168626725 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 168626725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10509863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 234326313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 413462901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165517 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165519 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279514 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10593088 # Total number of bytes read from memory +system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10593216 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10593088 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10334 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10242 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7300 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7379 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43266004500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry +system.physmem.totGap 42726035000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165517 # Categorize read packet sizes +system.physmem.readPktSize::6 165519 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 113997 # categorize write packet sizes +system.physmem.writePktSize::6 114011 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see @@ -161,45 +161,45 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9309879146 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11706015146 # Sum of mem lat for all requests -system.physmem.totBusLat 662068000 # Total cycles spent in databus access -system.physmem.totBankLat 1734068000 # Total cycles spent in bank access -system.physmem.avgQLat 56247.27 # Average queueing delay per request -system.physmem.avgBankLat 10476.68 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70723.94 # Average memory access latency -system.physmem.avgRdBW 244.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 168.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 244.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 168.63 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.58 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.27 # Average read queue length over time -system.physmem.avgWrQLen 10.35 # Average write queue length over time -system.physmem.readRowHits 151965 # Number of row buffer hits during reads -system.physmem.writeRowHits 41713 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes -system.physmem.avgGap 154790.12 # Average gap between requests -system.cpu.branchPred.lookups 18742312 # Number of BP lookups -system.cpu.branchPred.condPredicted 12317439 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4774431 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15498318 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4661486 # Number of BTB hits +system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests +system.physmem.totBusLat 827595000 # Total cycles spent in databus access +system.physmem.totBankLat 1765926250 # Total cycles spent in bank access +system.physmem.avgQLat 42615.22 # Average queueing delay per request +system.physmem.avgBankLat 10669.02 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58284.24 # Average memory access latency +system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.27 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.23 # Average read queue length over time +system.physmem.avgWrQLen 10.42 # Average write queue length over time +system.physmem.readRowHits 148856 # Number of row buffer hits during reads +system.physmem.writeRowHits 71620 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes +system.physmem.avgGap 152857.21 # Average gap between requests +system.cpu.branchPred.lookups 18742591 # Number of BP lookups +system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.077367 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660962 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -209,18 +209,18 @@ system.cpu.dtb.read_hits 20277550 # DT system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 20367698 # DTB read accesses -system.cpu.dtb.write_hits 14728696 # DTB write hits +system.cpu.dtb.write_hits 14728779 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14735948 # DTB write accesses -system.cpu.dtb.data_hits 35006246 # DTB hits +system.cpu.dtb.write_accesses 14736031 # DTB write accesses +system.cpu.dtb.data_hits 35006329 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103646 # DTB accesses -system.cpu.itb.fetch_hits 12367278 # ITB hits -system.cpu.itb.fetch_misses 11044 # ITB misses +system.cpu.dtb.data_accesses 35103729 # DTB accesses +system.cpu.itb.fetch_hits 12368275 # ITB hits +system.cpu.itb.fetch_misses 11063 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378322 # ITB accesses +system.cpu.itb.fetch_accesses 12379338 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,34 +234,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 86532050 # number of cpu cycles simulated +system.cpu.numCycles 85452112 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126488722 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66053 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293683 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14165611 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060577 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447125 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216806 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4663931 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9108659 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.863863 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777842 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060657 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77186042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 230961 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16958681 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69573369 # Number of cycles cpu stages are processed. -system.cpu.activity 80.401850 # Percentage of cycles cpu is active +system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed. +system.cpu.activity 81.422683 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -273,194 +273,194 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.979527 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.967302 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.979527 # CPI: Total CPI of All Threads -system.cpu.ipc 1.020901 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.967302 # CPI: Total CPI of All Threads +system.cpu.ipc 1.033803 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.020901 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33881250 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52650800 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.845432 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44079875 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42452175 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 49.059481 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 43502532 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43029518 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.726683 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 64419596 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22112454 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.554062 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40482959 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46049091 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 53.216226 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 84282 # number of replacements -system.cpu.icache.tagsinuse 1908.908494 # Cycle average of tags in use -system.cpu.icache.total_refs 12250113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 86328 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.901967 # Average number of references to valid blocks. +system.cpu.ipc_total 1.033803 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32797293 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52654819 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.619096 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 42999337 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42452775 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 49.680194 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 42422406 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43029706 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 50.355345 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 63339640 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22112472 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.877034 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 39402909 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 84308 # number of replacements +system.cpu.icache.tagsinuse 1908.296965 # Cycle average of tags in use +system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1908.908494 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.932084 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.932084 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12250113 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250113 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250113 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250113 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250113 # number of overall hits -system.cpu.icache.overall_hits::total 12250113 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117156 # number of overall misses -system.cpu.icache.overall_misses::total 117156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1822166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1822166500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1822166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1822166500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1822166500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1822166500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15553.334870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15553.334870 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15553.334870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15553.334870 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12251160 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12251160 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12251160 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12251160 # number of overall hits +system.cpu.icache.overall_hits::total 12251160 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117106 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117106 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117106 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses +system.cpu.icache.overall_misses::total 117106 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1888398500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1888398500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1888398500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1888398500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1888398500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1888398500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12368266 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12368266 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12368266 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16125.548648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16125.548648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16125.548648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16125.548648 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.263158 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.066667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30828 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30828 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30828 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30828 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30828 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86328 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 86328 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 86328 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 86328 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 86328 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 86328 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1279244500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1279244500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1279244500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1279244500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1279244500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1279244500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14818.419285 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14818.419285 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30752 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30752 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30752 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30752 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30752 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30752 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86354 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336296000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1336296000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336296000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1336296000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336296000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1336296000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15474.627695 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15474.627695 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 56839.869470 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91650.663529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91650.663529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84367.945674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84367.945674 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # 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Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995652 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995652 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180269 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180269 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574613 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574613 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754882 # number of overall hits +system.cpu.dcache.overall_hits::total 33754882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038764 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038764 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135133 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses +system.cpu.dcache.overall_misses::total 1135133 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3868219500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3868219500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76703201000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76703201000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80571420500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80571420500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80571420500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80571420500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -559,38 +559,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032531 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032531 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032531 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032531 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40910.768209 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40910.768209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88012.808503 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 88012.808503 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84013.662839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84013.662839 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6187652 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 65 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116324 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.666283 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.666283 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73840.834877 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73840.834877 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70979.718236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70979.718236 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5030029 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.193253 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 65 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.221477 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks system.cpu.dcache.writebacks::total 168350 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35602 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35602 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895066 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895066 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35604 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35604 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895184 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895184 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930788 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204345 system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1934793000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1934793000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14541156500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14541156500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16475949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16475949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16475949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31840.582572 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31840.582572 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101275.640758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101275.640758 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index ee0778484..2c49ec916 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024415 # Number of seconds simulated -sim_ticks 24414646000 # Number of ticks simulated -final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023883 # Number of seconds simulated +sim_ticks 23882696000 # Number of ticks simulated +final_tick 23882696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131517 # Simulator instruction rate (inst/s) -host_op_rate 131517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40342582 # Simulator tick rate (ticks/s) -host_mem_usage 309584 # Number of bytes of host memory used -host_seconds 605.18 # Real time elapsed on the host +host_inst_rate 224964 # Simulator instruction rate (inst/s) +host_op_rate 224964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67503934 # Simulator tick rate (ticks/s) +host_mem_usage 262380 # Number of bytes of host memory used +host_seconds 353.80 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153920 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158655 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166317 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20084993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 415894623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 435979616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20084993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20084993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 298876338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 298876338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 298876338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20084993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 415894623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 734855955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166317 # Total number of read requests seen -system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280332 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10644288 # Total number of bytes read from memory -system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10644288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 490816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154176 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7669 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158659 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166328 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20551114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425168750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 445719863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20551114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20551114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 305536025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 305536025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 305536025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20551114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425168750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 751255888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166328 # Total number of read requests seen +system.physmem.writeReqs 114016 # Total number of write requests seen +system.physmem.cpureqs 280344 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10644992 # Total number of bytes read from memory +system.physmem.bytesWritten 7297024 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10644992 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10583 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10017 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10252 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6953 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6884 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7381 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6936 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7376 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7191 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10530 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10395 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10156 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10115 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7275 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24414612500 # Total gap between requests +system.physmem.totGap 23882663000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166317 # Categorize read packet sizes +system.physmem.readPktSize::6 166328 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 114015 # categorize write packet sizes +system.physmem.writePktSize::6 114016 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 67939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63061 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,14 +138,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4949 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9394568799 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11745778799 # Sum of mem lat for all requests -system.physmem.totBusLat 665260000 # Total cycles spent in databus access -system.physmem.totBankLat 1685950000 # Total cycles spent in bank access -system.physmem.avgQLat 56486.60 # Average queueing delay per request -system.physmem.avgBankLat 10137.09 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70623.69 # Average memory access latency -system.physmem.avgRdBW 435.98 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 298.88 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 435.98 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 298.88 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.48 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 152275 # Number of row buffer hits during reads -system.physmem.writeRowHits 40821 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes -system.physmem.avgGap 87091.78 # Average gap between requests -system.cpu.branchPred.lookups 16536427 # Number of BP lookups -system.cpu.branchPred.condPredicted 10675204 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 418905 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11705282 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7341882 # Number of BTB hits +system.physmem.totQLat 7244561154 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9788827404 # Sum of mem lat for all requests +system.physmem.totBusLat 831635000 # Total cycles spent in databus access +system.physmem.totBankLat 1712631250 # Total cycles spent in bank access +system.physmem.avgQLat 43556.13 # Average queueing delay per request +system.physmem.avgBankLat 10296.77 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58852.91 # Average memory access latency +system.physmem.avgRdBW 445.72 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 305.54 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 445.72 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 305.54 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 5.87 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.41 # Average read queue length over time +system.physmem.avgWrQLen 10.04 # Average write queue length over time +system.physmem.readRowHits 149202 # Number of row buffer hits during reads +system.physmem.writeRowHits 70865 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.15 # Row buffer hit rate for writes +system.physmem.avgGap 85190.56 # Average gap between requests +system.cpu.branchPred.lookups 16542352 # Number of BP lookups +system.cpu.branchPred.condPredicted 10681130 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 417709 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11519084 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7344749 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.722812 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1987114 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42052 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.761572 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990053 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40943 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22403664 # DTB read hits -system.cpu.dtb.read_misses 220373 # DTB read misses -system.cpu.dtb.read_acv 50 # DTB read access violations -system.cpu.dtb.read_accesses 22624037 # DTB read accesses -system.cpu.dtb.write_hits 15711393 # DTB write hits -system.cpu.dtb.write_misses 41143 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15752536 # DTB write accesses -system.cpu.dtb.data_hits 38115057 # DTB hits -system.cpu.dtb.data_misses 261516 # DTB misses -system.cpu.dtb.data_acv 54 # DTB access violations -system.cpu.dtb.data_accesses 38376573 # DTB accesses -system.cpu.itb.fetch_hits 13911095 # ITB hits -system.cpu.itb.fetch_misses 34570 # ITB misses +system.cpu.dtb.read_hits 22396635 # DTB read hits +system.cpu.dtb.read_misses 219070 # DTB read misses +system.cpu.dtb.read_acv 53 # DTB read access violations +system.cpu.dtb.read_accesses 22615705 # DTB read accesses +system.cpu.dtb.write_hits 15704107 # DTB write hits +system.cpu.dtb.write_misses 40999 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 15745106 # DTB write accesses +system.cpu.dtb.data_hits 38100742 # DTB hits +system.cpu.dtb.data_misses 260069 # DTB misses +system.cpu.dtb.data_acv 59 # DTB access violations +system.cpu.dtb.data_accesses 38360811 # DTB accesses +system.cpu.itb.fetch_hits 13916224 # ITB hits +system.cpu.itb.fetch_misses 34938 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13945665 # ITB accesses +system.cpu.itb.fetch_accesses 13951162 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,238 +234,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 48829295 # number of cpu cycles simulated +system.cpu.numCycles 47765395 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9328996 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19544366 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2001802 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6569447 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 313140 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13911095 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206120 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43680847 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.412284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.135635 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15792461 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105331722 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16542352 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9334802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19546012 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2000871 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6407929 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 309888 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13916224 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206477 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43516697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.420490 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.137268 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24136481 55.26% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1528556 3.50% 58.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1370450 3.14% 61.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1506920 3.45% 65.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4142263 9.48% 74.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846581 4.23% 79.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 675220 1.55% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1067886 2.44% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7406490 16.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23970685 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1532413 3.52% 58.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1373284 3.16% 61.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510754 3.47% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137026 9.51% 74.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1849440 4.25% 78.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 675147 1.55% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069291 2.46% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7398657 17.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43680847 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.338658 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.157938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16869436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6110909 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18556945 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 793975 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1349582 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3748874 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107098 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103640564 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305578 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1349582 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17328003 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3849727 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84405 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18840913 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2228217 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102377631 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2729 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2099672 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61646345 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123373260 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122920505 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 452755 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43516697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346325 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.205189 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16865376 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5950414 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18541793 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 811002 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1348112 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3746218 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106835 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103623462 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 302130 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1348112 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17322335 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3664232 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84922 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18847631 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2249465 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102361026 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 441 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2593 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2123305 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61634933 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123335826 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122884489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 451337 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9099464 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5534 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4609870 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23237420 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16278692 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1191956 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 452268 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90762555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88451556 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 99102 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10723978 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4670719 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 705 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43680847 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.024951 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.111086 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9088052 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5535 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4634659 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23233430 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16268738 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1206800 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 454955 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90740192 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5270 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88424187 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 96369 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10688335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4670210 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43516697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.031960 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.108941 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15440168 35.35% 35.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6886071 15.76% 51.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5612203 12.85% 63.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4740584 10.85% 74.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4695591 10.75% 85.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649897 6.07% 91.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1923598 4.40% 96.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1315990 3.01% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 416745 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15243033 35.03% 35.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6914940 15.89% 50.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5620995 12.92% 63.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4761900 10.94% 74.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4675938 10.75% 85.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2651856 6.09% 91.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1932644 4.44% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1300467 2.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 414924 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43680847 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43516697 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126167 6.80% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 781555 42.12% 48.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 947649 51.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 125783 6.76% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 785729 42.22% 48.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 949726 51.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49366923 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43857 0.05% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121501 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49355625 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43814 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121422 0.14% 56.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121281 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 51 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22854121 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15904789 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121345 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38953 0.04% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22849621 25.84% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15893267 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88451556 # Type of FU issued -system.cpu.iq.rate 1.811444 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1855371 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020976 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 221933846 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101092156 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86564383 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 604586 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 417604 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294342 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90004545 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302382 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1470214 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88424187 # Type of FU issued +system.cpu.iq.rate 1.851219 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1861238 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021049 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221719097 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101035757 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86539045 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603581 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 415879 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294278 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89983556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301869 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467344 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2960782 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4826 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1665315 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2956792 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4757 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2876 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 81924 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2846 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 90923 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1349582 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2855245 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 77128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100251958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 208716 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23237420 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16278692 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5288 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 488 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 198098 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161281 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 359379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87608240 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22627118 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 843316 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1348112 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2689881 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74163 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100228982 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217751 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23233430 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16268738 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5270 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60091 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 514 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 196583 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160586 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 357169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87578672 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22618883 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 845515 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9484115 # number of nop insts executed -system.cpu.iew.exec_refs 38379967 # number of memory reference insts executed -system.cpu.iew.exec_branches 15086881 # Number of branches executed -system.cpu.iew.exec_stores 15752849 # Number of stores executed -system.cpu.iew.exec_rate 1.794174 # Inst execution rate -system.cpu.iew.wb_sent 87251382 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86858725 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33364118 # num instructions producing a value -system.cpu.iew.wb_consumers 43780682 # num instructions consuming a value +system.cpu.iew.exec_nop 9483520 # number of nop insts executed +system.cpu.iew.exec_refs 38364354 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084185 # Number of branches executed +system.cpu.iew.exec_stores 15745471 # Number of stores executed +system.cpu.iew.exec_rate 1.833517 # Inst execution rate +system.cpu.iew.wb_sent 87223381 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86833323 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33358386 # num instructions producing a value +system.cpu.iew.wb_consumers 43765374 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.778824 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762074 # average fanout of values written-back +system.cpu.iew.wb_rate 1.817913 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762210 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8914358 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8889050 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 313984 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42331265 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.086889 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804714 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 313123 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42168585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.094940 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.806680 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19478152 46.01% 46.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7019307 16.58% 62.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3402930 8.04% 70.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2062880 4.87% 75.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2059752 4.87% 80.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1161194 2.74% 83.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1088223 2.57% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718067 1.70% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5340760 12.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19301880 45.77% 45.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7026183 16.66% 62.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3423669 8.12% 70.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2056444 4.88% 75.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2047690 4.86% 80.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1162920 2.76% 83.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1093248 2.59% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719437 1.71% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5337114 12.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42331265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42168585 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5340760 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5337114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132928193 # The number of ROB reads -system.cpu.rob.rob_writes 195862433 # The number of ROB writes -system.cpu.timesIdled 69428 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5148448 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132743851 # The number of ROB reads +system.cpu.rob.rob_writes 195810249 # The number of ROB writes +system.cpu.timesIdled 70469 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4248698 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.613497 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.613497 # CPI: Total CPI of All Threads -system.cpu.ipc 1.630000 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.630000 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115949669 # number of integer regfile reads -system.cpu.int_regfile_writes 57525330 # number of integer regfile writes -system.cpu.fp_regfile_reads 249508 # number of floating regfile reads -system.cpu.fp_regfile_writes 240213 # number of floating regfile writes -system.cpu.misc_regfile_reads 38023 # number of misc regfile reads +system.cpu.cpi 0.600130 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600130 # CPI: Total CPI of All Threads +system.cpu.ipc 1.666306 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.666306 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115907691 # number of integer regfile reads +system.cpu.int_regfile_writes 57507162 # number of integer regfile writes +system.cpu.fp_regfile_reads 249392 # number of floating regfile reads +system.cpu.fp_regfile_writes 240337 # number of floating regfile writes +system.cpu.misc_regfile_reads 38035 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 91621 # number of replacements -system.cpu.icache.tagsinuse 1930.572235 # Cycle average of tags in use -system.cpu.icache.total_refs 13805106 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93669 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.381802 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19945764000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1930.572235 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942662 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942662 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13805106 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13805106 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13805106 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13805106 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13805106 # number of overall hits -system.cpu.icache.overall_hits::total 13805106 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105989 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105989 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105989 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105989 # number of overall misses -system.cpu.icache.overall_misses::total 105989 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1780097998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1780097998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1780097998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1780097998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1780097998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1780097998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13911095 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13911095 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13911095 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13911095 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13911095 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13911095 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007619 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007619 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007619 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007619 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007619 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007619 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16795.120229 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16795.120229 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16795.120229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16795.120229 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 364 # number of cycles access was blocked +system.cpu.icache.replacements 91216 # number of replacements +system.cpu.icache.tagsinuse 1928.922459 # Cycle average of tags in use +system.cpu.icache.total_refs 13810559 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93264 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 148.080277 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19641578000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1928.922459 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.941857 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.941857 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13810559 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13810559 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13810559 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13810559 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13810559 # number of overall hits +system.cpu.icache.overall_hits::total 13810559 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105664 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105664 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105664 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105664 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105664 # number of overall misses +system.cpu.icache.overall_misses::total 105664 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863781999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1863781999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1863781999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1863781999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1863781999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1863781999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13916223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13916223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13916223 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13916223 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13916223 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13916223 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007593 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007593 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007593 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007593 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007593 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007593 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17638.760590 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17638.760590 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17638.760590 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17638.760590 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.071429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12319 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12319 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12319 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12319 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12319 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12319 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93670 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93670 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93670 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93670 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93670 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93670 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1391219000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1391219000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1391219000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1391219000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1391219000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1391219000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006733 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006733 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006733 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14852.343333 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14852.343333 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12399 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12399 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12399 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12399 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12399 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12399 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93265 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93265 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93265 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93265 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93265 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93265 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1450659000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1450659000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1450659000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1450659000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1450659000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1450659000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006702 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006702 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006702 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15554.162869 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15554.162869 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15554.162869 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15554.162869 # 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Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26652.913522 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2131.265496 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2069.596933 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.813382 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.065041 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.063159 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941583 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 86007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34313 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120320 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168957 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201507 # number of replacements -system.cpu.dcache.tagsinuse 4077.368240 # Cycle average of tags in use -system.cpu.dcache.total_refs 34205521 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205603 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.366838 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 173993000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4077.368240 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995451 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995451 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20631452 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20631452 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574012 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34205464 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34205464 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34205464 # number of overall hits -system.cpu.dcache.overall_hits::total 34205464 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267045 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267045 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039365 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039365 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306410 # number of overall misses -system.cpu.dcache.overall_misses::total 1306410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12450634000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12450634000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 93436551833 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 93436551833 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105887185833 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105887185833 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105887185833 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105887185833 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20898497 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20898497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201431 # number of replacements +system.cpu.dcache.tagsinuse 4076.502318 # Cycle average of tags in use +system.cpu.dcache.total_refs 34195386 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205527 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.379045 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 178801000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.502318 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995240 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995240 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20621336 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20621336 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13573997 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13573997 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34195333 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34195333 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34195333 # number of overall hits +system.cpu.dcache.overall_hits::total 34195333 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 266907 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 266907 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039380 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039380 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306287 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306287 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306287 # number of overall misses +system.cpu.dcache.overall_misses::total 1306287 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12007604500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12007604500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 79088080451 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 79088080451 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91095684951 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91095684951 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91095684951 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91095684951 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20888243 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20888243 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35511874 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35511874 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35511874 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35511874 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35501620 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35501620 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35501620 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35501620 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012778 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012778 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071124 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071124 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036788 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036788 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036788 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036788 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46623.730083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46623.730083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89897.727779 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89897.727779 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81052.032542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81052.032542 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5486905 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071125 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071125 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036795 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036795 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036795 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036795 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44987.971466 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44987.971466 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76091.593499 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76091.593499 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69736.348100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69736.348100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4377310 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112436 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112282 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.800251 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.984966 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168957 # number of writebacks -system.cpu.dcache.writebacks::total 168957 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895935 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895935 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100807 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100807 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100807 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100807 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62173 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62173 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143430 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143430 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205603 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205603 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205603 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205603 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2029919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2029919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14640535990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14640535990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16670455490 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16670455490 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16670455490 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16670455490 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32649.534364 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32649.534364 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102074.433452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102074.433452 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168913 # number of writebacks +system.cpu.dcache.writebacks::total 168913 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204795 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204795 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895965 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895965 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100760 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100760 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100760 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100760 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62112 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143415 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143415 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205527 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205527 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205527 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205527 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2016329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2016329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12443477492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12443477492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14459806992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14459806992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14459806992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14459806992 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002974 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002974 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32462.801069 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32462.801069 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86765.523076 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86765.523076 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 57be29288..bdf692e24 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026275 # Number of seconds simulated -sim_ticks 26275145500 # Number of ticks simulated -final_tick 26275145500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025578 # Number of seconds simulated +sim_ticks 25577832000 # Number of ticks simulated +final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87619 # Simulator instruction rate (inst/s) -host_op_rate 124343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32467681 # Simulator tick rate (ticks/s) -host_mem_usage 316828 # Number of bytes of host memory used -host_seconds 809.27 # Real time elapsed on the host +host_inst_rate 153227 # Simulator instruction rate (inst/s) +host_op_rate 217448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55271946 # Simulator tick rate (ticks/s) +host_mem_usage 270340 # Number of bytes of host memory used +host_seconds 462.76 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128759 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11345779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302280495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 313626275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11345779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11345779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 204474910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 204474910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 204474910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11345779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302280495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 518101184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128759 # Total number of read requests seen -system.physmem.writeReqs 83947 # Total number of write requests seen -system.physmem.cpureqs 213029 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8240576 # Total number of bytes read from memory -system.physmem.bytesWritten 5372608 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8240576 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372608 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128779 # Total number of read requests seen +system.physmem.writeReqs 83944 # Total number of write requests seen +system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241856 # Total number of bytes read from memory +system.physmem.bytesWritten 5372416 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 323 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8094 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7925 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7989 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8178 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8151 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8058 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7986 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7982 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5173 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5371 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5150 # Track writes on a per bank basis +system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26275013500 # Total gap between requests +system.physmem.totGap 25577735000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128759 # Categorize read packet sizes +system.physmem.readPktSize::6 128779 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83947 # categorize write packet sizes +system.physmem.writePktSize::6 83944 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,14 +102,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 323 # categorize neither packet sizes +system.physmem.neitherpktsize::6 312 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,11 +138,11 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -155,52 +155,52 @@ system.physmem.wrQLenPdf::13 3650 # Wh system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4891352059 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6777204059 # Sum of mem lat for all requests -system.physmem.totBusLat 515028000 # Total cycles spent in databus access -system.physmem.totBankLat 1370824000 # Total cycles spent in bank access -system.physmem.avgQLat 37989.02 # Average queueing delay per request -system.physmem.avgBankLat 10646.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52635.62 # Average memory access latency -system.physmem.avgRdBW 313.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 204.47 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 313.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 204.47 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.24 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.26 # Average read queue length over time -system.physmem.avgWrQLen 9.34 # Average write queue length over time -system.physmem.readRowHits 118922 # Number of row buffer hits during reads -system.physmem.writeRowHits 27176 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.37 # Row buffer hit rate for writes -system.physmem.avgGap 123527.37 # Average gap between requests -system.cpu.branchPred.lookups 16626972 # Number of BP lookups -system.cpu.branchPred.condPredicted 12763144 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 604576 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10780847 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7773827 # Number of BTB hits +system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests +system.physmem.totBusLat 643885000 # Total cycles spent in databus access +system.physmem.totBankLat 1400135000 # Total cycles spent in bank access +system.physmem.avgQLat 24884.99 # Average queueing delay per request +system.physmem.avgBankLat 10872.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 40757.55 # Average memory access latency +system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 4.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.21 # Average read queue length over time +system.physmem.avgWrQLen 9.73 # Average write queue length over time +system.physmem.readRowHits 116758 # Number of row buffer hits during reads +system.physmem.writeRowHits 52879 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes +system.physmem.avgGap 120239.63 # Average gap between requests +system.cpu.branchPred.lookups 16629564 # Number of BP lookups +system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.107757 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825491 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113784 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,136 +244,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 52550292 # number of cpu cycles simulated +system.cpu.numCycles 51155665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12554350 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85230964 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16626972 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9599318 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21200413 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2370934 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10497631 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11689041 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 183016 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45992800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.594519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24812491 53.95% 53.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2139973 4.65% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1966955 4.28% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042614 4.44% 67.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1467231 3.19% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1381601 3.00% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958651 2.08% 75.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1187660 2.58% 78.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10035624 21.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45992800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316401 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.621893 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14631573 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8854890 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19476912 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1392472 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1636953 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3331046 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104815 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116877182 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363170 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1636953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16335988 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2535467 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 864548 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19115469 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5504375 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114992065 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17001 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4650627 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 317 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115303250 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529787373 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529782097 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5276 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16170578 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20502 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20496 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13002691 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29626313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22450124 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3876856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4338192 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111565223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36031 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107269202 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 275818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10829565 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25919062 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2245 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45992800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.332304 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990217 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10779099 23.44% 23.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8049451 17.50% 40.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7422892 16.14% 57.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7126081 15.49% 72.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5395767 11.73% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3928809 8.54% 92.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1841047 4.00% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 874903 1.90% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 574751 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45992800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 114108 4.61% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1356583 54.78% 59.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1005840 40.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56641700 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91676 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 165 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -399,84 +399,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28901726 26.94% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21633928 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107269202 # Type of FU issued -system.cpu.iq.rate 2.041267 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2476532 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023087 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263283068 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122458972 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105581252 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 486 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 768 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109745491 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2188417 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued +system.cpu.iq.rate 2.096836 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2319205 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6776 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29966 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1894386 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 503 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1636953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1044060 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45930 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111611011 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 291580 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29626313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22450124 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20111 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6644 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5462 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29966 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393316 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181236 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 574552 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106238160 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28602099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1031042 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9757 # number of nop insts executed -system.cpu.iew.exec_refs 49948126 # number of memory reference insts executed -system.cpu.iew.exec_branches 14604066 # Number of branches executed -system.cpu.iew.exec_stores 21346027 # Number of stores executed -system.cpu.iew.exec_rate 2.021647 # Inst execution rate -system.cpu.iew.wb_sent 105801461 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105581404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53258894 # num instructions producing a value -system.cpu.iew.wb_consumers 103486689 # num instructions consuming a value +system.cpu.iew.exec_nop 9761 # number of nop insts executed +system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed +system.cpu.iew.exec_branches 14602542 # Number of branches executed +system.cpu.iew.exec_stores 21344564 # Number of stores executed +system.cpu.iew.exec_rate 2.076700 # Inst execution rate +system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53282087 # num instructions producing a value +system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.009150 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514645 # average fanout of values written-back +system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10979497 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 501718 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44355847 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.268752 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.766108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15312059 34.52% 34.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11621987 26.20% 60.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3450685 7.78% 68.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2867250 6.46% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1878784 4.24% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1958737 4.42% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685559 1.55% 85.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 561142 1.27% 86.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6019644 13.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44355847 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,204 +487,204 @@ system.cpu.commit.branches 13741505 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6019644 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149922829 # The number of ROB reads -system.cpu.rob.rob_writes 224870236 # The number of ROB writes -system.cpu.timesIdled 74082 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6557492 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149959303 # The number of ROB reads +system.cpu.rob.rob_writes 224865260 # The number of ROB writes +system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.741109 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.741109 # CPI: Total CPI of All Threads -system.cpu.ipc 1.349329 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.349329 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511669135 # number of integer regfile reads -system.cpu.int_regfile_writes 103349973 # number of integer regfile writes -system.cpu.fp_regfile_reads 690 # number of floating regfile reads -system.cpu.fp_regfile_writes 602 # number of floating regfile writes -system.cpu.misc_regfile_reads 49186281 # number of misc regfile reads +system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads +system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511661177 # number of integer regfile reads +system.cpu.int_regfile_writes 103341315 # number of integer regfile writes +system.cpu.fp_regfile_reads 804 # number of floating regfile reads +system.cpu.fp_regfile_writes 688 # number of floating regfile writes +system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 29504 # number of replacements -system.cpu.icache.tagsinuse 1815.541660 # Cycle average of tags in use -system.cpu.icache.total_refs 11653533 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31535 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 369.542825 # Average number of references to valid blocks. +system.cpu.icache.replacements 28586 # number of replacements +system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use +system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1815.541660 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886495 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886495 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11653539 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11653539 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11653539 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11653539 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11653539 # number of overall hits -system.cpu.icache.overall_hits::total 11653539 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35502 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35502 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35502 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35502 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35502 # number of overall misses -system.cpu.icache.overall_misses::total 35502 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 704211999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 704211999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 704211999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 704211999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 704211999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 704211999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11689041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11689041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11689041 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11689041 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11689041 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11689041 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003037 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003037 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003037 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003037 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003037 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003037 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19835.840206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19835.840206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19835.840206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19835.840206 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits +system.cpu.icache.overall_hits::total 11645446 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses +system.cpu.icache.overall_misses::total 34686 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 96.590909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3638 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3638 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3638 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3638 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3638 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3638 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31864 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31864 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31864 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31864 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31864 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31864 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 575585499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 575585499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 575585499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 575585499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 575585499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 575585499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002726 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002726 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8227454893 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8443777804 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216322911 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8227454893 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8443777804 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394097 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305382 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.949853 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.949853 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955504 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955504 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763949 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.664386 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763949 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.664386 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46441.157364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63081.982283 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60157.185571 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10046.024845 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10046.024845 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66982.456844 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66982.456844 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83944 # number of writebacks +system.cpu.l2cache.writebacks::total 83944 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26522 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128779 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251333698 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209966181 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461299879 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5384861495 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5384861495 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251333698 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.939759 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.939759 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53922.698563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55348.162527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55097.650215 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52660.077012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52660.077012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158352 # number of replacements -system.cpu.dcache.tagsinuse 4073.285602 # Cycle average of tags in use -system.cpu.dcache.total_refs 44355767 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.045941 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 278219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.285602 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994454 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994454 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26058145 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26058145 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18265070 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18265070 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15998 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15998 # number of LoadLockedReq hits +system.cpu.dcache.replacements 158328 # number of replacements +system.cpu.dcache.tagsinuse 4072.315266 # Cycle average of tags in use +system.cpu.dcache.total_refs 44370475 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.176840 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.315266 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44323215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44323215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44323215 # number of overall hits -system.cpu.dcache.overall_hits::total 44323215 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124984 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124984 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1584831 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1584831 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1709815 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1709815 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1709815 # number of overall misses -system.cpu.dcache.overall_misses::total 1709815 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4634379500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4634379500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 120528782979 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 120528782979 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 848000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 848000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 125163162479 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 125163162479 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 125163162479 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 125163162479 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26183129 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26183129 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44337922 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44337922 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits +system.cpu.dcache.overall_hits::total 44337922 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses +system.cpu.dcache.overall_misses::total 1707147 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16039 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16039 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46033030 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46033030 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46033030 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46033030 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004773 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004773 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002556 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002556 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037143 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037143 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037143 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037143 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37079.782212 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37079.782212 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76051.505163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76051.505163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20682.926829 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20682.926829 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73202.751455 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73202.751455 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3167 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 649 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.784173 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 43.266667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129085 # number of writebacks -system.cpu.dcache.writebacks::total 129085 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69523 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1547028 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1547028 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1547028 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1547028 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55461 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55461 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107326 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107326 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162787 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162787 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162787 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162787 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2049044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2049044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8282203488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8282203488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10331247488 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10331247488 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10331247488 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10331247488 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36945.673536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36945.673536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77168.658927 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77168.658927 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks +system.cpu.dcache.writebacks::total 129109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 2c8c2e903..bbfef95ab 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.985090 # Number of seconds simulated -sim_ticks 985089830500 # Number of ticks simulated -final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.993559 # Number of seconds simulated +sim_ticks 993559170500 # Number of ticks simulated +final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87940 # Simulator instruction rate (inst/s) -host_op_rate 87940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47603973 # Simulator tick rate (ticks/s) -host_mem_usage 516412 # Number of bytes of host memory used -host_seconds 20693.44 # Real time elapsed on the host +host_inst_rate 148425 # Simulator instruction rate (inst/s) +host_op_rate 148425 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 81036604 # Simulator tick rate (ticks/s) +host_mem_usage 464668 # Number of bytes of host memory used +host_seconds 12260.62 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125364992 # Number of bytes read from this memory -system.physmem.bytes_read::total 125419968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory -system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959687 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 127262497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 127318306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 66141704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 66141704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 66141704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 127262497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193460010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959687 # Total number of read requests seen -system.physmem.writeReqs 1018055 # Total number of write requests seen -system.physmem.cpureqs 2977742 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125419968 # Total number of bytes read from memory -system.physmem.bytesWritten 65155520 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125419968 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() +system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 126177745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 126233078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 65578089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 65578089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 65578089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 126177745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959688 # Total number of read requests seen +system.physmem.writeReqs 1018058 # Total number of write requests seen +system.physmem.cpureqs 2977859 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125420032 # Total number of bytes read from memory +system.physmem.bytesWritten 65155712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 122602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 122610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123177 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63395 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 65307 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122179 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 121801 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 121647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 123761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 121052 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 121884 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121113 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125175 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 123789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123937 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63764 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64028 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63369 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63391 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63292 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 985089778500 # Total gap between requests +system.physmem.numWrRetry 113 # Number of times wr buffer was full causing retry +system.physmem.totGap 993559118500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959687 # Categorize read packet sizes +system.physmem.readPktSize::6 1959688 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1018055 # categorize write packet sizes +system.physmem.writePktSize::6 1018171 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1651728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44262 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19640844571 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85229742571 # Sum of mem lat for all requests -system.physmem.totBusLat 7836420000 # Total cycles spent in databus access -system.physmem.totBankLat 57752478000 # Total cycles spent in bank access -system.physmem.avgQLat 10025.42 # Average queueing delay per request -system.physmem.avgBankLat 29479.01 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43504.43 # Average memory access latency -system.physmem.avgRdBW 127.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 66.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 127.32 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 66.14 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.09 # Average read queue length over time -system.physmem.avgWrQLen 10.28 # Average write queue length over time -system.physmem.readRowHits 834572 # Number of row buffer hits during reads -system.physmem.writeRowHits 194113 # Number of row buffer hits during writes -system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes -system.physmem.avgGap 330817.71 # Average gap between requests -system.cpu.branchPred.lookups 326556831 # Number of BP lookups -system.cpu.branchPred.condPredicted 252596788 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138232865 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 218937552 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135479530 # Number of BTB hits +system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests +system.physmem.totBusLat 9795530000 # Total cycles spent in databus access +system.physmem.totBankLat 58644685000 # Total cycles spent in bank access +system.physmem.avgQLat 18298.46 # Average queueing delay per request +system.physmem.avgBankLat 29934.41 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 53232.87 # Average memory access latency +system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 65.58 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 1.50 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.10 # Average read queue length over time +system.physmem.avgWrQLen 10.46 # Average write queue length over time +system.physmem.readRowHits 770935 # Number of row buffer hits during reads +system.physmem.writeRowHits 285714 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes +system.physmem.avgGap 333661.47 # Average gap between requests +system.cpu.branchPred.lookups 326540496 # Number of BP lookups +system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.880444 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.613527 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444784566 # DTB read hits +system.cpu.dtb.read_hits 444796007 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449681644 # DTB read accesses -system.cpu.dtb.write_hits 160833172 # DTB write hits +system.cpu.dtb.read_accesses 449693085 # DTB read accesses +system.cpu.dtb.write_hits 160833351 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534476 # DTB write accesses -system.cpu.dtb.data_hits 605617738 # DTB hits +system.cpu.dtb.write_accesses 162534655 # DTB write accesses +system.cpu.dtb.data_hits 605629358 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612216120 # DTB accesses -system.cpu.itb.fetch_hits 231916745 # ITB hits +system.cpu.dtb.data_accesses 612227740 # DTB accesses +system.cpu.itb.fetch_hits 232025962 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231916767 # ITB accesses +system.cpu.itb.fetch_accesses 232025984 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,34 +234,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1970179662 # number of cpu cycles simulated +system.cpu.numCycles 1987118342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043822969 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651716748 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617888959 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120522099 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11112308 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131634407 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83565858 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.168329 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139351244 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884568 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83550128 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.175613 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139371391 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1741570972 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7474606 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 398498363 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571681299 # Number of cycles cpu stages are processed. -system.cpu.activity 79.773501 # Percentage of cycles cpu is active +system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed. +system.cpu.activity 79.100703 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -273,191 +273,191 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.082647 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.091955 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.082647 # CPI: Total CPI of All Threads -system.cpu.ipc 0.923662 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.091955 # CPI: Total CPI of All Threads +system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.923662 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 783567133 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186612529 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.228646 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1036391021 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933788641 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.396116 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 997796043 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972383619 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.355073 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1560555740 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409623922 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.791196 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 948846788 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021332874 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.839581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.601881 # Cycle average of tags in use -system.cpu.icache.total_refs 231915637 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use +system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269983.279395 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.601881 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325977 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325977 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231915637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231915637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231915637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231915637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231915637 # number of overall hits -system.cpu.icache.overall_hits::total 231915637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses -system.cpu.icache.overall_misses::total 1108 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59929000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59929000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59929000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59929000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59929000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59929000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231916745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231916745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231916745 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231916745 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231916745 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231916745 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits +system.cpu.icache.overall_hits::total 232024853 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses +system.cpu.icache.overall_misses::total 1109 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232025962 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781299 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781299 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958828 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1959687 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958829 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959688 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958828 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1959687 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35585421 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39571189 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68487354640 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68526925829 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56485658700 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56485658700 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39571189 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124973013340 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 125012584529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39571189 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124973013340 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 125012584529 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41426.566938 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51972.495373 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51964.807812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57536.719982 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57536.719982 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46066.576251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58161.876674 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58153.059668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72297.108661 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72297.108661 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107378 # number of replacements -system.cpu.dcache.tagsinuse 4082.173275 # Cycle average of tags in use -system.cpu.dcache.total_refs 593539212 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111474 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.141953 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12614691000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.173275 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996624 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996624 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268752 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268752 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156270460 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156270460 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593539212 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195351556000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195351556000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 355675180500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 355675180500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 355675180500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 355675180500 # number of overall miss cycles +system.cpu.dcache.replacements 9107372 # number of replacements +system.cpu.dcache.tagsinuse 4082.262475 # Cycle average of tags in use +system.cpu.dcache.total_refs 593512880 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111468 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.139106 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156244122 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156244122 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593512880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593512880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593512880 # number of overall hits +system.cpu.dcache.overall_hits::total 593512880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326905 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 369795252000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 369795252000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -556,54 +556,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027736 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027736 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21881.475631 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21881.475631 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43820.034894 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43820.034894 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30180.449638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30180.449638 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9247830 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4818517 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 358256 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65602 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.813469 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 73.450764 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.036924 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.036924 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.324339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.324339 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31308.638476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31308.638476 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13465460 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4770860 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 372579 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693296 # number of writebacks -system.cpu.dcache.writebacks::total 3693296 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104633 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104633 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568846 # 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number of writebacks +system.cpu.dcache.writebacks::total 3693293 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889185 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -612,14 +612,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19940.512398 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19940.512398 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35981.075018 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35981.075018 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index c63a4e0f8..db2985766 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.655920 # Number of seconds simulated -sim_ticks 655919824500 # Number of ticks simulated -final_tick 655919824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.665563 # Number of seconds simulated +sim_ticks 665562897500 # Number of ticks simulated +final_tick 665562897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111017 # Simulator instruction rate (inst/s) -host_op_rate 111017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41944886 # Simulator tick rate (ticks/s) -host_mem_usage 517560 # Number of bytes of host memory used -host_seconds 15637.66 # Real time elapsed on the host +host_inst_rate 181531 # Simulator instruction rate (inst/s) +host_op_rate 181531 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69595242 # Simulator tick rate (ticks/s) +host_mem_usage 467736 # Number of bytes of host memory used +host_seconds 9563.34 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125796416 # Number of bytes read from this memory -system.physmem.bytes_read::total 125857920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65262592 # Number of bytes written to this memory -system.physmem.bytes_written::total 65262592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965569 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966530 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019728 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019728 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 191786269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 191880037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 99497819 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 99497819 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 99497819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 191786269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 291377856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966530 # Total number of read requests seen -system.physmem.writeReqs 1019728 # Total number of write requests seen -system.physmem.cpureqs 2986258 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125857920 # Total number of bytes read from memory -system.physmem.bytesWritten 65262592 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125857920 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65262592 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 571 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125801472 # Number of bytes read from this memory +system.physmem.bytes_read::total 125863104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65262912 # Number of bytes written to this memory +system.physmem.bytes_written::total 65262912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965648 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966611 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019733 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019733 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 189015152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 189107753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98056716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98056716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98056716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 189015152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 287164469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966611 # Total number of read requests seen +system.physmem.writeReqs 1019733 # Total number of write requests seen +system.physmem.cpureqs 2988993 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125863104 # Total number of bytes read from memory +system.physmem.bytesWritten 65262912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125863104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65262912 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 562 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 123004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123537 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 123239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124908 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122835 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 123027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 122324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123664 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63503 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63256 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63532 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 64078 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64812 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64564 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 122306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 124220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122580 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120700 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 121417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121462 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 124270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 123173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 124451 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62392 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63122 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63842 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63461 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63474 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63840 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63360 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64652 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63751 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64373 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 655919756000 # Total gap between requests +system.physmem.numWrRetry 2649 # Number of times wr buffer was full causing retry +system.physmem.totGap 665562829000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966530 # Categorize read packet sizes +system.physmem.readPktSize::6 1966611 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1019728 # categorize write packet sizes +system.physmem.writePktSize::6 1022382 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1634092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 26268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1625792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 77536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44320 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 44336 # Wh system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 20705208242 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85868216242 # Sum of mem lat for all requests -system.physmem.totBusLat 7863836000 # Total cycles spent in databus access -system.physmem.totBankLat 57299172000 # Total cycles spent in bank access -system.physmem.avgQLat 10531.86 # Average queueing delay per request -system.physmem.avgBankLat 29145.66 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43677.52 # Average memory access latency -system.physmem.avgRdBW 191.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 99.50 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 191.88 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 99.50 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.82 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 10.55 # Average write queue length over time -system.physmem.readRowHits 840760 # Number of row buffer hits during reads -system.physmem.writeRowHits 193886 # Number of row buffer hits during writes -system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.01 # Row buffer hit rate for writes -system.physmem.avgGap 219646.04 # Average gap between requests -system.cpu.branchPred.lookups 381024003 # Number of BP lookups -system.cpu.branchPred.condPredicted 296029232 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16079219 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 261934224 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259237388 # Number of BTB hits +system.physmem.totQLat 34363983237 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102498683237 # Sum of mem lat for all requests +system.physmem.totBusLat 9830245000 # Total cycles spent in databus access +system.physmem.totBankLat 58304455000 # Total cycles spent in bank access +system.physmem.avgQLat 17478.70 # Average queueing delay per request +system.physmem.avgBankLat 29655.65 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 52134.35 # Average memory access latency +system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.24 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 10.79 # Average write queue length over time +system.physmem.readRowHits 776053 # Number of row buffer hits during reads +system.physmem.writeRowHits 286138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes +system.physmem.avgGap 222868.77 # Average gap between requests +system.cpu.branchPred.lookups 381322658 # Number of BP lookups +system.cpu.branchPred.condPredicted 296346711 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16069927 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262182430 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259521497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.970415 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24703724 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3041 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.985083 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24701305 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3076 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613741491 # DTB read hits -system.cpu.dtb.read_misses 11247891 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 624989382 # DTB read accesses -system.cpu.dtb.write_hits 212247245 # DTB write hits -system.cpu.dtb.write_misses 7144332 # DTB write misses +system.cpu.dtb.read_hits 613798645 # DTB read hits +system.cpu.dtb.read_misses 11251599 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 625050244 # DTB read accesses +system.cpu.dtb.write_hits 212271089 # DTB write hits +system.cpu.dtb.write_misses 7143652 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219391577 # DTB write accesses -system.cpu.dtb.data_hits 825988736 # DTB hits -system.cpu.dtb.data_misses 18392223 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 844380959 # DTB accesses -system.cpu.itb.fetch_hits 390708850 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.write_accesses 219414741 # DTB write accesses +system.cpu.dtb.data_hits 826069734 # DTB hits +system.cpu.dtb.data_misses 18395251 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 844464985 # DTB accesses +system.cpu.itb.fetch_hits 390709896 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390708888 # ITB accesses +system.cpu.itb.fetch_accesses 390709940 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,139 +234,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1311839650 # number of cpu cycles simulated +system.cpu.numCycles 1331125796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402148068 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3157560086 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381024003 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 283941112 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 573880213 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140086808 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 165153102 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390708850 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8061624 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1257505437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.510971 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.156516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402151320 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3159313188 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381322658 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284222802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574163176 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140279243 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 173671179 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390709896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8056983 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1266457048 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152796 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 683625224 54.36% 54.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42619367 3.39% 57.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21744894 1.73% 59.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39684878 3.16% 62.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129121337 10.27% 72.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61516601 4.89% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38545793 3.07% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28125558 2.24% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212521785 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692293872 54.66% 54.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42630313 3.37% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21744461 1.72% 59.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39673370 3.13% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129246893 10.21% 73.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61513639 4.86% 77.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38552077 3.04% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28113770 2.22% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212688653 16.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1257505437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.290450 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.406971 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433733980 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 146719588 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542274905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18455051 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116321913 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58305735 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 954 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3085307728 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2035 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116321913 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456557347 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 93252503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5104 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535232007 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56136563 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3003562340 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 560555 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1735251 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50037437 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2245657329 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3895152131 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3893909248 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1242883 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1266457048 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286466 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.373414 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433835858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 155176701 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542390430 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18584911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116469148 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58290582 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 824 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3086789571 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2029 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116469148 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456704578 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 101399871 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7042 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535436988 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56439421 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3004825157 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 566473 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1727265 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50367655 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2246602827 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3897066108 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3895827965 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1238143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 869454366 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 190 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 189 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 120669951 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679225578 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255273844 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68130212 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37368209 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2722510883 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 144 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508555980 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3078936 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 977267031 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 413974741 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 115 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1257505437 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.994867 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.973352 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 870399864 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 162 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 161 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121306422 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679329311 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255341435 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67772546 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36892101 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2723405673 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508908939 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3097394 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978157995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 414914582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1266457048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981045 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.973109 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 417762073 33.22% 33.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201459942 16.02% 49.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185268981 14.73% 63.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153261704 12.19% 76.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133079768 10.58% 86.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81048988 6.45% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65262511 5.19% 98.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15257874 1.21% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5103596 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 426262331 33.66% 33.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201879469 15.94% 49.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185440300 14.64% 64.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153069981 12.09% 76.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133127020 10.51% 86.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81075751 6.40% 93.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65263497 5.15% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15238482 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5100217 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1257505437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1266457048 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2150864 11.67% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11870466 64.42% 76.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4405017 23.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2147356 11.64% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11882629 64.43% 76.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4412064 23.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643219876 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643457358 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 108 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 253 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 38 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued @@ -388,84 +388,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641326950 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224008572 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641426814 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224024134 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508555980 # Type of FU issued -system.cpu.iq.rate 1.912243 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18426347 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007345 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6294223850 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3698666551 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412312770 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1898830 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1217307 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 851008 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526043830 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938497 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62613731 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508908939 # Type of FU issued +system.cpu.iq.rate 1.884802 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18442049 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6303917077 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3700456251 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412530118 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1897292 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1213669 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850482 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526413076 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 937912 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62601543 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234629915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264851 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107543 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94545342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234733648 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263681 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107887 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94612933 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 100 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1452143 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 149 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1508556 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116321913 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 41870148 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1143259 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2864507060 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8845706 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679225578 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255273844 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 144 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 295805 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17199 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107543 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10354551 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8556122 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18910673 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461271813 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 624989902 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47284167 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116469148 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45249808 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153798 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2865411802 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8865893 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679329311 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255341435 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 296621 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17062 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107887 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10351897 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8549059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18900956 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461552831 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625050873 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47356108 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141996033 # number of nop insts executed -system.cpu.iew.exec_refs 844381512 # number of memory reference insts executed -system.cpu.iew.exec_branches 300766985 # Number of branches executed -system.cpu.iew.exec_stores 219391610 # Number of stores executed -system.cpu.iew.exec_rate 1.876199 # Inst execution rate -system.cpu.iew.wb_sent 2441119325 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413163778 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388569148 # num instructions producing a value -system.cpu.iew.wb_consumers 1764314853 # num instructions consuming a value +system.cpu.iew.exec_nop 142006007 # number of nop insts executed +system.cpu.iew.exec_refs 844465652 # number of memory reference insts executed +system.cpu.iew.exec_branches 300780520 # Number of branches executed +system.cpu.iew.exec_stores 219414779 # Number of stores executed +system.cpu.iew.exec_rate 1.849226 # Inst execution rate +system.cpu.iew.wb_sent 2441340597 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413380600 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388547079 # num instructions producing a value +system.cpu.iew.wb_consumers 1764258867 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.839526 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.787030 # average fanout of values written-back +system.cpu.iew.wb_rate 1.813037 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787043 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 823556826 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 824496541 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16078403 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1141183524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.594643 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.519930 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16069169 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1149987900 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.582434 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 628040121 55.03% 55.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174132211 15.26% 70.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86354537 7.57% 77.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53988637 4.73% 82.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34269513 3.00% 85.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24750272 2.17% 87.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22050678 1.93% 89.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22940990 2.01% 91.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94656565 8.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 636582703 55.36% 55.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174528815 15.18% 70.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86154838 7.49% 78.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53696009 4.67% 82.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34510870 3.00% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25214106 2.19% 87.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21871895 1.90% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22921084 1.99% 91.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94507580 8.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1141183524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1149987900 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,189 +476,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94656565 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94507580 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3604084711 # The number of ROB reads -system.cpu.rob.rob_writes 5403096067 # The number of ROB writes -system.cpu.timesIdled 804666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54334213 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3613977787 # The number of ROB reads +system.cpu.rob.rob_writes 5405122718 # The number of ROB writes +system.cpu.timesIdled 818240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64668748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.755649 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755649 # CPI: Total CPI of All Threads -system.cpu.ipc 1.323366 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.323366 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3316903206 # number of integer regfile reads -system.cpu.int_regfile_writes 1931453212 # number of integer regfile writes -system.cpu.fp_regfile_reads 30791 # number of floating regfile reads -system.cpu.fp_regfile_writes 509 # number of floating regfile writes +system.cpu.cpi 0.766758 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.766758 # CPI: Total CPI of All Threads +system.cpu.ipc 1.304192 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.304192 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317304663 # number of integer regfile reads +system.cpu.int_regfile_writes 1931628776 # number of integer regfile writes +system.cpu.fp_regfile_reads 30090 # number of floating regfile reads +system.cpu.fp_regfile_writes 557 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 768.875728 # Cycle average of tags in use -system.cpu.icache.total_refs 390707378 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 406563.348595 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 772.264197 # Cycle average of tags in use +system.cpu.icache.total_refs 390708412 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 963 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 405720.053998 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 768.875728 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375428 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375428 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390707378 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390707378 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390707378 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390707378 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390707378 # number of overall hits -system.cpu.icache.overall_hits::total 390707378 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1472 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1472 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1472 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1472 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1472 # number of overall misses -system.cpu.icache.overall_misses::total 1472 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 78332000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 78332000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 78332000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 78332000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 78332000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 78332000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390708850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390708850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390708850 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390708850 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390708850 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390708850 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 772.264197 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377082 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377082 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390708412 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390708412 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390708412 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390708412 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390708412 # number of overall hits +system.cpu.icache.overall_hits::total 390708412 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67326.522352 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57367.845994 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67331.391317 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67326.522352 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214115 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214197 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60341.640706 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75690.842131 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75678.436545 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74939.816206 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74939.816206 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60341.640706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75394.691979 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75387.320878 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60341.640706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75394.691979 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75387.320878 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -667,160 +667,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019728 # number of writebacks -system.cpu.l2cache.writebacks::total 1019728 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190397 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191358 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775172 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775172 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965569 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965569 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43023532 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 65297790926 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65340814458 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 42150717127 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 42150717127 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43023532 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107448508053 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 107491531585 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43023532 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107448508053 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 107491531585 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019733 # number of writebacks +system.cpu.l2cache.writebacks::total 1019733 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190539 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191502 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775109 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775109 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965648 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966611 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965648 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966611 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46150301 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 75292068672 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75338218973 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48421097021 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48421097021 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46150301 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 123713165693 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 123759315994 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46150301 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 123713165693 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 123759315994 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163144 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163255 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411546 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411546 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163270 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411509 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214193 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214115 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214197 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214193 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44769.544225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54853.793252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54845.658868 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54375.954146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54375.954146 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44769.544225 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54665.345278 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54660.509418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44769.544225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54665.345278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54660.509418 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214115 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214197 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47923.469367 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63242.001037 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63229.620238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62470.048756 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62470.048756 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47923.469367 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62937.599048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62930.247006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47923.469367 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62937.599048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62930.247006 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176047 # number of replacements -system.cpu.dcache.tagsinuse 4087.418525 # Cycle average of tags in use -system.cpu.dcache.total_refs 694335392 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.634485 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5062814000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.418525 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997905 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997905 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538685115 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538685115 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155650275 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155650275 # number of WriteReq hits +system.cpu.dcache.replacements 9176263 # number of replacements +system.cpu.dcache.tagsinuse 4087.522413 # Cycle average of tags in use +system.cpu.dcache.total_refs 694338200 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180359 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.633012 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.522413 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538691860 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538691860 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155646338 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155646338 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694335390 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694335390 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694335390 # number of overall hits -system.cpu.dcache.overall_hits::total 694335390 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11273608 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11273608 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5078227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5078227 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 694338198 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694338198 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694338198 # number of overall hits +system.cpu.dcache.overall_hits::total 694338198 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11282428 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11282428 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5082164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5082164 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16351835 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16351835 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16351835 # number of overall misses -system.cpu.dcache.overall_misses::total 16351835 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 280031703000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 280031703000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 217034506033 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 217034506033 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 48500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 48500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 497066209033 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 497066209033 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 497066209033 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 497066209033 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549958723 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549958723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16364592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16364592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16364592 # number of overall misses +system.cpu.dcache.overall_misses::total 16364592 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 295012100000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 295012100000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 224191521595 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 224191521595 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 431500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 431500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 519203621595 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 519203621595 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 519203621595 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 519203621595 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549974288 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549974288 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710687225 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710687225 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710687225 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710687225 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020499 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020499 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031595 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031595 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 710702790 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710702790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710702790 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710702790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020514 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020514 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031620 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023008 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023008 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023008 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023008 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24839.581348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24839.581348 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42738.244280 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42738.244280 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30398.191337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30398.191337 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10428893 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5642690 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 733632 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023026 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023026 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023026 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023026 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26147.926670 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26147.926670 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44113.397678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44113.397678 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 431500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 431500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31727.257337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31727.257337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12329196 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5816488 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 735313 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.215428 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 86.632020 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.767276 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.300335 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724933 # number of writebacks -system.cpu.dcache.writebacks::total 3724933 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3977017 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3977017 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3194676 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3194676 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7171693 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7171693 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7171693 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7171693 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883551 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725054 # number of writebacks +system.cpu.dcache.writebacks::total 3725054 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985636 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3985636 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198598 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3198598 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7184234 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7184234 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7184234 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7184234 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296792 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296792 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883566 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883566 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149546401000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 149546401000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65349746897 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 65349746897 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 46500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 46500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214896147897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 214896147897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214896147897 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180358 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180358 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180358 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180358 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159255490500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 159255490500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71503545346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71503545346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 429500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 429500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230759035846 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230759035846 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230759035846 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230759035846 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses @@ -831,16 +831,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20495.379418 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20495.379418 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34694.970774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34694.970774 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 46500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 46500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.411839 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.411839 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37961.794461 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37961.794461 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 429500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 429500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index fe1996e1b..fe58c49f1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.506354 # Number of seconds simulated -sim_ticks 506353996500 # Number of ticks simulated -final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517386 # Number of seconds simulated +sim_ticks 517386177000 # Number of ticks simulated +final_tick 517386177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105319 # Simulator instruction rate (inst/s) -host_op_rate 117491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34526611 # Simulator tick rate (ticks/s) -host_mem_usage 552892 # Number of bytes of host memory used -host_seconds 14665.62 # Real time elapsed on the host +host_inst_rate 165493 # Simulator instruction rate (inst/s) +host_op_rate 184620 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55435711 # Simulator tick rate (ticks/s) +host_mem_usage 502788 # Number of bytes of host memory used +host_seconds 9333.08 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143771904 # Number of bytes read from this memory -system.physmem.bytes_read::total 143819904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143728256 # Number of bytes read from this memory +system.physmem.bytes_read::total 143776256 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70451968 # Number of bytes written to this memory -system.physmem.bytes_written::total 70451968 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 70436224 # Number of bytes written to this memory +system.physmem.bytes_written::total 70436224 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2246436 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2247186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100812 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100812 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283935557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 284030352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 139135799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 139135799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 139135799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283935557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 423166152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2247186 # Total number of read requests seen -system.physmem.writeReqs 1100812 # Total number of write requests seen -system.physmem.cpureqs 3347998 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143819904 # Total number of bytes read from memory -system.physmem.bytesWritten 70451968 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143819904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70451968 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 672 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 2245754 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246504 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100566 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100566 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277796861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 277889635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136138589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136138589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136138589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277796861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 414028224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246504 # Total number of read requests seen +system.physmem.writeReqs 1100566 # Total number of write requests seen +system.physmem.cpureqs 3350665 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143776256 # Total number of bytes read from memory +system.physmem.bytesWritten 70436224 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143776256 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70436224 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 651 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139825 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 143804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141798 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 137923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 141349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 139500 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 137255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 141125 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 138862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 139997 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 70413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 68873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 67768 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68477 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 68286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 68308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 68629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 68528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 67273 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70384 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68935 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 141458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 139475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 142337 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 139999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140517 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 138551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 136478 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 141026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 139159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 141757 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69121 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 68349 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69281 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 69052 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 67825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 67029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69533 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 69105 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 68630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68911 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 506353933500 # Total gap between requests +system.physmem.numWrRetry 3595 # Number of times wr buffer was full causing retry +system.physmem.totGap 517386097500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2247186 # Categorize read packet sizes +system.physmem.readPktSize::6 2246504 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1100812 # categorize write packet sizes +system.physmem.writePktSize::6 1104161 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1577555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 446581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 156376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 65982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1563469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 451045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68688 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,69 +138,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 44097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 27009597750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102747541750 # Sum of mem lat for all requests -system.physmem.totBusLat 8986056000 # Total cycles spent in databus access -system.physmem.totBankLat 66751888000 # Total cycles spent in bank access -system.physmem.avgQLat 12022.89 # Average queueing delay per request -system.physmem.avgBankLat 29713.54 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45736.44 # Average memory access latency -system.physmem.avgRdBW 284.03 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 139.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 284.03 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 139.14 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.64 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 914505 # Number of row buffer hits during reads -system.physmem.writeRowHits 189005 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes -system.physmem.avgGap 151240.81 # Average gap between requests -system.cpu.branchPred.lookups 301930111 # Number of BP lookups -system.cpu.branchPred.condPredicted 248173247 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15201095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 171785530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 160276899 # Number of BTB hits +system.physmem.totQLat 51687050307 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 131176334057 # Sum of mem lat for all requests +system.physmem.totBusLat 11229265000 # Total cycles spent in databus access +system.physmem.totBankLat 68260018750 # Total cycles spent in bank access +system.physmem.avgQLat 23014.44 # Average queueing delay per request +system.physmem.avgBankLat 30393.81 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58408.25 # Average memory access latency +system.physmem.avgRdBW 277.89 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 277.89 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.23 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.25 # Average read queue length over time +system.physmem.avgWrQLen 10.38 # Average write queue length over time +system.physmem.readRowHits 827421 # Number of row buffer hits during reads +system.physmem.writeRowHits 271011 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 24.62 # Row buffer hit rate for writes +system.physmem.avgGap 154578.81 # Average gap between requests +system.cpu.branchPred.lookups 303247532 # Number of BP lookups +system.cpu.branchPred.condPredicted 249450034 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15218023 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 175041543 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161435617 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.300582 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17551988 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.227030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17558020 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 197 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,237 +244,238 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1012707994 # number of cpu cycles simulated +system.cpu.numCycles 1034772355 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 177828887 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433076308 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 86433742 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 153009166 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 286734480 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5522368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 951217236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.532975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216056 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298171037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2186159989 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303247532 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 178993637 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435067157 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87822274 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155469980 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 288529454 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5728473 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958589014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.523348 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.213310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 518141000 54.47% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25031243 2.63% 57.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39020791 4.10% 61.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48260411 5.07% 66.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42551008 4.47% 70.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46329866 4.87% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38408585 4.04% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18543654 1.95% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174930678 18.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 523521931 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25504837 2.66% 57.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39086427 4.08% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48350867 5.04% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43002654 4.49% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46446539 4.85% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38408277 4.01% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18709630 1.95% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175557852 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 951217236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298141 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.149522 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327471231 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 131306156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403441377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20045518 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68952954 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46012127 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2358019040 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68952954 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 350612417 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61250936 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16584 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 398830274 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71554071 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2297211554 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 127534 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5036199 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58405264 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2272168650 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10608574023 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10608571065 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2958 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958589014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293057 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.112697 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 329732299 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 133726687 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405163333 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20087198 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69879497 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46055159 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 678 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2366957956 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2458 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69879497 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 353264569 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63487571 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18775 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400193247 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71745355 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2304463172 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133379 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5038858 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58609164 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2279851599 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10642208168 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10642204755 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3413 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 565848720 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 855 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 852 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158388501 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 623121269 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220470896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86042540 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70771050 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2196546407 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 888 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016009796 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3969588 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 468927262 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1107841980 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 718 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 951217236 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.119400 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 573531669 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 681 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 678 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158828994 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624462299 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220966139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86157140 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71007424 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2201342631 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 714 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018151759 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3999657 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 473702297 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1125076843 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 544 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958589014 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.105336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906417 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 271448438 28.54% 28.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 150881497 15.86% 44.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160823100 16.91% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119315575 12.54% 73.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124031902 13.04% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73881034 7.77% 94.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38429694 4.04% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9823536 1.03% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2582460 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277560944 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151408943 15.79% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161184316 16.81% 61.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119741050 12.49% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124054843 12.94% 87.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73850392 7.70% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38407609 4.01% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9813288 1.02% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2567629 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 951217236 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958589014 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 875964 3.67% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5764 0.02% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18242361 76.45% 80.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4736544 19.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872793 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5710 0.02% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18283969 76.42% 80.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4762893 19.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1235492979 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925544 0.05% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 40 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 586540633 29.09% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193050569 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236667909 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925774 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587469094 29.11% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193088896 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016009796 # Type of FU issued -system.cpu.iq.rate 1.990712 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23860633 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011836 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5011066759 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2665664471 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1956606463 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 290 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2039870285 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64705720 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018151759 # Type of FU issued +system.cpu.iq.rate 1.950334 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23925365 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011855 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5022817228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2675235301 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957490366 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042076961 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 163 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64626006 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 137194500 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 273797 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192943 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45623851 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138535530 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 270863 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192819 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46119094 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3807412 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4653355 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68952954 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27155997 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1495704 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2196547422 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6100181 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 623121269 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220470896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 826 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 473871 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 90052 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192943 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8142096 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9608050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17750146 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986410888 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573023734 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29598908 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69879497 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28935964 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1499081 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2201343583 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6151222 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624462299 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220966139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 652 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 473850 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 90091 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192819 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8153540 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9614603 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17768143 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988132356 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573881676 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30019403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 127 # number of nop insts executed -system.cpu.iew.exec_refs 763190345 # number of memory reference insts executed -system.cpu.iew.exec_branches 238305534 # Number of branches executed -system.cpu.iew.exec_stores 190166611 # Number of stores executed -system.cpu.iew.exec_rate 1.961484 # Inst execution rate -system.cpu.iew.wb_sent 1965043499 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1956606576 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295701772 # num instructions producing a value -system.cpu.iew.wb_consumers 2060221208 # num instructions consuming a value +system.cpu.iew.exec_nop 238 # number of nop insts executed +system.cpu.iew.exec_refs 764075762 # number of memory reference insts executed +system.cpu.iew.exec_branches 238335526 # Number of branches executed +system.cpu.iew.exec_stores 190194086 # Number of stores executed +system.cpu.iew.exec_rate 1.921323 # Inst execution rate +system.cpu.iew.wb_sent 1965930006 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957490498 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296385031 # num instructions producing a value +system.cpu.iew.wb_consumers 2061135459 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.932054 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628914 # average fanout of values written-back +system.cpu.iew.wb_rate 1.891711 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 473572340 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 478367692 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15200427 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882264282 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733344 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15217365 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888709517 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.938849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727981 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 395036396 44.78% 44.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 191994213 21.76% 66.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72477507 8.21% 74.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35260039 4.00% 78.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18947912 2.15% 80.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30765236 3.49% 84.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20067867 2.27% 86.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11401417 1.29% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106313695 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 401294450 45.15% 45.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192123349 21.62% 66.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72572906 8.17% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35244916 3.97% 78.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18969010 2.13% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30763331 3.46% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20056672 2.26% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11441847 1.29% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106243036 11.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882264282 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888709517 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -485,192 +486,192 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106313695 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106243036 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2972596181 # The number of ROB reads -system.cpu.rob.rob_writes 4462393115 # The number of ROB writes -system.cpu.timesIdled 1008109 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61490758 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2983907427 # The number of ROB reads +system.cpu.rob.rob_writes 4472910463 # The number of ROB writes +system.cpu.timesIdled 1017511 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76183341 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.655660 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.655660 # CPI: Total CPI of All Threads -system.cpu.ipc 1.525181 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.525181 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9949148949 # number of integer regfile reads -system.cpu.int_regfile_writes 1936492974 # number of integer regfile writes -system.cpu.fp_regfile_reads 113 # number of floating regfile reads -system.cpu.fp_regfile_writes 115 # number of floating regfile writes -system.cpu.misc_regfile_reads 737540247 # number of misc regfile reads +system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads +system.cpu.ipc 1.492660 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.492660 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956386896 # number of integer regfile reads +system.cpu.int_regfile_writes 1937427158 # number of integer regfile writes +system.cpu.fp_regfile_reads 137 # number of floating regfile reads +system.cpu.fp_regfile_writes 146 # number of floating regfile writes +system.cpu.misc_regfile_reads 737590270 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 23 # number of replacements -system.cpu.icache.tagsinuse 625.185145 # Cycle average of tags in use -system.cpu.icache.total_refs 286733320 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 778 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 368551.825193 # Average number of references to valid blocks. +system.cpu.icache.replacements 21 # number of replacements +system.cpu.icache.tagsinuse 626.247624 # Cycle average of tags in use +system.cpu.icache.total_refs 288528273 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 370382.892169 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.185145 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305266 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305266 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 286733320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286733320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286733320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286733320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286733320 # number of overall hits -system.cpu.icache.overall_hits::total 286733320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1160 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1160 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1160 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1160 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1160 # number of overall misses -system.cpu.icache.overall_misses::total 1160 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59910000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59910000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59910000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59910000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59910000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59910000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286734480 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286734480 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286734480 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286734480 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286734480 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286734480 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 626.247624 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305785 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305785 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 288528273 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288528273 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288528273 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288528273 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288528273 # number of overall hits +system.cpu.icache.overall_hits::total 288528273 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses +system.cpu.icache.overall_misses::total 1181 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66140500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66140500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66140500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66140500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66140500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66140500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288529454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288529454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288529454 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288529454 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288529454 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288529454 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51646.551724 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51646.551724 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51646.551724 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51646.551724 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56003.810330 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56003.810330 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56003.810330 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56003.810330 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56003.810330 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56003.810330 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 382 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 382 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 382 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 382 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43554500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 402 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 402 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 402 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 402 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 402 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46510000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46510000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46510000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55982.647815 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55982.647815 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59704.749679 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59704.749679 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59704.749679 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59704.749679 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59704.749679 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59704.749679 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233945 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233945 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47744.264000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67733.805495 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67723.246508 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72760.777006 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72760.777006 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9598379 # number of replacements -system.cpu.dcache.tagsinuse 4087.934747 # Cycle average of tags in use -system.cpu.dcache.total_refs 656008169 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9602475 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.316571 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3424422000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.934747 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 488954223 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 488954223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167053823 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167053823 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.replacements 9597826 # number of replacements +system.cpu.dcache.tagsinuse 4088.019917 # Cycle average of tags in use +system.cpu.dcache.total_refs 656092202 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9601922 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.329258 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3440649000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.019917 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 489045122 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489045122 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167046955 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167046955 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656008046 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656008046 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656008046 # number of overall hits -system.cpu.dcache.overall_hits::total 656008046 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11476242 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11476242 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5532224 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5532224 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656092077 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656092077 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656092077 # number of overall hits +system.cpu.dcache.overall_hits::total 656092077 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11476427 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11476427 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5539092 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5539092 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17008466 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17008466 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17008466 # number of overall misses -system.cpu.dcache.overall_misses::total 17008466 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 299283762000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 299283762000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 216949721927 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 216949721927 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 516233483927 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 516233483927 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 516233483927 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 516233483927 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500430465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500430465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17015519 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17015519 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17015519 # number of overall misses +system.cpu.dcache.overall_misses::total 17015519 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 322914399500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 322914399500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 229337265001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229337265001 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 552251664501 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 552251664501 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 552251664501 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 552251664501 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500521549 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500521549 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673016512 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673016512 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673016512 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673016512 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032055 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032055 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025272 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025272 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025272 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025272 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26078.550975 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26078.550975 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39215.643099 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39215.643099 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30351.560448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30351.560448 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19781174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 987477 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1172505 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64541 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.870865 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15.299995 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673107596 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673107596 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673107596 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673107596 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28137.189345 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28137.189345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41403.404204 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41403.404204 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32455.763736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32455.763736 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26327984 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1057907 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1182334 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64553 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.267806 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.388193 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781550 # number of writebacks -system.cpu.dcache.writebacks::total 3781550 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767179 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3767179 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638811 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3638811 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781250 # number of writebacks +system.cpu.dcache.writebacks::total 3781250 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767955 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3767955 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645642 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3645642 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7405990 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7405990 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7405990 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7405990 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709063 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7709063 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893413 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893413 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602476 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602476 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602476 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602476 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170550521000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 170550521000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71842126604 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71842126604 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242392647604 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 242392647604 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242392647604 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 242392647604 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7413597 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7413597 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7413597 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7413597 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708472 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708472 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893450 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893450 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601922 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601922 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186178488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 186178488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508071510 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508071510 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269686560010 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 269686560010 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269686560010 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 269686560010 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22123.378808 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22123.378808 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37943.188625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37943.188625 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24152.450512 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24152.450512 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44103.658143 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44103.658143 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 2877a6d58..7e4c9be17 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041615 # Number of seconds simulated -sim_ticks 41615049000 # Number of ticks simulated -final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041622 # Number of seconds simulated +sim_ticks 41622221000 # Number of ticks simulated +final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92405 # Simulator instruction rate (inst/s) -host_op_rate 92405 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41842312 # Simulator tick rate (ticks/s) -host_mem_usage 276220 # Number of bytes of host memory used -host_seconds 994.57 # Real time elapsed on the host +host_inst_rate 156492 # Simulator instruction rate (inst/s) +host_op_rate 156492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70874179 # Simulator tick rate (ticks/s) +host_mem_usage 228076 # Number of bytes of host memory used +host_seconds 587.27 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4296907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3297269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7594176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4296907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4296907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4296907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3297269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7594176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 316032 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 352 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 356 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41614997000 # Total gap between requests +system.physmem.totGap 41622168000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 17845427 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 106827427 # Sum of mem lat for all requests -system.physmem.totBusLat 19752000 # Total cycles spent in databus access -system.physmem.totBankLat 69230000 # Total cycles spent in bank access -system.physmem.avgQLat 3613.90 # Average queueing delay per request -system.physmem.avgBankLat 14019.85 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21633.74 # Average memory access latency +system.physmem.totQLat 23375922 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122137172 # Sum of mem lat for all requests +system.physmem.totBusLat 24690000 # Total cycles spent in databus access +system.physmem.totBankLat 74071250 # Total cycles spent in bank access +system.physmem.avgQLat 4733.88 # Average queueing delay per request +system.physmem.avgBankLat 15000.25 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24734.14 # Average memory access latency system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4457 # Number of row buffer hits during reads +system.physmem.readRowHits 4243 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8427500.41 # Average gap between requests -system.cpu.branchPred.lookups 13412629 # Number of BP lookups -system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted +system.physmem.avgGap 8428952.61 # Average gap between requests +system.cpu.branchPred.lookups 13412628 # Number of BP lookups +system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424481 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.757716 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996253 # DTB read hits +system.cpu.dtb.read_hits 19996247 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996263 # DTB read accesses -system.cpu.dtb.write_hits 6501863 # DTB write hits +system.cpu.dtb.read_accesses 19996257 # DTB read accesses +system.cpu.dtb.write_hits 6501860 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501886 # DTB write accesses -system.cpu.dtb.data_hits 26498116 # DTB hits +system.cpu.dtb.write_accesses 6501883 # DTB write accesses +system.cpu.dtb.data_hits 26498107 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498149 # DTB accesses -system.cpu.itb.fetch_hits 9956935 # ITB hits +system.cpu.dtb.data_accesses 26498140 # DTB accesses +system.cpu.itb.fetch_hits 9956943 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956984 # ITB accesses +system.cpu.itb.fetch_accesses 9956992 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83230099 # number of cpu cycles simulated +system.cpu.numCycles 83244443 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570549 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146019 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136146021 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521872 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 38521870 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 57404029 # Nu system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970257 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10685 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7622365 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607734 # Number of cycles cpu stages are processed. -system.cpu.activity 90.841817 # Percentage of cycles cpu is active +system.cpu.timesIdled 10691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7636719 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607724 # Number of cycles cpu stages are processed. +system.cpu.activity 90.826152 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -266,72 +266,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.905629 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.905785 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.905629 # CPI: Total CPI of All Threads -system.cpu.ipc 1.104205 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.905785 # CPI: Total CPI of All Threads +system.cpu.ipc 1.104014 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.104205 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27549736 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680363 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.899311 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33978401 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251698 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.175345 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33378776 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851323 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.895787 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65203595 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026504 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.658636 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29370403 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859696 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.711801 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.104014 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27564085 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680358 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.887778 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33992749 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251694 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.165143 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33393108 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851335 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.885481 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29384711 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 7635 # number of replacements -system.cpu.icache.tagsinuse 1492.730683 # Cycle average of tags in use -system.cpu.icache.total_refs 9945572 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1492.649363 # Cycle average of tags in use +system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1044.702941 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.730683 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728872 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728872 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9945572 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9945572 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9945572 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9945572 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9945572 # number of overall hits -system.cpu.icache.overall_hits::total 9945572 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11363 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11363 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11363 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11363 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11363 # number of overall misses -system.cpu.icache.overall_misses::total 11363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 253418000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 253418000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 253418000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 253418000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 253418000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 253418000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956935 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956935 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956935 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956935 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956935 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956935 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1492.649363 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945578 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945578 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945578 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945578 # number of overall hits +system.cpu.icache.overall_hits::total 9945578 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses +system.cpu.icache.overall_misses::total 11365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259189500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259189500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259189500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259189500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259189500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259189500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956943 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956943 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956943 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22302.032914 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22302.032914 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22302.032914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22302.032914 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22805.939287 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22805.939287 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22805.939287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22805.939287 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -340,50 +340,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1843 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1843 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1843 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1843 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1843 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1843 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204186500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 204186500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204186500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 204186500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204186500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 204186500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209613500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 209613500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209613500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 209613500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209613500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 209613500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21448.161765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21448.161765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22018.224790 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22018.224790 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2190.387059 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2190.263467 # Cycle average of tags in use system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.839462 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.429033 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.118565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.325234 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.099221 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055586 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066845 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits @@ -408,17 +408,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127130500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21966500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 149097000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79600500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 79600500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127130500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101567000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 228697500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127130500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101567000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 228697500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132557500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 156626500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84092000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84092000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 132557500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 108161000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 240718500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 132557500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 108161000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 240718500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -443,17 +443,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45501.252684 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52053.317536 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46361.007463 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46225.609756 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46225.609756 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46313.791009 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46313.791009 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47443.629205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48702.269900 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48833.914053 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48833.914053 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48748.177400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48748.177400 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91774816 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16652177 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18812201 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116655537 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63127136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63127136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97843336 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81939337 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 179782673 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97843336 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81939337 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 179782673 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -495,51 +495,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32847.106657 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39460.135071 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33714.861007 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33884.375726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33884.375726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35019.089477 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44578.675355 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36273.487873 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36659.196283 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36659.196283 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.892023 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488629 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.801688 # Cycle average of tags in use +system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.712551 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.892023 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352024 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352024 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1441.801688 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488629 # number of overall hits -system.cpu.dcache.overall_hits::total 26488629 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493002 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493002 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488625 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488625 # number of overall hits +system.cpu.dcache.overall_hits::total 26488625 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8672 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8672 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8672 # number of overall misses -system.cpu.dcache.overall_misses::total 8672 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28721000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28721000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 329862500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 329862500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 358583500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 358583500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 358583500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 358583500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8101 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8101 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8676 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses +system.cpu.dcache.overall_misses::total 8676 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 345698500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 345698500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 377082000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 377082000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 377082000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 377082000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -550,25 +550,25 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49949.565217 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49949.565217 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40738.853897 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40738.853897 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41349.573339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41349.573339 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11994 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42673.558820 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42673.558820 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43462.655602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43462.655602 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 830 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.450602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.647202 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -576,12 +576,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6349 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6349 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6449 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6449 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6449 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -590,14 +590,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81618000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 81618000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 104608000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 104608000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 104608000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 104608000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86109500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86109500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 111202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111202000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 111202000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -606,14 +606,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48400 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48400 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46692.219680 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46692.219680 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49261.727689 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49261.727689 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 32c2b95d3..c7256bad9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023378 # Number of seconds simulated -sim_ticks 23378067000 # Number of ticks simulated -final_tick 23378067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023427 # Number of seconds simulated +sim_ticks 23426793000 # Number of ticks simulated +final_tick 23426793000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125836 # Simulator instruction rate (inst/s) -host_op_rate 125836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34946651 # Simulator tick rate (ticks/s) -host_mem_usage 277248 # Number of bytes of host memory used -host_seconds 668.96 # Real time elapsed on the host +host_inst_rate 213464 # Simulator instruction rate (inst/s) +host_op_rate 213464 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59405864 # Simulator tick rate (ticks/s) +host_mem_usage 230136 # Number of bytes of host memory used +host_seconds 394.35 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory system.physmem.bytes_read::total 334592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8388033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5924185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14312218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8388033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8388033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8388033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5924185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14312218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8365123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5917327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14282450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8365123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8365123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8365123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5917327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14282450 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5228 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 5228 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 334592 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 320 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 275 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 352 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 308 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 398 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23377961000 # Total gap between requests +system.physmem.totGap 23426687000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 21787213 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116311213 # Sum of mem lat for all requests -system.physmem.totBusLat 20912000 # Total cycles spent in databus access -system.physmem.totBankLat 73612000 # Total cycles spent in bank access -system.physmem.avgQLat 4167.41 # Average queueing delay per request -system.physmem.avgBankLat 14080.34 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22247.75 # Average memory access latency -system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 28657456 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 133887456 # Sum of mem lat for all requests +system.physmem.totBusLat 26140000 # Total cycles spent in databus access +system.physmem.totBankLat 79090000 # Total cycles spent in bank access +system.physmem.avgQLat 5481.53 # Average queueing delay per request +system.physmem.avgBankLat 15128.16 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25609.69 # Average memory access latency +system.physmem.avgRdBW 14.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.11 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4677 # Number of row buffer hits during reads +system.physmem.readRowHits 4452 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4471683.44 # Average gap between requests -system.cpu.branchPred.lookups 14833517 # Number of BP lookups -system.cpu.branchPred.condPredicted 10762267 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 917019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8075874 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6944735 # Number of BTB hits +system.physmem.avgGap 4481003.63 # Average gap between requests +system.cpu.branchPred.lookups 14862899 # Number of BP lookups +system.cpu.branchPred.condPredicted 10784279 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 925607 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8448126 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6969256 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.993603 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1466052 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3147 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.494698 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1468807 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3068 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23102664 # DTB read hits -system.cpu.dtb.read_misses 192481 # DTB read misses +system.cpu.dtb.read_hits 23133213 # DTB read hits +system.cpu.dtb.read_misses 193272 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23295145 # DTB read accesses -system.cpu.dtb.write_hits 7068005 # DTB write hits -system.cpu.dtb.write_misses 1092 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7069097 # DTB write accesses -system.cpu.dtb.data_hits 30170669 # DTB hits -system.cpu.dtb.data_misses 193573 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 30364242 # DTB accesses -system.cpu.itb.fetch_hits 14708082 # ITB hits -system.cpu.itb.fetch_misses 96 # ITB misses +system.cpu.dtb.read_accesses 23326485 # DTB read accesses +system.cpu.dtb.write_hits 7072266 # DTB write hits +system.cpu.dtb.write_misses 1114 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7073380 # DTB write accesses +system.cpu.dtb.data_hits 30205479 # DTB hits +system.cpu.dtb.data_misses 194386 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 30399865 # DTB accesses +system.cpu.itb.fetch_hits 14751258 # ITB hits +system.cpu.itb.fetch_misses 97 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14708178 # ITB accesses +system.cpu.itb.fetch_accesses 14751355 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,237 +227,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46756135 # number of cpu cycles simulated +system.cpu.numCycles 46853587 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15430530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126815242 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14833517 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8410787 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22106787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4454905 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5569972 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2009 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14708082 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 322729 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46612836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376239 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15478226 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127086204 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14862899 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8438063 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22152522 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4487790 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5536762 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 83 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2724 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14751258 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 326039 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46698540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.721417 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376215 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24506049 52.57% 52.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2362426 5.07% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1191299 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1739407 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2752944 5.91% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1147923 2.46% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1216668 2.61% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 768362 1.65% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10927758 23.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24546018 52.56% 52.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2363136 5.06% 57.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191999 2.55% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1747286 3.74% 63.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2758963 5.91% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1151332 2.47% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1219220 2.61% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 775308 1.66% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10945278 23.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46612836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317253 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.712270 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17256308 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4263506 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20503237 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1097959 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3491826 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2511850 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123858190 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32546 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3491826 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18399179 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 964925 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20435541 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3314078 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121046582 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 48 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 399182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2434828 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88894409 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157311905 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147648223 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9663682 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46698540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317220 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712411 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17303274 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4237001 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20547487 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1094236 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3516542 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2516790 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12060 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124092936 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31896 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3516542 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18446150 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 953596 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7276 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20476535 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3298441 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121253427 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 399455 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2423561 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89048453 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157563733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147863840 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9699893 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20467048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 739 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 732 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8795383 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25343096 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8237940 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2594464 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 920924 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105370947 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1446 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96530679 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178191 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20721356 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15565520 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1057 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46612836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.070903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875751 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20621092 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 715 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762124 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25385907 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8248290 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2586709 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 908922 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105520430 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1810 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96627173 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 179301 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20866432 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15656081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1421 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46698540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.069169 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876778 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12074665 25.90% 25.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9351108 20.06% 45.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8402793 18.03% 63.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6288710 13.49% 77.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4905546 10.52% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2859533 6.13% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1729691 3.71% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796460 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 204330 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12145462 26.01% 26.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9347287 20.02% 46.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8392983 17.97% 64.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6295181 13.48% 77.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4922186 10.54% 88.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2865412 6.14% 94.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725444 3.69% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796771 1.71% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 207814 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46612836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46698540 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 190047 12.12% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 203 0.01% 12.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7055 0.45% 12.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5882 0.38% 12.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842974 53.75% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444058 28.31% 95.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78249 4.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 188040 12.01% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 192 0.01% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7132 0.46% 12.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5753 0.37% 12.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842663 53.82% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 443560 28.33% 95.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78346 5.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58717725 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479593 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58768195 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479903 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2796739 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115257 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386885 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311006 0.32% 67.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760000 0.79% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23812199 24.67% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7150949 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800414 2.90% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115399 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387049 2.47% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311103 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759957 0.79% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23849343 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7155484 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96530679 # Type of FU issued -system.cpu.iq.rate 2.064556 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226318050 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117401953 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87051166 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15102803 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8726703 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7059295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90117667 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7981473 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1519109 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96627173 # Type of FU issued +system.cpu.iq.rate 2.062322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1565686 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226574505 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117655638 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87117393 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15123368 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8767383 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066303 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90201258 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7991594 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1516780 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5346898 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18469 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35032 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1736837 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5389709 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18571 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34473 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1747187 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10557 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10549 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1581 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3491826 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132020 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18316 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115597875 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 364987 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25343096 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8237940 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3142 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35032 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 529110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494336 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1023446 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95309066 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23295605 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1221613 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3516542 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 131686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18180 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115763317 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371525 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25385907 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8248290 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1810 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2912 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34473 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 538490 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495901 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034391 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95392807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23326978 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1234366 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10225482 # number of nop insts executed -system.cpu.iew.exec_refs 30364899 # number of memory reference insts executed -system.cpu.iew.exec_branches 12021435 # Number of branches executed -system.cpu.iew.exec_stores 7069294 # Number of stores executed -system.cpu.iew.exec_rate 2.038429 # Inst execution rate -system.cpu.iew.wb_sent 94627849 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94110461 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64468484 # num instructions producing a value -system.cpu.iew.wb_consumers 89853069 # num instructions consuming a value +system.cpu.iew.exec_nop 10241077 # number of nop insts executed +system.cpu.iew.exec_refs 30400564 # number of memory reference insts executed +system.cpu.iew.exec_branches 12029650 # Number of branches executed +system.cpu.iew.exec_stores 7073586 # Number of stores executed +system.cpu.iew.exec_rate 2.035977 # Inst execution rate +system.cpu.iew.wb_sent 94705450 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94183696 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64505139 # num instructions producing a value +system.cpu.iew.wb_consumers 89892889 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.012794 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717488 # average fanout of values written-back +system.cpu.iew.wb_rate 2.010170 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717578 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23695922 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23861264 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 905358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43121010 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.131283 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.747044 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 913934 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43181998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.128272 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.745397 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16684738 38.69% 38.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9903892 22.97% 61.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4485087 10.40% 72.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2259914 5.24% 77.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1605498 3.72% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1123100 2.60% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 719913 1.67% 85.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818667 1.90% 87.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5520201 12.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16729209 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9919354 22.97% 61.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4482137 10.38% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2267062 5.25% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1606601 3.72% 81.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122793 2.60% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721285 1.67% 85.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818294 1.89% 87.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5515263 12.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43121010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43181998 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,192 +469,192 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5520201 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5515263 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153198746 # The number of ROB reads -system.cpu.rob.rob_writes 234713539 # The number of ROB writes -system.cpu.timesIdled 5103 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 143299 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153430014 # The number of ROB reads +system.cpu.rob.rob_writes 235069144 # The number of ROB writes +system.cpu.timesIdled 5265 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.555432 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555432 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800399 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800399 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129015669 # number of integer regfile reads -system.cpu.int_regfile_writes 70499119 # number of integer regfile writes -system.cpu.fp_regfile_reads 6185969 # number of floating regfile reads -system.cpu.fp_regfile_writes 6040722 # number of floating regfile writes -system.cpu.misc_regfile_reads 714490 # number of misc regfile reads +system.cpu.cpi 0.556590 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.556590 # CPI: Total CPI of All Threads +system.cpu.ipc 1.796655 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.796655 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129123035 # number of integer regfile reads +system.cpu.int_regfile_writes 70557439 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190540 # number of floating regfile reads +system.cpu.fp_regfile_writes 6048182 # number of floating regfile writes +system.cpu.misc_regfile_reads 714455 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 9535 # number of replacements -system.cpu.icache.tagsinuse 1597.711655 # Cycle average of tags in use -system.cpu.icache.total_refs 14694095 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11468 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1281.312783 # Average number of references to valid blocks. +system.cpu.icache.replacements 9558 # number of replacements +system.cpu.icache.tagsinuse 1591.672723 # Cycle average of tags in use +system.cpu.icache.total_refs 14737290 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11492 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1282.395580 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1597.711655 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.780133 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.780133 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14694095 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14694095 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14694095 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14694095 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14694095 # number of overall hits -system.cpu.icache.overall_hits::total 14694095 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13987 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13987 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13987 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13987 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13987 # number of overall misses -system.cpu.icache.overall_misses::total 13987 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 308160500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 308160500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 308160500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 308160500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 308160500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 308160500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14708082 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14708082 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14708082 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14708082 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14708082 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14708082 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000951 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000951 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000951 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000951 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000951 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000951 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22031.922499 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22031.922499 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22031.922499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22031.922499 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1591.672723 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777184 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777184 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14737290 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14737290 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14737290 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14737290 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14737290 # number of overall hits +system.cpu.icache.overall_hits::total 14737290 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13967 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13967 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13967 # number of overall misses +system.cpu.icache.overall_misses::total 13967 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 317608000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 317608000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 317608000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 317608000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 317608000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 317608000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14751257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14751257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14751257 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14751257 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14751257 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14751257 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000947 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000947 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000947 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000947 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000947 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000947 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.886876 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22739.886876 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.886876 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22739.886876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.886876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22739.886876 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2519 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2519 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2519 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2519 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2519 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2519 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11468 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11468 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11468 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11468 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11468 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11468 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 234957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 234957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234957500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 234957500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000780 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000780 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20488.097314 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20488.097314 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2475 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2475 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2475 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2475 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2475 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2475 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11492 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11492 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11492 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11492 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11492 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11492 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 240859500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 240859500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 240859500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 240859500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 240859500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 240859500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000779 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20958.884441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20958.884441 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20958.884441 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20958.884441 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20958.884441 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20958.884441 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2411.634709 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8474 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.361103 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2404.595595 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8500 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3590 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.367688 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.671111 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2014.246310 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 379.717288 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.668263 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2005.213140 # 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Cycle average of tags in use +system.cpu.dcache.total_refs 28096546 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2247 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12504.025812 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1458.941648 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.356187 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.356187 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21570663 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21570663 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493007 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 234 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 234 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28063670 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28063670 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28063670 # number of overall hits -system.cpu.dcache.overall_hits::total 28063670 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 977 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 977 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8096 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8096 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1459.874578 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.356415 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.356415 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21603310 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21603310 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 230 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 230 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28096316 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28096316 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28096316 # number of overall hits +system.cpu.dcache.overall_hits::total 28096316 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1004 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1004 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9073 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9073 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9073 # number of overall misses -system.cpu.dcache.overall_misses::total 9073 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44122000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44122000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 343188654 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 343188654 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9101 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9101 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9101 # number of overall misses +system.cpu.dcache.overall_misses::total 9101 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 50487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 50487500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 356466299 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 356466299 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 387310654 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 387310654 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 387310654 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 387310654 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21571640 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21571640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 406953799 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 406953799 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 406953799 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 406953799 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21604314 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21604314 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28072743 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28072743 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28072743 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28072743 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 231 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 231 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28105417 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28105417 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28105417 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28105417 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000323 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000323 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45160.696008 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45160.696008 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42389.902915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42389.902915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50286.354582 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50286.354582 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44024.490429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44024.490429 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42688.267828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42688.267828 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10592 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44715.283925 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44715.283925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44715.283925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44715.283925 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14195 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 468 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 327 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.632479 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.409786 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6364 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6364 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6829 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6829 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6829 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6829 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6366 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6366 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6855 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6855 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6855 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6855 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26453500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26453500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82660498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 82660498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30190000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30190000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88528998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88528998 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 109113998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 109113998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 109113998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 109113998 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118718998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 118718998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118718998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 118718998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004255 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004255 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004329 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004329 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51666.992188 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51666.992188 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47725.460739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47725.460739 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58621.359223 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58621.359223 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51143.268631 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51143.268631 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52857.968833 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52857.968833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52857.968833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52857.968833 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index b23c244b9..4d507d8ac 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074149 # Number of seconds simulated -sim_ticks 74148853000 # Number of ticks simulated -final_tick 74148853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074156 # Number of seconds simulated +sim_ticks 74155951500 # Number of ticks simulated +final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87257 # Simulator instruction rate (inst/s) -host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37550131 # Simulator tick rate (ticks/s) -host_mem_usage 292636 # Number of bytes of host memory used -host_seconds 1974.66 # Real time elapsed on the host +host_inst_rate 108940 # Simulator instruction rate (inst/s) +host_op_rate 119280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46885764 # Simulator tick rate (ticks/s) +host_mem_usage 245224 # Number of bytes of host memory used +host_seconds 1581.63 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111744 # Number of bytes read from this memory -system.physmem.bytes_read::total 243392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131648 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2057 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3803 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1775456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1507023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3282478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1775456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1775456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1775456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1507023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3282478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3804 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112064 # Number of bytes read from this memory +system.physmem.bytes_read::total 243840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1751 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3810 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1777012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1511194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3288205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1777012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1777012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1777012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1511194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3288205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3811 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3804 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 243392 # Total number of bytes read from memory +system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 243840 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 243392 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 243840 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 190 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 322 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74148834500 # Total gap between requests +system.physmem.totGap 74155933000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3804 # Categorize read packet sizes +system.physmem.readPktSize::6 3811 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 2808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 11954297 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86040297 # Sum of mem lat for all requests -system.physmem.totBusLat 15216000 # Total cycles spent in databus access -system.physmem.totBankLat 58870000 # Total cycles spent in bank access -system.physmem.avgQLat 3142.56 # Average queueing delay per request -system.physmem.avgBankLat 15475.81 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22618.37 # Average memory access latency -system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 17813284 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 103885784 # Sum of mem lat for all requests +system.physmem.totBusLat 19055000 # Total cycles spent in databus access +system.physmem.totBankLat 67017500 # Total cycles spent in bank access +system.physmem.avgQLat 4674.18 # Average queueing delay per request +system.physmem.avgBankLat 17585.28 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27259.46 # Average memory access latency +system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3306 # Number of row buffer hits during reads +system.physmem.readRowHits 3029 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19492332.94 # Average gap between requests -system.cpu.branchPred.lookups 94799058 # Number of BP lookups -system.cpu.branchPred.condPredicted 74801869 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6279291 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44724397 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43048437 # Number of BTB hits +system.physmem.avgGap 19458392.29 # Average gap between requests +system.cpu.branchPred.lookups 94769609 # Number of BP lookups +system.cpu.branchPred.condPredicted 74778233 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6277605 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44694278 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43050555 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.252694 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4355507 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88338 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.322297 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4352672 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88403 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,135 +237,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148297707 # number of cpu cycles simulated +system.cpu.numCycles 148311904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39650853 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380235632 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94799058 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47403944 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80363745 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27281096 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7190522 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5914 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39646309 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380172339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94769609 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47403227 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80367500 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27273234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7195566 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5621 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36846162 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1830987 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148197153 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153253 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36841499 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1830160 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148194878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152973 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68002614 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5258973 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10529156 7.10% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10279296 6.94% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8665155 5.85% 69.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6547882 4.42% 73.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6243481 4.21% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8012637 5.41% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24657959 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67997083 45.88% 45.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5272996 3.56% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10535975 7.11% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10290073 6.94% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8651484 5.84% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6547502 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6243559 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8000119 5.40% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24656087 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148197153 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.639248 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.564002 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45504222 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5859124 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74799977 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1201103 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832727 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14326960 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164415 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392837219 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 734618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832727 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50888432 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722612 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 592441 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70554465 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4606476 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371355589 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339881 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3653545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631848996 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581867929 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1564559444 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17308485 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148194878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638989 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.563330 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45496007 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5866375 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74802564 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203257 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20826675 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14321536 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392763604 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 730055 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20826675 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50882111 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 721217 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 592672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70557397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4614806 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371296733 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 341377 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661217 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631671723 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581648558 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1564322118 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17326440 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333804857 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25175 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25171 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13001756 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43004891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16418786 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5685881 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3634471 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329217927 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47188 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249444233 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 790071 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139538270 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362161071 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1972 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148197153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761683 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333627584 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25019 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25015 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13027360 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43001248 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16425649 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5676819 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3663476 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329185491 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47072 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249459953 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 787409 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139507738 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 361963164 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1856 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148194878 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761955 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56041941 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22617532 15.26% 53.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24819018 16.75% 69.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20330052 13.72% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12543560 8.46% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6522981 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4027974 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1111240 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182855 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56034848 37.81% 37.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22634456 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24811776 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20313354 13.71% 83.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12551343 8.47% 92.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6515797 4.40% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4037298 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1114310 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181696 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148197153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148194878 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 964308 38.46% 38.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5601 0.22% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1163168 46.39% 85.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 374037 14.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 964655 38.37% 38.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5597 0.22% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 47 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1171629 46.60% 85.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372002 14.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194888705 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979440 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194901733 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979970 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -384,93 +384,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33084 0.01% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33123 0.01% 78.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164341 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254530 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76430 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465703 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38355599 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13947826 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164480 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254950 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465883 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206474 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38354449 15.37% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13950286 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249444233 # Type of FU issued -system.cpu.iq.rate 1.682051 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2507262 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010051 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646645921 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466634028 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237875698 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3737031 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2187759 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1841461 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250076224 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875271 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2007740 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249459953 # Type of FU issued +system.cpu.iq.rate 1.681995 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2514028 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010078 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646678377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466567894 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237899290 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737844 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2190776 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1842401 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250099013 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1874968 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2006458 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13155407 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11336 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18867 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3774152 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13151764 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11904 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18813 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3781015 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 95 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832727 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16956 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 865 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329282292 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 783571 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43004891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16418786 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24780 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 273 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18867 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889474 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3759056 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7648530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242951850 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36852953 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6492383 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20826675 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16651 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 839 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329249613 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 779131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43001248 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16425649 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24664 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18813 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3890202 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3759917 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650119 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242971028 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36855113 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6488925 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17177 # number of nop insts executed -system.cpu.iew.exec_refs 50499895 # number of memory reference insts executed -system.cpu.iew.exec_branches 53421871 # Number of branches executed -system.cpu.iew.exec_stores 13646942 # Number of stores executed -system.cpu.iew.exec_rate 1.638271 # Inst execution rate -system.cpu.iew.wb_sent 240774594 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239717159 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148465347 # num instructions producing a value -system.cpu.iew.wb_consumers 267264848 # num instructions consuming a value +system.cpu.iew.exec_nop 17050 # number of nop insts executed +system.cpu.iew.exec_refs 50502517 # number of memory reference insts executed +system.cpu.iew.exec_branches 53426440 # Number of branches executed +system.cpu.iew.exec_stores 13647404 # Number of stores executed +system.cpu.iew.exec_rate 1.638244 # Inst execution rate +system.cpu.iew.wb_sent 240798946 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239741691 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148482444 # num instructions producing a value +system.cpu.iew.wb_consumers 267276214 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616459 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555499 # average fanout of values written-back +system.cpu.iew.wb_rate 1.616470 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140611386 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140578703 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6125994 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127364426 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481347 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186226 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6124430 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127368203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186211 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57685030 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31666758 24.86% 70.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13788542 10.83% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7634444 5.99% 86.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4378206 3.44% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321179 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1702157 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1312824 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7875286 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57677570 45.28% 45.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31688766 24.88% 70.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13782136 10.82% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7629564 5.99% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4377691 3.44% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1320690 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1704652 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1310037 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7877097 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127364426 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127368203 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -481,192 +481,196 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7875286 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7877097 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448766216 # The number of ROB reads -system.cpu.rob.rob_writes 679506166 # The number of ROB writes -system.cpu.timesIdled 2556 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 100554 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448735499 # The number of ROB reads +system.cpu.rob.rob_writes 679435154 # The number of ROB writes +system.cpu.timesIdled 2602 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 117026 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.860680 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.860680 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161872 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161872 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079384127 # number of integer regfile reads -system.cpu.int_regfile_writes 384869699 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912697 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497246 # number of floating regfile writes -system.cpu.misc_regfile_reads 54493639 # number of misc regfile reads +system.cpu.cpi 0.860762 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.860762 # CPI: Total CPI of All Threads +system.cpu.ipc 1.161761 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.161761 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079459412 # number of integer regfile reads +system.cpu.int_regfile_writes 384885584 # number of integer regfile writes +system.cpu.fp_regfile_reads 2914044 # number of floating regfile reads +system.cpu.fp_regfile_writes 2498648 # number of floating regfile writes +system.cpu.misc_regfile_reads 54505090 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.icache.replacements 2375 # number of replacements -system.cpu.icache.tagsinuse 1350.215949 # Cycle average of tags in use -system.cpu.icache.total_refs 36840897 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4105 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8974.639951 # Average number of references to valid blocks. +system.cpu.icache.replacements 2367 # number of replacements +system.cpu.icache.tagsinuse 1349.329106 # Cycle average of tags in use +system.cpu.icache.total_refs 36836268 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8991.034415 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1350.215949 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.659285 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.659285 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36840897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36840897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36840897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36840897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36840897 # number of overall hits -system.cpu.icache.overall_hits::total 36840897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5265 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5265 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5265 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5265 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5265 # number of overall misses -system.cpu.icache.overall_misses::total 5265 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 158318499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 158318499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 158318499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 158318499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 158318499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 158318499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36846162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36846162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36846162 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36846162 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36846162 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36846162 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30069.990313 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30069.990313 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30069.990313 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30069.990313 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30069.990313 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30069.990313 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 679 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1349.329106 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.658852 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.658852 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36836269 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36836269 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36836269 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36836269 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36836269 # number of overall hits +system.cpu.icache.overall_hits::total 36836269 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5230 # number of overall misses +system.cpu.icache.overall_misses::total 5230 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 167188500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 167188500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 167188500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 167188500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 167188500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 167188500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36841499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36841499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36841499 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36841499 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36841499 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36841499 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31967.208413 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31967.208413 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31967.208413 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31967.208413 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31967.208413 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31967.208413 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.722222 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1159 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1159 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1159 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1159 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1159 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4106 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4106 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4106 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4106 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4106 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4106 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121527999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 121527999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121527999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 121527999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121527999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 121527999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1129 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1129 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1129 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1129 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1129 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1129 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4101 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4101 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4101 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4101 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4101 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4101 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 128471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 128471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128471500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 128471500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29597.661715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29597.661715 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29597.661715 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29597.661715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29597.661715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29597.661715 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31326.871495 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31326.871495 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31326.871495 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 31326.871495 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31326.871495 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 31326.871495 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.043583 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016204 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.059939 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2043 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2131 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 5.016873 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1429.150441 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 536.739967 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000153 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.043614 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016380 # 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number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2140 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 677 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2740 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2063 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3820 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2063 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1757 # number of overall misses -system.cpu.l2cache.overall_misses::total 3820 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46197.955390 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50366.828087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50810.550199 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50571.185998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50366.828087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50810.550199 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50571.185998 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,184 +680,184 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58562641 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 129052068 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870588 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.638255 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501218 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34251.422255 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33541.031501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33925.359621 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2060 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2735 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1076 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1076 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2060 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67299993 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145431973 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78131980 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67299993 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145431973 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869845 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.560911 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991705 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991705 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.639322 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.639322 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37928.145631 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45904.093333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39896.615356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33749.749071 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33749.749071 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 58 # number of replacements -system.cpu.dcache.tagsinuse 1406.419520 # Cycle average of tags in use -system.cpu.dcache.total_refs 46792514 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25238.680690 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1410.136977 # Cycle average of tags in use +system.cpu.dcache.total_refs 46795714 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1861 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25145.466953 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1406.419520 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.343364 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.343364 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34391106 # 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number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46747641 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46747641 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46747641 # number of overall hits -system.cpu.dcache.overall_hits::total 46747641 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 46750832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46750832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46750832 # number of overall hits +system.cpu.dcache.overall_hits::total 46750832 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1904 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1904 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9656 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9656 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9656 # number of overall misses -system.cpu.dcache.overall_misses::total 9656 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84169500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84169500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 293859496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 293859496 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9634 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9634 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9634 # number of overall misses +system.cpu.dcache.overall_misses::total 9634 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 93402000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 93402000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 306706496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 306706496 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 378028996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 378028996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 378028996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 378028996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34393010 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34393010 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 400108496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 400108496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 400108496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 400108496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34396179 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34396179 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22468 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22468 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46757297 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46757297 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46757297 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46757297 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46760466 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46760466 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46760466 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46760466 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44206.670168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44206.670168 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37907.571723 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37907.571723 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49055.672269 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49055.672269 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39677.425097 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39677.425097 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39149.647473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39149.647473 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 472 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 34 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41530.879801 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41530.879801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41530.879801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41530.879801 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 527 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.307692 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1138 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1138 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6664 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6664 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1127 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7802 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7802 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7802 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7802 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1088 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1088 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1854 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1854 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1854 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1854 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36187000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36187000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47523998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 47523998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83710998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 83710998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83710998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 83710998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7770 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7770 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7770 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7770 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1087 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1087 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41603000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41603000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50879498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 50879498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92482498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92482498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92482498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92482498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47241.514360 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47241.514360 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43680.145221 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43680.145221 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53543.114543 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53543.114543 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46807.265869 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46807.265869 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49615.074034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49615.074034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49615.074034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49615.074034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index daaac056b..ea454cb40 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.082648 # Number of seconds simulated -sim_ticks 82648140000 # Number of ticks simulated -final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.082836 # Number of seconds simulated +sim_ticks 82836235000 # Number of ticks simulated +final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59257 # Simulator instruction rate (inst/s) -host_op_rate 99320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37082179 # Simulator tick rate (ticks/s) -host_mem_usage 321776 # Number of bytes of host memory used -host_seconds 2228.78 # Real time elapsed on the host +host_inst_rate 72340 # Simulator instruction rate (inst/s) +host_op_rate 121249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45372545 # Simulator tick rate (ticks/s) +host_mem_usage 275820 # Number of bytes of host memory used +host_seconds 1825.69 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory -system.physmem.bytes_read::total 342144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5346 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2634397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1505370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4139766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2634397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2634397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2634397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1505370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4139766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5348 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124544 # Number of bytes read from this memory +system.physmem.bytes_read::total 342912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218368 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5358 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2636141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1503497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4139638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2636141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2636141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2636141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1503497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4139638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5362 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5502 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342144 # Total number of bytes read from memory +system.physmem.cpureqs 5515 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 342912 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342144 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 342912 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 295 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 153 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 338 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 82648109000 # Total gap between requests +system.physmem.totGap 82836206000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5348 # Categorize read packet sizes +system.physmem.readPktSize::6 5362 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,15 +95,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 154 # categorize neither packet sizes +system.physmem.neitherpktsize::6 153 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,164 +164,164 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16873822 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests -system.physmem.totBusLat 21392000 # Total cycles spent in databus access -system.physmem.totBankLat 84182000 # Total cycles spent in bank access -system.physmem.avgQLat 3155.16 # Average queueing delay per request -system.physmem.avgBankLat 15740.84 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22896.00 # Average memory access latency +system.physmem.totQLat 15727084 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 132185834 # Sum of mem lat for all requests +system.physmem.totBusLat 26795000 # Total cycles spent in databus access +system.physmem.totBankLat 89663750 # Total cycles spent in bank access +system.physmem.avgQLat 2933.06 # Average queueing delay per request +system.physmem.avgBankLat 16722.07 # Average bank access latency per request +system.physmem.avgBusLat 4997.20 # Average bus latency per request +system.physmem.avgMemAccLat 24652.34 # Average memory access latency system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4742 # Number of row buffer hits during reads +system.physmem.readRowHits 4538 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15454021.88 # Average gap between requests -system.cpu.branchPred.lookups 19953215 # Number of BP lookups -system.cpu.branchPred.condPredicted 19953215 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2011335 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 13840594 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13098591 # Number of BTB hits +system.physmem.avgGap 15448751.59 # Average gap between requests +system.cpu.branchPred.lookups 19976706 # Number of BP lookups +system.cpu.branchPred.condPredicted 19976706 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2014402 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 13812152 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13105283 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.638937 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 94.882267 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 165296281 # number of cpu cycles simulated +system.cpu.numCycles 165672471 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25870668 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219126869 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19976706 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13105283 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 57628355 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17696017 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 66630701 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2007 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24475842 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 426793 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 165546176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.187647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326502 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3450171 2.09% 73.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3573015 2.16% 75.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4309284 2.61% 78.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2725915 1.65% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33580712 20.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 109520431 66.16% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3059143 1.85% 68.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2383042 1.44% 69.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2888379 1.74% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3450462 2.08% 73.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3573116 2.16% 75.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4323051 2.61% 78.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2727876 1.65% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33620676 20.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 165175969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.120712 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.324235 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38701150 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56465114 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44698220 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9957565 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15353920 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 353610105 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 15353920 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46165738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14909579 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23078 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46524421 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42199233 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 345243747 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 88 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17893684 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22177130 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 398936501 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 960723880 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 950976963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9746917 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 165546176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.120580 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.322651 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38775408 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56644846 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44737695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9974174 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15414053 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 354047911 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15414053 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46255302 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14979465 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23344 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46561207 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42312805 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 345686471 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18031828 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22149425 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 50 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 399403706 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 962076305 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 952204922 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9871383 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 139507897 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1674 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1664 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90390787 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 86672801 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31756377 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 57758664 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18775058 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 333623093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3362 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 267451276 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 258403 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111810012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 230098900 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2117 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 165175969 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.619190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 139975102 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1676 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1665 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90583210 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 86793756 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31811808 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 57862174 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18818230 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334054188 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3459 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267584091 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 253989 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 112238541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 231222254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 165546176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.616371 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.504250 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44964626 27.22% 27.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46539597 28.18% 55.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32801785 19.86% 75.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19824720 12.00% 87.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13230335 8.01% 95.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4791341 2.90% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2351721 1.42% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 529174 0.32% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 142670 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45159771 27.28% 27.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46666031 28.19% 55.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32872103 19.86% 75.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19858979 12.00% 87.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13194353 7.97% 95.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4779249 2.89% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2330620 1.41% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 541020 0.33% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 144050 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 165175969 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 165546176 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 137826 5.20% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2250902 84.86% 90.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 263908 9.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 132244 4.97% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2258982 84.96% 89.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 267651 10.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212134 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174151286 65.12% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212144 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174232004 65.11% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1593879 0.60% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1599138 0.60% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued @@ -347,84 +347,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67229168 25.14% 91.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23264809 8.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67256463 25.13% 91.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23284342 8.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 267451276 # Type of FU issued -system.cpu.iq.rate 1.618011 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2652636 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 697648502 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 441157156 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260237459 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5341058 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4570848 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2570585 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266205797 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2685981 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19039823 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267584091 # Type of FU issued +system.cpu.iq.rate 1.615139 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2658877 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 698266747 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 441935949 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260335869 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5360477 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4651988 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2579879 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266334819 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2696005 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19019917 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30023215 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29490 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 296813 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11240660 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30144170 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29191 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 297029 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11296091 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49425 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49411 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15353920 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 582358 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 260686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 333626455 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 190123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 86672801 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31756377 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1654 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 146774 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 296813 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1177159 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 916050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2093209 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264577691 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66245889 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2873585 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15414053 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 584332 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 268197 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334057647 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 187603 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 86793756 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31811808 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1663 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 154006 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 31822 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 297029 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1177472 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 918811 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2096283 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264704604 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66268952 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2879487 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 89117815 # number of memory reference insts executed -system.cpu.iew.exec_branches 14597039 # Number of branches executed -system.cpu.iew.exec_stores 22871926 # Number of stores executed -system.cpu.iew.exec_rate 1.600627 # Inst execution rate -system.cpu.iew.wb_sent 263630467 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 262808044 # cumulative count of insts written-back -system.cpu.iew.wb_producers 212084858 # num instructions producing a value -system.cpu.iew.wb_consumers 375096623 # num instructions consuming a value +system.cpu.iew.exec_refs 89158933 # number of memory reference insts executed +system.cpu.iew.exec_branches 14605846 # Number of branches executed +system.cpu.iew.exec_stores 22889981 # Number of stores executed +system.cpu.iew.exec_rate 1.597759 # Inst execution rate +system.cpu.iew.wb_sent 263752937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 262915748 # cumulative count of insts written-back +system.cpu.iew.wb_producers 212158955 # num instructions producing a value +system.cpu.iew.wb_consumers 375269860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.589921 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.565414 # average fanout of values written-back +system.cpu.iew.wb_rate 1.586961 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565350 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 112301239 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 112734910 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2011502 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822049 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.477506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.946000 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2014608 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150132123 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.474454 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.942401 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50722618 33.86% 33.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57116806 38.12% 71.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13820755 9.22% 81.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12019830 8.02% 89.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4145175 2.77% 91.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2956577 1.97% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1072909 0.72% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 994916 0.66% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6972463 4.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50871002 33.88% 33.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57276171 38.15% 72.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13824598 9.21% 81.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12056402 8.03% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4136994 2.76% 92.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2958422 1.97% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1072501 0.71% 94.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 994968 0.66% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6941065 4.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822049 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 150132123 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362961 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -435,198 +435,198 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339551 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6972463 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6941065 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 476513786 # The number of ROB reads -system.cpu.rob.rob_writes 682717187 # The number of ROB writes -system.cpu.timesIdled 2881 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 120312 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 477288929 # The number of ROB reads +system.cpu.rob.rob_writes 683644230 # The number of ROB writes +system.cpu.timesIdled 2956 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 126295 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362961 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.251570 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.251570 # CPI: Total CPI of All Threads -system.cpu.ipc 0.798997 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.798997 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 562635091 # number of integer regfile reads -system.cpu.int_regfile_writes 298739906 # number of integer regfile writes -system.cpu.fp_regfile_reads 3520410 # number of floating regfile reads -system.cpu.fp_regfile_writes 2230055 # number of floating regfile writes -system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads +system.cpu.cpi 1.254418 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.254418 # CPI: Total CPI of All Threads +system.cpu.ipc 0.797182 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.797182 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 562757952 # number of integer regfile reads +system.cpu.int_regfile_writes 298813122 # number of integer regfile writes +system.cpu.fp_regfile_reads 3531630 # number of floating regfile reads +system.cpu.fp_regfile_writes 2237821 # number of floating regfile writes +system.cpu.misc_regfile_reads 137110805 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4732 # number of replacements -system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use -system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. +system.cpu.icache.replacements 4901 # number of replacements +system.cpu.icache.tagsinuse 1627.835837 # Cycle average of tags in use +system.cpu.icache.total_refs 24466683 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6871 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3560.862029 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24437101 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24437101 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits -system.cpu.icache.overall_hits::total 24437101 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses -system.cpu.icache.overall_misses::total 8952 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000366 # 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Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.794842 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24466683 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24466683 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24466683 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24466683 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24466683 # number of overall hits +system.cpu.icache.overall_hits::total 24466683 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9159 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9159 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9159 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9159 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9159 # number of overall misses +system.cpu.icache.overall_misses::total 9159 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 269675497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 269675497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 269675497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 269675497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 269675497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 269675497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24475842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24475842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24475842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24475842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24475842 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29443.770827 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29443.770827 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 864 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.230769 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,100 +635,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3402 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 386 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3788 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 154 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 154 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1560 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995519 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995519 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.605260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.605260 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35531.298271 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.901015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36751.756764 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31667.202572 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31667.202572 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 55 # number of replacements -system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use -system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. +system.cpu.dcache.replacements 56 # number of replacements +system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use +system.cpu.dcache.total_refs 67604390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34091.976803 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits -system.cpu.dcache.overall_hits::total 67560798 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 1416.460930 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345816 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117154000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117154000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117154000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 47090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 47090980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 67606711 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67606711 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67606711 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67606711 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses @@ -737,48 +737,48 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50254.740834 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50254.740834 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45106.351981 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45106.351981 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46730.753889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46730.753889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1715 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1715 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2139 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2139 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2139 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2139 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 98158500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 98158500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 98158500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 98158500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses @@ -787,14 +787,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57126.179245 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57126.179245 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43111.953353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43111.953353 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |