diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
| commit | 3c666083c6f5fecc38699a6f0c5f4f25b23e18c9 (patch) | |
| tree | e554e37e76714f9ae9c9faa07ef645db0f9a6d93 /tests/long/se | |
| parent | 8e2a8fbb7e4751260c88fccd19ebe8d1138d0695 (diff) | |
| download | gem5-3c666083c6f5fecc38699a6f0c5f4f25b23e18c9.tar.xz | |
ARM: Update stats for IT and conditional branch changes
Diffstat (limited to 'tests/long/se')
72 files changed, 4373 insertions, 4372 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 5d521d8ff..043132ebd 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 2783a8301..35fcd0232 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:26 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:38:16 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164277874000 because target called exit() +Exiting @ tick 164248292500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 46c526502..8bc0cbb1b 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164278 # Number of seconds simulated -sim_ticks 164277874000 # Number of ticks simulated -final_tick 164277874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164248 # Number of seconds simulated +sim_ticks 164248292500 # Number of ticks simulated +final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203470 # Simulator instruction rate (inst/s) -host_op_rate 215002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58636208 # Simulator tick rate (ticks/s) -host_mem_usage 227276 # Number of bytes of host memory used -host_seconds 2801.65 # Real time elapsed on the host -sim_insts 570051643 # Number of instructions simulated -sim_ops 602359850 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5845952 # Number of bytes read from this memory -system.physmem.bytes_inst_read 50048 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3721408 # Number of bytes written to this memory -system.physmem.num_reads 91343 # Number of read requests responded to by this memory -system.physmem.num_writes 58147 # Number of write requests responded to by this memory +host_inst_rate 250614 # Simulator instruction rate (inst/s) +host_op_rate 264817 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72208895 # Simulator tick rate (ticks/s) +host_mem_usage 224524 # Number of bytes of host memory used +host_seconds 2274.63 # Real time elapsed on the host +sim_insts 570052728 # Number of instructions simulated +sim_ops 602360935 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 5850432 # Number of bytes read from this memory +system.physmem.bytes_inst_read 51136 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3722112 # Number of bytes written to this memory +system.physmem.num_reads 91413 # Number of read requests responded to by this memory +system.physmem.num_writes 58158 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 35585754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 304655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 22653130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 58238884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 35619439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 311334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 22661496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 58280935 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,141 +64,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 328555749 # number of cpu cycles simulated +system.cpu.numCycles 328496586 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85495228 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80299392 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2363839 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47188450 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46808758 # Number of BTB hits +system.cpu.BPredUnit.lookups 85500889 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80301573 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2363462 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47194810 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46809578 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1441266 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2064 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68932526 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669692235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85495228 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48250024 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130038876 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13469589 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117716369 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67498352 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807371 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 327717199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.177607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.200173 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1441693 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2047 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68928725 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669724193 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85500889 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48251271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130040939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13471504 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117632066 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 466 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67495318 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807242 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 327633093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.178244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.200456 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 197678537 60.32% 60.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20955398 6.39% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4944268 1.51% 68.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14317146 4.37% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8982056 2.74% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9405272 2.87% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4386310 1.34% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5814100 1.77% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61234112 18.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 197592366 60.31% 60.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20955363 6.40% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4944852 1.51% 68.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14316797 4.37% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8978717 2.74% 75.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9406752 2.87% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4386482 1.34% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5812411 1.77% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61239353 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 327717199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260215 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.038291 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93143264 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94872868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108628769 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20045238 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11027060 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4784060 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705973468 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5432 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11027060 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107429081 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13945008 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 118563 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114317154 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80880333 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697178999 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 231 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59283430 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19375407 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 624 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723780453 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241174730 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241174602 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 327633093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260279 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.038755 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93122772 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94805335 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108615724 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20060132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11029130 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4785077 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1812 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705993706 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5866 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11029130 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107405098 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13994903 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53643 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114322395 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80827924 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697209083 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59229209 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19383033 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 653 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723812839 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241314962 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241314834 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417466 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96362987 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11553 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11552 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169904976 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172902366 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80616631 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21434396 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 27805052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681951411 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9116 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646829241 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1424329 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79415012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197703011 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 327717199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.973742 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.738606 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419202 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96393637 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6694 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6687 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169956085 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172904405 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80621547 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21577919 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28225780 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681971655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4856 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646826004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1423990 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79433587 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197870891 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 327633093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.974239 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.736392 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68508405 20.90% 20.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84956160 25.92% 46.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75144846 22.93% 69.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40581693 12.38% 82.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28626833 8.74% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15169754 4.63% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5928523 1.81% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6496810 1.98% 99.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2304175 0.70% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68428283 20.89% 20.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84743637 25.87% 46.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75345420 23.00% 69.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40565003 12.38% 82.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28664322 8.75% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15213545 4.64% 95.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5876273 1.79% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6659013 2.03% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2137597 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 327717199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 327633093 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 204843 5.11% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2907010 72.53% 77.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 896423 22.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205009 5.12% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2904405 72.49% 77.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 897167 22.39% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403920439 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403920644 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -226,153 +226,153 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166108811 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76793420 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166111461 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76787311 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646829241 # Type of FU issued -system.cpu.iq.rate 1.968705 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4008276 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006197 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1626808250 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761386923 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638549644 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646826004 # Type of FU issued +system.cpu.iq.rate 1.969049 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4006581 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006194 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1626715636 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761421594 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638533475 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650837497 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650832565 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30424903 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30420680 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23949762 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 129784 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11648 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10395608 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23951584 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 127945 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11724 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10400307 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12818 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12531 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12832 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12549 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11027060 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 853408 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 62572 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682026706 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 660555 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172902366 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80616631 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6245 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11648 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1315368 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1582506 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2897874 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642687405 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163985784 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4141836 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11029130 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 827373 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 62655 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682042744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 662438 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172904405 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80621547 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3504 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13090 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6258 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11724 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1313555 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1583724 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2897279 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642671991 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163979527 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4154013 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66179 # number of nop insts executed -system.cpu.iew.exec_refs 239997187 # number of memory reference insts executed -system.cpu.iew.exec_branches 74667058 # Number of branches executed -system.cpu.iew.exec_stores 76011403 # Number of stores executed -system.cpu.iew.exec_rate 1.956098 # Inst execution rate -system.cpu.iew.wb_sent 640040588 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638549660 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420197588 # num instructions producing a value -system.cpu.iew.wb_consumers 654962025 # num instructions consuming a value +system.cpu.iew.exec_nop 66233 # number of nop insts executed +system.cpu.iew.exec_refs 239982954 # number of memory reference insts executed +system.cpu.iew.exec_branches 74668739 # Number of branches executed +system.cpu.iew.exec_stores 76003427 # Number of stores executed +system.cpu.iew.exec_rate 1.956404 # Inst execution rate +system.cpu.iew.wb_sent 640027985 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638533491 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420151811 # num instructions producing a value +system.cpu.iew.wb_consumers 654946950 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.943505 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641560 # average fanout of values written-back +system.cpu.iew.wb_rate 1.943806 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641505 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570051694 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602359901 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 79676133 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6355 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2424230 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 316690140 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.902048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.239406 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570052779 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602360986 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79691237 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2423863 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 316603964 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.902569 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.239613 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 92731092 29.28% 29.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104002875 32.84% 62.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43058477 13.60% 75.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8922442 2.82% 78.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25674548 8.11% 86.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13103987 4.14% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7582493 2.39% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1154147 0.36% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20460079 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92664555 29.27% 29.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103983968 32.84% 62.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43054287 13.60% 75.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8920631 2.82% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25673085 8.11% 86.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13110941 4.14% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7578873 2.39% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1154724 0.36% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20462900 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 316690140 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570051694 # Number of instructions committed -system.cpu.commit.committedOps 602359901 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 316603964 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052779 # Number of instructions committed +system.cpu.commit.committedOps 602360986 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173627 # Number of memory references committed -system.cpu.commit.loads 148952604 # Number of loads committed +system.cpu.commit.refs 219174061 # Number of memory references committed +system.cpu.commit.loads 148952821 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828611 # Number of branches committed +system.cpu.commit.branches 70828828 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522679 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523547 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20460079 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20462900 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 978265483 # The number of ROB reads -system.cpu.rob.rob_writes 1375131668 # The number of ROB writes -system.cpu.timesIdled 36876 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 838550 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570051643 # Number of Instructions Simulated -system.cpu.committedOps 602359850 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570051643 # Number of Instructions Simulated -system.cpu.cpi 0.576361 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.576361 # CPI: Total CPI of All Threads -system.cpu.ipc 1.735023 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.735023 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210434144 # number of integer regfile reads -system.cpu.int_regfile_writes 664206400 # number of integer regfile writes +system.cpu.rob.rob_reads 978192675 # The number of ROB reads +system.cpu.rob.rob_writes 1375166180 # The number of ROB writes +system.cpu.timesIdled 37006 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 863493 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052728 # Number of Instructions Simulated +system.cpu.committedOps 602360935 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052728 # Number of Instructions Simulated +system.cpu.cpi 0.576256 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.576256 # CPI: Total CPI of All Threads +system.cpu.ipc 1.735338 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.735338 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210352058 # number of integer regfile reads +system.cpu.int_regfile_writes 664199500 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905030713 # number of misc regfile reads -system.cpu.misc_regfile_writes 2676 # number of misc regfile writes -system.cpu.icache.replacements 62 # number of replacements -system.cpu.icache.tagsinuse 695.805278 # Cycle average of tags in use -system.cpu.icache.total_refs 67497251 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 819 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82414.225885 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905055598 # number of misc regfile reads +system.cpu.misc_regfile_writes 3110 # number of misc regfile writes +system.cpu.icache.replacements 66 # number of replacements +system.cpu.icache.tagsinuse 704.852693 # Cycle average of tags in use +system.cpu.icache.total_refs 67494169 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 836 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 80734.651914 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 695.805278 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.339749 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.339749 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67497251 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67497251 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67497251 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67497251 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67497251 # number of overall hits -system.cpu.icache.overall_hits::total 67497251 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1101 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1101 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1101 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1101 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1101 # number of overall misses -system.cpu.icache.overall_misses::total 1101 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37785500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37785500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37785500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37785500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37785500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37785500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67498352 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67498352 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67498352 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67498352 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67498352 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67498352 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34319.255223 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 704.852693 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.344166 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.344166 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67494169 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67494169 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67494169 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67494169 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67494169 # number of overall hits +system.cpu.icache.overall_hits::total 67494169 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1149 # 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Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 88231000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.647718 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999670 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 132066425 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 132066425 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 67860846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 67860846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1466 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1466 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1337 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1337 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87177000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.673413 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999676 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999676 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 132064751 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 132064751 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 67849620 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 67849620 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1690 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1690 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1554 # 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number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32262 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33044 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58299 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58299 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 90561 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 91343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 90561 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 91343 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24334000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1002753500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027087500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1820295000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1820295000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24334000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2823048500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2847382500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24334000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2823048500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2847382500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235918 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203691 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203691 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31117.647059 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.566549 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31223.434364 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 799 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32297 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33096 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58317 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58317 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 799 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90614 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91413 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 799 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90614 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91413 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24875000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003961000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028836000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1821234000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1821234000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24875000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2825195000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2850070000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24875000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2825195000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2850070000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163537 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235994 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31132.665832 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31085.271078 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31229.898657 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index f06b9ec67..867a31b3a 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index d3f3c8cc8..fda635c2d 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:43:07 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:54:39 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index f3821c915..1d050592c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3323130 # Simulator instruction rate (inst/s) -host_op_rate 3511472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1755802369 # Simulator tick rate (ticks/s) -host_mem_usage 216428 # Number of bytes of host memory used -host_seconds 171.54 # Real time elapsed on the host +host_inst_rate 2848986 # Simulator instruction rate (inst/s) +host_op_rate 3010454 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1505284316 # Simulator tick rate (ticks/s) +host_mem_usage 213580 # Number of bytes of host memory used +host_seconds 200.09 # Real time elapsed on the host sim_insts 570051644 # Number of instructions simulated sim_ops 602359851 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2680160157 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 602359851 # Nu system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 14843a60a..877a85204 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index eee2e0cb2..25af6cb73 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:45:54 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:58:09 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 52945d306..f70524856 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1880906 # Simulator instruction rate (inst/s) -host_op_rate 1986306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2635941289 # Simulator tick rate (ticks/s) -host_mem_usage 225340 # Number of bytes of host memory used -host_seconds 302.27 # Real time elapsed on the host +host_inst_rate 2008356 # Simulator instruction rate (inst/s) +host_op_rate 2120897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2814551305 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 283.09 # Real time elapsed on the host sim_insts 568539343 # Number of instructions simulated sim_ops 600398281 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5759488 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 600398281 # Nu system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index f9650cc7f..71cbbf675 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -514,9 +514,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index bd690b9dd..2d894fefb 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:26 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:02:50 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 30004011500 because target called exit() +Exiting @ tick 25988864000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index c606c0251..a17606260 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030004 # Number of seconds simulated -sim_ticks 30004011500 # Number of ticks simulated -final_tick 30004011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025989 # Number of seconds simulated +sim_ticks 25988864000 # Number of ticks simulated +final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 194545 # Simulator instruction rate (inst/s) -host_op_rate 195941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64427791 # Simulator tick rate (ticks/s) -host_mem_usage 360100 # Number of bytes of host memory used -host_seconds 465.70 # Real time elapsed on the host -sim_insts 90599351 # Number of instructions simulated -sim_ops 91249905 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 997760 # Number of bytes read from this memory -system.physmem.bytes_inst_read 45184 # Number of instructions bytes read from this memory +host_inst_rate 238212 # Simulator instruction rate (inst/s) +host_op_rate 239922 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68332245 # Simulator tick rate (ticks/s) +host_mem_usage 357212 # Number of bytes of host memory used +host_seconds 380.33 # Real time elapsed on the host +sim_insts 90599356 # Number of instructions simulated +sim_ops 91249910 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 999040 # Number of bytes read from this memory +system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory -system.physmem.num_reads 15590 # Number of read requests responded to by this memory +system.physmem.num_reads 15610 # Number of read requests responded to by this memory system.physmem.num_writes 32 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 33254220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1505932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 68258 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 33322478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 38441080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1775530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 78803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 38519883 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 60008024 # number of cpu cycles simulated +system.cpu.numCycles 51977729 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26814888 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22097408 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 908993 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11644795 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11349875 # Number of BTB hits +system.cpu.BPredUnit.lookups 27100787 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22324909 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 913851 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11625204 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11498872 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 60971 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 9988 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14353439 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128015722 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26814888 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11410846 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24114191 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4769366 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 17672895 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 61157 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 10323 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14508615 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 130146910 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27100787 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11560029 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24493529 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4999674 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8879281 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1085 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 13983254 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 369829 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 59980295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.152543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.127200 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 50 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14156722 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 388066 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 51938784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.527703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.247354 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 35906918 59.86% 59.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3423177 5.71% 65.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2008077 3.35% 68.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1555866 2.59% 71.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1665852 2.78% 74.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2959461 4.93% 79.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1530954 2.55% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1083113 1.81% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9846877 16.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27487299 52.92% 52.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3456218 6.65% 59.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2037280 3.92% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1594827 3.07% 66.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1702478 3.28% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2979904 5.74% 75.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1536396 2.96% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1112311 2.14% 80.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10032071 19.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 59980295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.446855 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.133310 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17244522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15439127 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22437836 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1028996 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3829814 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4444165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8973 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126393401 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43020 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3829814 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19245787 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2026344 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8384525 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21437306 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5056519 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122679258 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 280519 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3795375 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 142938307 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 534568737 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 534562281 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6456 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35508836 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 621620 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 624255 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13585300 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29418557 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5501060 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1379571 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 681227 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 117000498 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 611217 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 104991352 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 35829 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26158745 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 64243821 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 56369 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 59980295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.750431 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.873941 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 51938784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.521392 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.503898 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17258666 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6822276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22930941 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 878432 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4048469 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4484484 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8960 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 128309268 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42973 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4048469 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19038937 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2026641 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 195067 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21988132 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4641538 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124853766 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 286024 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3901771 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 441 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145615724 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 543819179 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 543813062 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6117 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429479 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38186245 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20008 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20006 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 11296413 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29738779 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5601526 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2062082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1203344 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119239629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22672 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105633795 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 86270 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27804178 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69103102 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12544 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 51938784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.033813 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.918657 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 20705588 34.52% 34.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13184290 21.98% 56.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8487470 14.15% 70.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6459646 10.77% 81.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4931435 8.22% 89.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2870978 4.79% 94.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2481638 4.14% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 391274 0.65% 99.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 467976 0.78% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 14084713 27.12% 27.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11449450 22.04% 49.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8003608 15.41% 64.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6710442 12.92% 77.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5305637 10.22% 87.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2900837 5.59% 93.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2546575 4.90% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 460556 0.89% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 476966 0.92% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 59980295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 51938784 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31457 4.81% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 343779 52.58% 57.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 278563 42.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33927 5.08% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 354815 53.12% 58.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 279170 41.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74214604 70.69% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10958 0.01% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 201 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 251 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25591383 24.37% 95.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5173950 4.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74740578 70.75% 70.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10525 0.01% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 195 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 237 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25722669 24.35% 95.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5159588 4.88% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 104991352 # Type of FU issued -system.cpu.iq.rate 1.749622 # Inst issue rate -system.cpu.iq.fu_busy_cnt 653826 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006227 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 270651681 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 143770389 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102345485 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1384 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 418 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105644695 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 483 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 378050 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105633795 # Type of FU issued +system.cpu.iq.rate 2.032290 # Inst issue rate +system.cpu.iq.fu_busy_cnt 667939 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006323 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263959647 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 147067415 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102938725 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 936 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1347 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 404 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106301267 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 467 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 423068 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6842681 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23943 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1595 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 754307 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7162902 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8413 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3100 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 854772 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 497 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30477 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39235 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3829814 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 196269 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 34070 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 117648153 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 398714 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29418557 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5501060 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 607315 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13787 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1140 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1595 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 486496 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 484094 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 970590 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 103957070 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25266637 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1034282 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4048469 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 193737 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33246 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119298911 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 399459 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29738779 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5601526 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18769 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13636 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1014 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3100 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 499711 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 490212 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 989923 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104558374 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25377273 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1075421 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 36438 # number of nop insts executed -system.cpu.iew.exec_refs 30369134 # number of memory reference insts executed -system.cpu.iew.exec_branches 21275406 # Number of branches executed -system.cpu.iew.exec_stores 5102497 # Number of stores executed -system.cpu.iew.exec_rate 1.732386 # Inst execution rate -system.cpu.iew.wb_sent 102646599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102345903 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60560786 # num instructions producing a value -system.cpu.iew.wb_consumers 98602756 # num instructions consuming a value +system.cpu.iew.exec_nop 36610 # number of nop insts executed +system.cpu.iew.exec_refs 30470186 # number of memory reference insts executed +system.cpu.iew.exec_branches 21355608 # Number of branches executed +system.cpu.iew.exec_stores 5092913 # Number of stores executed +system.cpu.iew.exec_rate 2.011600 # Inst execution rate +system.cpu.iew.wb_sent 103258351 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102939129 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62202150 # num instructions producing a value +system.cpu.iew.wb_consumers 103963576 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.705537 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.614190 # average fanout of values written-back +system.cpu.iew.wb_rate 1.980447 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598307 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 90611960 # The number of committed instructions -system.cpu.commit.commitCommittedOps 91262514 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26386952 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554848 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 912021 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 56150482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.625320 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.343724 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 90611965 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262519 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 28037719 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10128 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 916929 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 47890316 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.905657 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507554 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23848704 42.47% 42.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15483848 27.58% 70.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4738925 8.44% 78.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3887159 6.92% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1619823 2.88% 88.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 955795 1.70% 90.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 662165 1.18% 91.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 224422 0.40% 91.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4729641 8.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17540600 36.63% 36.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13534361 28.26% 64.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4502880 9.40% 74.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3873758 8.09% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516151 3.17% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 799389 1.67% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 846315 1.77% 88.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253211 0.53% 89.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5023651 10.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 56150482 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611960 # Number of instructions committed -system.cpu.commit.committedOps 91262514 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 47890316 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611965 # Number of instructions committed +system.cpu.commit.committedOps 91262519 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322629 # Number of memory references committed -system.cpu.commit.loads 22575876 # Number of loads committed +system.cpu.commit.refs 27322631 # Number of memory references committed +system.cpu.commit.loads 22575877 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722470 # Number of branches committed +system.cpu.commit.branches 18722471 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533318 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4729641 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5023651 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 169064573 # The number of ROB reads -system.cpu.rob.rob_writes 239150312 # The number of ROB writes -system.cpu.timesIdled 1544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27729 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599351 # Number of Instructions Simulated -system.cpu.committedOps 91249905 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599351 # Number of Instructions Simulated -system.cpu.cpi 0.662345 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.662345 # CPI: Total CPI of All Threads -system.cpu.ipc 1.509787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.509787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 494492343 # number of integer regfile reads -system.cpu.int_regfile_writes 120192106 # number of integer regfile writes -system.cpu.fp_regfile_reads 207 # number of floating regfile reads -system.cpu.fp_regfile_writes 538 # number of floating regfile writes -system.cpu.misc_regfile_reads 181239075 # number of misc regfile reads -system.cpu.misc_regfile_writes 11602 # number of misc regfile writes +system.cpu.rob.rob_reads 162161169 # The number of ROB reads +system.cpu.rob.rob_writes 242671240 # The number of ROB writes +system.cpu.timesIdled 1828 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38945 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599356 # Number of Instructions Simulated +system.cpu.committedOps 91249910 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599356 # Number of Instructions Simulated +system.cpu.cpi 0.573710 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.573710 # CPI: Total CPI of All Threads +system.cpu.ipc 1.743042 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.743042 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 497076309 # number of integer regfile reads +system.cpu.int_regfile_writes 120895703 # number of integer regfile writes +system.cpu.fp_regfile_reads 198 # number of floating regfile reads +system.cpu.fp_regfile_writes 527 # number of floating regfile writes +system.cpu.misc_regfile_reads 183813486 # number of misc regfile reads +system.cpu.misc_regfile_writes 11604 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 625.228438 # Cycle average of tags in use -system.cpu.icache.total_refs 13982297 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 731 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19127.629275 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 649.670012 # Cycle average of tags in use +system.cpu.icache.total_refs 14155750 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 749 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18899.532710 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.228438 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305287 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305287 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13982297 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13982297 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13982297 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13982297 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13982297 # number of overall hits -system.cpu.icache.overall_hits::total 13982297 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses -system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33318000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33318000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33318000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33318000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33318000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33318000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13983254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13983254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13983254 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13983254 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13983254 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13983254 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34815.047022 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34815.047022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34815.047022 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 649.670012 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.317222 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.317222 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14155750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14155750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14155750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14155750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14155750 # number of overall hits +system.cpu.icache.overall_hits::total 14155750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 972 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 972 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 972 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 972 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 972 # number of overall misses +system.cpu.icache.overall_misses::total 972 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33892500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33892500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33892500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33892500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33892500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33892500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14156722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14156722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14156722 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14156722 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,214 +382,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 731 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 731 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 731 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 731 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 731 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 731 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25047000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25047000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25047000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25047000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25047000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25047000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34264.021888 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34264.021888 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34264.021888 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 749 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 749 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 749 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 749 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 749 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25625000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25625000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25625000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25625000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943524 # number of replacements -system.cpu.dcache.tagsinuse 3583.229064 # Cycle average of tags in use -system.cpu.dcache.total_refs 28391066 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947620 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.960391 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 10655820000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3583.229064 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.874812 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.874812 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23819030 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23819030 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4560353 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4560353 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5796 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28379383 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28379383 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28379383 # number of overall hits -system.cpu.dcache.overall_hits::total 28379383 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 991638 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 991638 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 174628 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 174628 # number of WriteReq misses +system.cpu.dcache.replacements 943602 # number of replacements +system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use +system.cpu.dcache.total_refs 28436874 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947698 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.006261 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8214901000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3646.405021 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.890236 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.890236 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23866253 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23866253 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4558926 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4558926 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5797 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5797 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28425179 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28425179 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28425179 # number of overall hits +system.cpu.dcache.overall_hits::total 28425179 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1004103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1004103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 176055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 176055 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1166266 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1166266 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1166266 # number of overall misses -system.cpu.dcache.overall_misses::total 1166266 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5615598500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5615598500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4530256968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4530256968 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 129500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10145855468 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10145855468 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10145855468 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10145855468 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24810668 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24810668 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1180158 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1180158 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1180158 # number of overall misses +system.cpu.dcache.overall_misses::total 1180158 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5784178500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5784178500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4612267011 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4612267011 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 129000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10396445511 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10396445511 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10396445511 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10396445511 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24870356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24870356 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5796 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5796 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29545649 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29545649 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29545649 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29545649 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039968 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036880 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001357 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5662.952106 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25942.328653 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8699.435179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8699.435179 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23124041 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29605337 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29605337 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8085 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.116388 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942876 # number of writebacks -system.cpu.dcache.writebacks::total 942876 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87943 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 87943 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 130703 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 130703 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks +system.cpu.dcache.writebacks::total 942908 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 99918 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 99918 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132542 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 132542 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 218646 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 218646 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 218646 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 218646 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903695 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903695 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43925 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43925 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947620 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947620 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947620 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947620 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2331156500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2331156500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1079888101 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1079888101 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3411044601 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3411044601 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3411044601 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3411044601 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036424 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032073 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032073 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2579.583266 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24584.817325 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3599.591187 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3599.591187 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 232460 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 232460 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 232460 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 232460 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904185 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904185 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43513 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43513 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 484896500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000383 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.321993 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015707 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015707 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.362606 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.849711 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.040308 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.362606 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31104.407417 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.362606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31104.407417 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 721 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 355 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14534 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 721 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14889 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15610 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 721 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14889 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15610 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22414000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11074500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 33488500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452032500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452032500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22414000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463107000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 485521000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22414000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 4140383de..4c0e3ba04 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -100,9 +100,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index f67da13a2..439b5027c 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:51:19 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:03:02 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 336dcb8a1..1ec302d05 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240666000 # Number of ticks simulated final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2969105 # Simulator instruction rate (inst/s) -host_op_rate 2990423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1777502999 # Simulator tick rate (ticks/s) -host_mem_usage 349280 # Number of bytes of host memory used -host_seconds 30.52 # Real time elapsed on the host +host_inst_rate 2795699 # Simulator instruction rate (inst/s) +host_op_rate 2815772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1673691127 # Simulator tick rate (ticks/s) +host_mem_usage 346432 # Number of bytes of host memory used +host_seconds 32.41 # Real time elapsed on the host sim_insts 90602415 # Number of instructions simulated sim_ops 91252969 # Number of ops (including micro ops) simulated system.physmem.bytes_read 521339715 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 91252969 # Nu system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15564339 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls system.cpu.num_int_insts 72525682 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 3779c19fc..f9dbf6b5f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -183,9 +183,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index d74925785..d8b8bc833 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:51:58 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:03:45 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 4a03aab99..f3ad4a424 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.148086 # Nu sim_ticks 148086239000 # Number of ticks simulated final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1772363 # Simulator instruction rate (inst/s) -host_op_rate 1785070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2897675173 # Simulator tick rate (ticks/s) -host_mem_usage 358192 # Number of bytes of host memory used -host_seconds 51.11 # Real time elapsed on the host +host_inst_rate 1876733 # Simulator instruction rate (inst/s) +host_op_rate 1890189 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3068313156 # Simulator tick rate (ticks/s) +host_mem_usage 355600 # Number of bytes of host memory used +host_seconds 48.26 # Real time elapsed on the host sim_insts 90576869 # Number of instructions simulated sim_ops 91226321 # Number of ops (including micro ops) simulated system.physmem.bytes_read 986112 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 91226321 # Nu system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15564339 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls system.cpu.num_int_insts 72525682 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 9cdb8964a..d81753d20 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -514,9 +514,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index af8c70dcf..7c2d8a83b 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:18:33 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:04:44 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 234107886500 because target called exit() +Exiting @ tick 233057542500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 95047c0ce..e5e06c89f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.234108 # Number of seconds simulated -sim_ticks 234107886500 # Number of ticks simulated -final_tick 234107886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233058 # Number of seconds simulated +sim_ticks 233057542500 # Number of ticks simulated +final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148403 # Simulator instruction rate (inst/s) -host_op_rate 167177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68261843 # Simulator tick rate (ticks/s) -host_mem_usage 232040 # Number of bytes of host memory used -host_seconds 3429.56 # Real time elapsed on the host -sim_insts 508954871 # Number of instructions simulated -sim_ops 573341432 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15193216 # Number of bytes read from this memory -system.physmem.bytes_inst_read 241280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10938560 # Number of bytes written to this memory -system.physmem.num_reads 237394 # Number of read requests responded to by this memory -system.physmem.num_writes 170915 # Number of write requests responded to by this memory +host_inst_rate 173099 # Simulator instruction rate (inst/s) +host_op_rate 194997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79264326 # Simulator tick rate (ticks/s) +host_mem_usage 229800 # Number of bytes of host memory used +host_seconds 2940.26 # Real time elapsed on the host +sim_insts 508954936 # Number of instructions simulated +sim_ops 573341497 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15214144 # Number of bytes read from this memory +system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10947904 # Number of bytes written to this memory +system.physmem.num_reads 237721 # Number of read requests responded to by this memory +system.physmem.num_writes 171061 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 64898352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1030636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 46724440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 111622792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,143 +64,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 468215774 # number of cpu cycles simulated +system.cpu.numCycles 466115086 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 200061766 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 161279268 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 13261114 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 110371027 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 98350021 # Number of BTB hits +system.cpu.BPredUnit.lookups 200399400 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 157559949 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13227368 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 107557824 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 98829929 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10012114 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2451761 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 136559610 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 898175750 # Number of instructions fetch has processed -system.cpu.fetch.Branches 200061766 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 108362135 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 197576941 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 54094157 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 91756620 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 80 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 71734 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 126283016 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3812130 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 464400798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.257289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.102621 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10084316 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2451057 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 137234241 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 896616118 # Number of instructions fetch has processed +system.cpu.fetch.Branches 200399400 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 108914245 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 197636410 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 54052361 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 88992455 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 126860220 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3882835 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 462293499 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.263975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.101557 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 266835612 57.46% 57.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 16224757 3.49% 60.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21301662 4.59% 65.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22971866 4.95% 70.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 24200733 5.21% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13160700 2.83% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13387272 2.88% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12932496 2.78% 84.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 73385700 15.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 264670388 57.25% 57.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16165090 3.50% 60.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21531844 4.66% 65.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22983454 4.97% 70.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24508471 5.30% 75.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13134616 2.84% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13371052 2.89% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12920313 2.79% 84.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 73008271 15.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 464400798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.427285 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.918295 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 151819691 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 87315779 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 182356495 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4679019 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 38229814 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 32058950 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 208727 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 978247672 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304018 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 38229814 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 165098123 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6680773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 67210378 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 173611976 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13569734 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 900335199 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1400 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2808611 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7742666 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1050683608 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3921835451 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3921830870 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4581 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199728 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 378483880 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6257639 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6252483 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 74230305 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 187204403 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74981295 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17030714 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11234948 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 805916100 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7086662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 700681614 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1544151 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 236754435 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 596849341 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3208414 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 464400798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.508786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.706470 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 462293499 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.429935 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.923594 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 152295850 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 84600682 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 182545472 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4580461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 38271034 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32275508 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160463 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 977106792 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 311018 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 38271034 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 165689191 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6700759 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 64642468 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 173582675 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13407372 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 899108485 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1442 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2810546 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7739563 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 106 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1049429059 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3915911188 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3915906253 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4935 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199832 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 377229227 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5987863 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5982547 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 72814411 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 187298810 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75062120 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17028922 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10874751 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 806565254 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6815793 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 700720615 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1613210 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 237113606 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 598814504 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3094720 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 462293499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.515748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.710183 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 194454987 41.87% 41.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75651609 16.29% 58.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69485384 14.96% 73.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 61139015 13.17% 86.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 35296693 7.60% 93.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15466096 3.33% 97.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7603561 1.64% 98.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3924050 0.84% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1379403 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 192936549 41.73% 41.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75135766 16.25% 57.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69228865 14.98% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 61089071 13.21% 86.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 35380643 7.65% 93.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15554118 3.36% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7568076 1.64% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4045000 0.87% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1355411 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 464400798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 462293499 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 453814 4.63% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6693711 68.30% 72.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2653315 27.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 467117 4.69% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6749256 67.80% 72.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2738977 27.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 472302081 67.41% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386521 0.06% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 472287152 67.40% 67.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 386091 0.06% 67.46% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 170 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 198 0.00% 67.46% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued @@ -226,153 +226,153 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.46% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 162598638 23.21% 90.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65394201 9.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 162565842 23.20% 90.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65481329 9.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 700681614 # Type of FU issued -system.cpu.iq.rate 1.496493 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9800840 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013988 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1877108639 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1049814796 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 668235184 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 700720615 # Type of FU issued +system.cpu.iq.rate 1.503321 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9955350 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014207 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1875302857 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1050553482 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 668216510 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 710482264 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9094204 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 710675747 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9109880 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 60431419 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 43883 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 61918 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17377390 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 60525813 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 50692 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 63405 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17458202 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20851 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 399 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 20818 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 376 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 38229814 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2886721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 175953 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 821878596 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 9525062 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 187204403 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74981295 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5597916 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 86243 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8756 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 61918 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10539331 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 7737636 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18276967 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 681941706 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 155293366 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18739908 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 38271034 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2890868 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 175492 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 822161545 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8144996 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 187298810 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75062120 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5327019 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 85808 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8514 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 63405 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10568276 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 7702731 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18271007 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 681861282 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 155223597 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18859333 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8875834 # number of nop insts executed -system.cpu.iew.exec_refs 219203468 # number of memory reference insts executed -system.cpu.iew.exec_branches 142018558 # Number of branches executed -system.cpu.iew.exec_stores 63910102 # Number of stores executed -system.cpu.iew.exec_rate 1.456469 # Inst execution rate -system.cpu.iew.wb_sent 673034239 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 668235200 # cumulative count of insts written-back -system.cpu.iew.wb_producers 381399199 # num instructions producing a value -system.cpu.iew.wb_consumers 655303832 # num instructions consuming a value +system.cpu.iew.exec_nop 8780498 # number of nop insts executed +system.cpu.iew.exec_refs 219185272 # number of memory reference insts executed +system.cpu.iew.exec_branches 141958281 # Number of branches executed +system.cpu.iew.exec_stores 63961675 # Number of stores executed +system.cpu.iew.exec_rate 1.462860 # Inst execution rate +system.cpu.iew.wb_sent 673014173 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 668216526 # cumulative count of insts written-back +system.cpu.iew.wb_producers 381765084 # num instructions producing a value +system.cpu.iew.wb_consumers 656387982 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.427195 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.582019 # average fanout of values written-back +system.cpu.iew.wb_rate 1.433587 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.581615 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510298755 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685316 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 247211019 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3878248 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15402240 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 426170985 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.348485 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.065618 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510298820 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685381 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 247493136 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721073 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15415046 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 424022466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.355318 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.071268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 207821757 48.76% 48.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103278684 24.23% 73.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 40154361 9.42% 82.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19502589 4.58% 87.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17446456 4.09% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7236627 1.70% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7721645 1.81% 94.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3779614 0.89% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 19229252 4.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 206316988 48.66% 48.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102533575 24.18% 72.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 40145036 9.47% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19513900 4.60% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17437160 4.11% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7239208 1.71% 92.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7753458 1.83% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3810522 0.90% 95.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 19272619 4.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 426170985 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510298755 # Number of instructions committed -system.cpu.commit.committedOps 574685316 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 424022466 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510298820 # Number of instructions committed +system.cpu.commit.committedOps 574685381 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376889 # Number of memory references committed -system.cpu.commit.loads 126772984 # Number of loads committed +system.cpu.commit.refs 184376915 # Number of memory references committed +system.cpu.commit.loads 126772997 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192169 # Number of branches committed +system.cpu.commit.branches 120192182 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701413 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701465 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 19229252 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 19272619 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1228830930 # The number of ROB reads -system.cpu.rob.rob_writes 1682168121 # The number of ROB writes -system.cpu.timesIdled 98147 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3814976 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508954871 # Number of Instructions Simulated -system.cpu.committedOps 573341432 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508954871 # Number of Instructions Simulated -system.cpu.cpi 0.919955 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.919955 # CPI: Total CPI of All Threads -system.cpu.ipc 1.087009 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.087009 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3163894948 # number of integer regfile reads -system.cpu.int_regfile_writes 777442018 # number of integer regfile writes +system.cpu.rob.rob_reads 1226921226 # The number of ROB reads +system.cpu.rob.rob_writes 1682775882 # The number of ROB writes +system.cpu.timesIdled 98525 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3821587 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508954936 # Number of Instructions Simulated +system.cpu.committedOps 573341497 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508954936 # Number of Instructions Simulated +system.cpu.cpi 0.915828 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.915828 # CPI: Total CPI of All Threads +system.cpu.ipc 1.091908 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.091908 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3163594515 # number of integer regfile reads +system.cpu.int_regfile_writes 777373809 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1131493621 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463940 # number of misc regfile writes -system.cpu.icache.replacements 16054 # number of replacements -system.cpu.icache.tagsinuse 1101.947975 # Cycle average of tags in use -system.cpu.icache.total_refs 126263236 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17918 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7046.725974 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1130092901 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463966 # number of misc regfile writes +system.cpu.icache.replacements 16105 # number of replacements +system.cpu.icache.tagsinuse 1117.727093 # Cycle average of tags in use +system.cpu.icache.total_refs 126840323 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17981 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7054.130638 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.947975 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.538061 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.538061 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 126263236 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 126263236 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 126263236 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 126263236 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 126263236 # number of overall hits -system.cpu.icache.overall_hits::total 126263236 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19780 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19780 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19780 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19780 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19780 # number of overall misses -system.cpu.icache.overall_misses::total 19780 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 264112500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 264112500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 264112500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 264112500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 264112500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 264112500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 126283016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 126283016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 126283016 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 126283016 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 126283016 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 126283016 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1117.727093 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.545765 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.545765 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 126840329 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 126840329 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 126840329 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 126840329 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 126840329 # number of overall hits +system.cpu.icache.overall_hits::total 126840329 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19891 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19891 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19891 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19891 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19891 # number of overall misses +system.cpu.icache.overall_misses::total 19891 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 267894500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 267894500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 267894500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 267894500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 267894500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13352.502528 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13352.502528 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13352.502528 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,224 +381,226 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1738 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1738 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1738 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1738 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1738 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1738 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18042 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 18042 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 18042 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 18042 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 18042 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 18042 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168794500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168794500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1759 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1759 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1759 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1759 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1759 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1759 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18132 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 18132 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 18132 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 18132 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 18132 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 18132 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171640500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 171640500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171640500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 171640500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9355.642390 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9355.642390 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9355.642390 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1204439 # number of replacements -system.cpu.dcache.tagsinuse 4053.213241 # Cycle average of tags in use -system.cpu.dcache.total_refs 197393966 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1208535 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.333264 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5508997000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4053.213241 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989554 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989554 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 140143872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 140143872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52777243 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52777243 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2240634 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2240634 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2231969 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2231969 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 192921115 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 192921115 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 192921115 # number of overall hits -system.cpu.dcache.overall_hits::total 192921115 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1321702 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1321702 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1462063 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1462063 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 79 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 79 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2783765 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2783765 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2783765 # number of overall misses -system.cpu.dcache.overall_misses::total 2783765 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15361891000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15361891000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24945206993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24945206993 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 848000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 848000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40307097993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40307097993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40307097993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40307097993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 141465574 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 141465574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1204809 # number of replacements +system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use +system.cpu.dcache.total_refs 197317737 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1208905 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.220217 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4052.906677 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989479 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989479 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 140063979 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 140063979 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52782968 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52782968 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2238489 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2238489 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2231982 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2231982 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 192846947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 192846947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 192846947 # number of overall hits +system.cpu.dcache.overall_hits::total 192846947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1318830 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1318830 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1456338 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1456338 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 78 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 78 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2775168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2775168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2775168 # number of overall misses +system.cpu.dcache.overall_misses::total 2775168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15287682000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15287682000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25164058992 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25164058992 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 845500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 845500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40451740992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40451740992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40451740992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40451740992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 141382809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 141382809 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2240713 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2240713 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231969 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2231969 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 195704880 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 195704880 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 195704880 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 195704880 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009343 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026956 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2238567 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2238567 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231982 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2231982 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 195622115 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 195622115 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014224 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014224 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11622.809832 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17061.649869 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10734.177215 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14479.346494 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14479.346494 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 557000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6054.347826 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6543.478261 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1073316 # number of writebacks -system.cpu.dcache.writebacks::total 1073316 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 452437 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 452437 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1122680 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1122680 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 79 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 79 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1575117 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1575117 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1575117 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1575117 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 869265 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 869265 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 339383 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 339383 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1208648 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1208648 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1208648 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1208648 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6267661500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6267661500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319283499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319283499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10586944999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10586944999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10586944999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10586944999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006145 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006257 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7210.300081 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12726.870524 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8759.328604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8759.328604 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1073322 # number of writebacks +system.cpu.dcache.writebacks::total 1073322 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 451055 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 451055 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1115056 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1115056 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 78 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1566111 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1566111 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1566111 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1566111 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 867775 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 867775 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 341282 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 341282 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1209057 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1209057 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1209057 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1209057 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6208585000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6208585000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4381340497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4381340497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10589925497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 218164 # number of replacements -system.cpu.l2cache.tagsinuse 21000.033728 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1558335 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 238544 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.532694 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 171274972000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 13326.233145 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 198.028961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7475.771622 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.406684 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.228142 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.640870 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14176 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 742295 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 756471 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1073316 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1073316 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 79 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 79 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232581 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232581 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14176 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 974876 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 989052 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14176 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 974876 # number of overall hits -system.cpu.l2cache.overall_hits::total 989052 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3773 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 126291 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 130064 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 107358 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 107358 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7375243500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 119582500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index a927ae45c..c2570b640 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -100,9 +100,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 2e77896ee..305853526 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:54:26 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:09:21 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 3614f4202..b71701baf 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu sim_ticks 290498972000 # Number of ticks simulated final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3161801 # Simulator instruction rate (inst/s) -host_op_rate 3563665 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1813132581 # Simulator tick rate (ticks/s) -host_mem_usage 219872 # Number of bytes of host memory used -host_seconds 160.22 # Real time elapsed on the host +host_inst_rate 2826052 # Simulator instruction rate (inst/s) +host_op_rate 3185244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1620598119 # Simulator tick rate (ticks/s) +host_mem_usage 217292 # Number of bytes of host memory used +host_seconds 179.25 # Real time elapsed on the host sim_insts 506581615 # Number of instructions simulated sim_ops 570968176 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2489298238 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 570968176 # Nu system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 15725605 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls system.cpu.num_int_insts 470727703 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 61506a548..eb4eafcdf 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -183,9 +183,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index b2e0bf661..3920067a6 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:18:46 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:11:24 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 1dce1fffd..97f343640 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.722234 # Nu sim_ticks 722234364000 # Number of ticks simulated final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1812748 # Simulator instruction rate (inst/s) -host_op_rate 2042661 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2592600297 # Simulator tick rate (ticks/s) -host_mem_usage 228776 # Number of bytes of host memory used -host_seconds 278.58 # Real time elapsed on the host +host_inst_rate 1807546 # Simulator instruction rate (inst/s) +host_op_rate 2036799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2585159889 # Simulator tick rate (ticks/s) +host_mem_usage 226208 # Number of bytes of host memory used +host_seconds 279.38 # Real time elapsed on the host sim_insts 504986861 # Number of instructions simulated sim_ops 569034848 # Number of ops (including micro ops) simulated system.physmem.bytes_read 14797056 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 569034848 # Nu system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 15725605 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls system.cpu.num_int_insts 470727703 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 20b788768..7bb4edd53 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index fc4913b5c..67a784ea7 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:18:58 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:12:32 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -12,5 +12,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.090000 -Exiting @ tick 99661890000 because target called exit() +OO-style eon Time= 0.070000 +Exiting @ tick 71774859500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index db6cb13f6..12f1040c9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.099662 # Number of seconds simulated -sim_ticks 99661890000 # Number of ticks simulated -final_tick 99661890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071775 # Number of seconds simulated +sim_ticks 71774859500 # Number of ticks simulated +final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162959 # Simulator instruction rate (inst/s) -host_op_rate 208335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59481796 # Simulator tick rate (ticks/s) -host_mem_usage 235924 # Number of bytes of host memory used -host_seconds 1675.50 # Real time elapsed on the host -sim_insts 273037886 # Number of instructions simulated -sim_ops 349065611 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 467712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 196352 # Number of instructions bytes read from this memory +host_inst_rate 200202 # Simulator instruction rate (inst/s) +host_op_rate 255946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52626024 # Simulator tick rate (ticks/s) +host_mem_usage 233120 # Number of bytes of host memory used +host_seconds 1363.87 # Real time elapsed on the host +sim_insts 273048474 # Number of instructions simulated +sim_ops 349076199 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 472896 # Number of bytes read from this memory +system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7308 # Number of read requests responded to by this memory +system.physmem.num_reads 7389 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 4692987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1970181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 4692987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,315 +63,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 199323781 # number of cpu cycles simulated +system.cpu.numCycles 143549720 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 36425277 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21814093 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2195714 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 21857400 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17699652 # Number of BTB hits +system.cpu.BPredUnit.lookups 37175542 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22262323 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2214096 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 22505770 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 18082192 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6983514 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 50540 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40843667 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 325977974 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36425277 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24683166 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73206871 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8096294 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 79308750 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3272 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39251627 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 692341 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 199214408 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.104516 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.205209 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7072101 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 52600 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 41561697 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 332366381 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37175542 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25154293 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 74569841 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8920940 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20643175 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 4492 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39951299 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710527 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 143433675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.978110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454958 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 126685996 63.59% 63.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7392332 3.71% 67.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5861965 2.94% 70.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6253075 3.14% 73.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4927164 2.47% 75.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4136176 2.08% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3211031 1.61% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4254661 2.14% 81.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36492008 18.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69560380 48.50% 48.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7529870 5.25% 53.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5927266 4.13% 57.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6353418 4.43% 62.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5053258 3.52% 65.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4245115 2.96% 68.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3249040 2.27% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4338891 3.03% 74.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 37176437 25.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 199214408 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.182744 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.635419 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 48091997 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 74157554 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67325954 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3856814 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5782089 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7547074 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69910 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 411121431 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 208451 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5782089 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 55063328 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1232045 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57746804 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 64402683 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14987459 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 399689928 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 40994 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8558988 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 23 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 436461452 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2357603268 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1290965650 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1066637618 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384568055 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51893397 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3989281 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4086766 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48885430 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104583194 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 92996995 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2832218 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4219793 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 383881743 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3901955 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374859266 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1372272 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 37676176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 103140014 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 346328 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 199214408 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.881688 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.014261 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 143433675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258973 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.315340 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 48398038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15922899 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70106313 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2422163 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6584262 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7647961 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70686 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 419107715 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 208401 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6584262 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 54237445 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1551128 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 362766 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 66624532 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14073542 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 408263314 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1648402 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10108765 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 752 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 447190592 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2407780645 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1318183800 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1089596845 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584999 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 62605593 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23936 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23899 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35817763 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106133186 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93562284 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4587440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5646194 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 394242574 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 33887 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 379407553 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1341475 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 44167400 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 116755410 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9405 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 143433675 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.645178 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.047092 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75091477 37.69% 37.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 33471491 16.80% 54.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 23546496 11.82% 66.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17816115 8.94% 75.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22176914 11.13% 86.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15007629 7.53% 93.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8468208 4.25% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2797235 1.40% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 838843 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29947758 20.88% 20.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20633542 14.39% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21077069 14.69% 49.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18246072 12.72% 62.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24216587 16.88% 79.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16050569 11.19% 90.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9012327 6.28% 97.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3309506 2.31% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 940245 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 199214408 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 143433675 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3057 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5025 0.03% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 40437 0.24% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 3591 0.02% 0.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 364 0.00% 0.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 63031 0.37% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 1376 0.01% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 149950 0.89% 1.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8836509 52.25% 53.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7809442 46.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9527 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4696 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 47773 0.27% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7824 0.04% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 381 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 194196 1.08% 1.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4065 0.02% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241389 1.34% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9461548 52.57% 55.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8027461 44.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 127218722 33.94% 33.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147662 0.57% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 1 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6752754 1.80% 36.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8445549 2.25% 38.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3419085 0.91% 39.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1579460 0.42% 39.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20849528 5.56% 45.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172342 1.91% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7118324 1.90% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101990541 27.21% 76.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 87990007 23.47% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 129140993 34.04% 34.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2178888 0.57% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6841737 1.80% 36.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8706483 2.29% 38.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3462240 0.91% 39.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1609824 0.42% 40.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21270001 5.61% 45.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182346 1.89% 47.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7142588 1.88% 49.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102963295 27.14% 76.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88733868 23.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374859266 # Type of FU issued -system.cpu.iq.rate 1.880655 # Inst issue rate -system.cpu.iq.fu_busy_cnt 16912785 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.045118 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 719593529 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 296504031 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250306667 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 247624468 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 128964922 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117586691 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 264413654 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 127358397 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8761278 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 379407553 # Type of FU issued +system.cpu.iq.rate 2.643039 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17998863 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047439 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 670841771 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 305961612 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253223434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 250747348 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132496015 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118776381 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 268120952 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129285464 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10792483 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9934214 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 114912 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 9298 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10621174 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11482088 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 116027 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13932 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11184344 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 180 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 9709 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 181 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5782089 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25749 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2296 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 387833269 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1480942 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104583194 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 92996995 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3890825 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 225 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 9298 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1748842 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 550283 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2299125 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370161123 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100475616 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4698143 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6584262 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34186 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1479 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 394326849 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1347232 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106133186 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93562284 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22722 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 192 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 169 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13932 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1780753 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 562062 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2342815 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 374477920 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101438803 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4929633 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 49571 # number of nop insts executed -system.cpu.iew.exec_refs 187121240 # number of memory reference insts executed -system.cpu.iew.exec_branches 32102790 # Number of branches executed -system.cpu.iew.exec_stores 86645624 # Number of stores executed -system.cpu.iew.exec_rate 1.857085 # Inst execution rate -system.cpu.iew.wb_sent 368581318 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 367893358 # cumulative count of insts written-back -system.cpu.iew.wb_producers 175547849 # num instructions producing a value -system.cpu.iew.wb_consumers 345820695 # num instructions consuming a value +system.cpu.iew.exec_nop 50388 # number of nop insts executed +system.cpu.iew.exec_refs 188856020 # number of memory reference insts executed +system.cpu.iew.exec_branches 32491949 # Number of branches executed +system.cpu.iew.exec_stores 87417217 # Number of stores executed +system.cpu.iew.exec_rate 2.608698 # Inst execution rate +system.cpu.iew.wb_sent 372876985 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371999815 # cumulative count of insts written-back +system.cpu.iew.wb_producers 185166823 # num instructions producing a value +system.cpu.iew.wb_consumers 368327153 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.845707 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.507627 # average fanout of values written-back +system.cpu.iew.wb_rate 2.591435 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502724 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 273038498 # The number of committed instructions -system.cpu.commit.commitCommittedOps 349066223 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 38767213 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3555627 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2167826 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 193432320 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.804591 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.360078 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 273049086 # The number of committed instructions +system.cpu.commit.commitCommittedOps 349076811 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 45250302 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2186131 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 136849414 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.550810 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.650371 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83176077 43.00% 43.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 39065690 20.20% 63.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17086597 8.83% 72.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13450710 6.95% 78.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14290443 7.39% 86.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7491330 3.87% 90.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3442946 1.78% 92.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3229105 1.67% 93.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 12199422 6.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 39364225 28.76% 28.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29162916 21.31% 50.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13605145 9.94% 60.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11228015 8.20% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13810148 10.09% 78.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7236976 5.29% 83.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4020101 2.94% 86.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3901622 2.85% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14520266 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 193432320 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273038498 # Number of instructions committed -system.cpu.commit.committedOps 349066223 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 136849414 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273049086 # Number of instructions committed +system.cpu.commit.committedOps 349076811 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024801 # Number of memory references committed -system.cpu.commit.loads 94648980 # Number of loads committed +system.cpu.commit.refs 177029038 # Number of memory references committed +system.cpu.commit.loads 94651098 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30521876 # Number of branches committed +system.cpu.commit.branches 30523993 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279585540 # Number of committed integer instructions. +system.cpu.commit.int_insts 279594011 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 12199422 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14520266 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 569063811 # The number of ROB reads -system.cpu.rob.rob_writes 781450888 # The number of ROB writes -system.cpu.timesIdled 2411 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 109373 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273037886 # Number of Instructions Simulated -system.cpu.committedOps 349065611 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273037886 # Number of Instructions Simulated -system.cpu.cpi 0.730022 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.730022 # CPI: Total CPI of All Threads -system.cpu.ipc 1.369821 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.369821 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1768986911 # number of integer regfile reads -system.cpu.int_regfile_writes 233848403 # number of integer regfile writes -system.cpu.fp_regfile_reads 187568002 # number of floating regfile reads -system.cpu.fp_regfile_writes 132321236 # number of floating regfile writes -system.cpu.misc_regfile_reads 981099777 # number of misc regfile reads -system.cpu.misc_regfile_writes 34422237 # number of misc regfile writes -system.cpu.icache.replacements 14037 # number of replacements -system.cpu.icache.tagsinuse 1859.121830 # Cycle average of tags in use -system.cpu.icache.total_refs 39234784 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15929 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2463.104024 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 516653738 # The number of ROB reads +system.cpu.rob.rob_writes 795243409 # The number of ROB writes +system.cpu.timesIdled 2720 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 116045 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048474 # Number of Instructions Simulated +system.cpu.committedOps 349076199 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048474 # Number of Instructions Simulated +system.cpu.cpi 0.525730 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.525730 # CPI: Total CPI of All Threads +system.cpu.ipc 1.902118 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.902118 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1788157543 # number of integer regfile reads +system.cpu.int_regfile_writes 236964047 # number of integer regfile writes +system.cpu.fp_regfile_reads 189767378 # number of floating regfile reads +system.cpu.fp_regfile_writes 133494852 # number of floating regfile writes +system.cpu.misc_regfile_reads 995239791 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes +system.cpu.icache.replacements 14190 # number of replacements +system.cpu.icache.tagsinuse 1864.933817 # Cycle average of tags in use +system.cpu.icache.total_refs 39934285 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16092 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2481.623478 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1859.121830 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.907774 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.907774 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39234786 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39234786 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39234786 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39234786 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39234786 # number of overall hits -system.cpu.icache.overall_hits::total 39234786 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16841 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16841 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16841 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16841 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16841 # number of overall misses -system.cpu.icache.overall_misses::total 16841 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208423500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208423500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208423500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208423500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208423500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208423500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39251627 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39251627 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39251627 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39251627 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39251627 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39251627 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000429 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000429 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000429 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12375.957485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12375.957485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12375.957485 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1864.933817 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.910612 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.910612 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39934285 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39934285 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39934285 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39934285 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39934285 # number of overall hits +system.cpu.icache.overall_hits::total 39934285 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17014 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17014 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17014 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17014 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17014 # number of overall misses +system.cpu.icache.overall_misses::total 17014 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 211050500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 211050500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 211050500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 211050500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 211050500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,219 +381,219 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 888 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 888 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 888 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 888 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 888 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 888 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15953 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15953 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15953 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15953 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15953 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15953 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137773000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 137773000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137773000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 137773000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137773000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 137773000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8636.181283 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8636.181283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8636.181283 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 900 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 900 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 900 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 900 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 900 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16114 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16114 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16114 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16114 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16114 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1416 # number of replacements -system.cpu.dcache.tagsinuse 3097.112853 # Cycle average of tags in use -system.cpu.dcache.total_refs 173600890 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4598 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37755.739452 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1427 # number of replacements +system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use +system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3097.112853 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.756131 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.756131 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 91544700 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 91544700 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82033348 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82033348 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11669 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11669 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11136 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 173578048 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 173578048 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 173578048 # number of overall hits -system.cpu.dcache.overall_hits::total 173578048 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3368 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3368 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19314 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19314 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.763586 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.763586 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90441052 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90441052 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82033132 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82033132 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 14008 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 14008 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 172474184 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172474184 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172474184 # number of overall hits +system.cpu.dcache.overall_hits::total 172474184 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3598 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3598 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19528 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19528 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 22682 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 22682 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22682 # number of overall misses -system.cpu.dcache.overall_misses::total 22682 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 110168000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 110168000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 637892000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 637892000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 23126 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 23126 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 23126 # number of overall misses +system.cpu.dcache.overall_misses::total 23126 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 115634000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 115634000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 650274000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 650274000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 748060000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 748060000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 748060000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 748060000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 91548068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 91548068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052662 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052662 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11671 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11671 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11136 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11136 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173600730 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173600730 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173600730 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173600730 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000037 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000235 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000171 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32710.213777 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33027.441234 # average WriteReq miss latency +system.cpu.dcache.demand_miss_latency::cpu.data 765908000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 765908000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 765908000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 765908000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90444650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90444650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 14010 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32980.336831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32980.336831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 317500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22678.571429 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks system.cpu.dcache.writebacks::total 1038 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1605 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1605 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16455 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16455 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1792 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1792 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16671 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16671 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 18060 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 18060 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 18060 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 18060 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1763 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2859 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2859 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4622 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4622 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4622 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4622 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53565000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53565000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101664500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101664500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155229500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 155229500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155229500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 155229500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 18463 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 18463 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 18463 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 18463 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2857 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2857 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4663 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 54896500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011618 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.085816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.023491 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.120925 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12854 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 293 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13147 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 380.580872 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2851.587465 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 802.133324 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011614 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.087024 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.024479 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.123117 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12970 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13268 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1038 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1038 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12854 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13165 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12854 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,57 +602,57 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 47 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 47 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 54 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 682000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 682000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88208000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88208000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96743500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133876000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 230619500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96743500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993651 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192605 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922140 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192605 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922140 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.671447 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31295.151089 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31275.647852 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.671447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.193396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.671447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.193396 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index a60b9f94a..dde743a2d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 861cd978d..7e0d618b4 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:59:35 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:16:14 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index cbd6c2617..e11cb6ba0 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu sim_ticks 212344048000 # Number of ticks simulated final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2182036 # Simulator instruction rate (inst/s) -host_op_rate 2789626 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1696989772 # Simulator tick rate (ticks/s) -host_mem_usage 224464 # Number of bytes of host memory used -host_seconds 125.13 # Real time elapsed on the host +host_inst_rate 1971895 # Simulator instruction rate (inst/s) +host_op_rate 2520972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1533561642 # Simulator tick rate (ticks/s) +host_mem_usage 221584 # Number of bytes of host memory used +host_seconds 138.46 # Real time elapsed on the host sim_insts 273037671 # Number of instructions simulated sim_ops 349065408 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1875350709 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 349065408 # Nu system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18102314 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 18087062 # number of instructions that are conditional controls system.cpu.num_int_insts 279584926 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 8414937bc..37b45f338 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index aff2d34a5..0225feba2 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:01:56 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:16:21 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 4bf4fdf3e..7147319f6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525854 # Nu sim_ticks 525854475000 # Number of ticks simulated final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1224247 # Simulator instruction rate (inst/s) -host_op_rate 1565155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2360407719 # Simulator tick rate (ticks/s) -host_mem_usage 233372 # Number of bytes of host memory used -host_seconds 222.78 # Real time elapsed on the host +host_inst_rate 1189484 # Simulator instruction rate (inst/s) +host_op_rate 1520711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2293381880 # Simulator tick rate (ticks/s) +host_mem_usage 230756 # Number of bytes of host memory used +host_seconds 229.29 # Real time elapsed on the host sim_insts 272739291 # Number of instructions simulated sim_ops 348687131 # Number of ops (including micro ops) simulated system.physmem.bytes_read 437312 # Number of bytes read from this memory @@ -71,7 +71,7 @@ system.cpu.committedOps 348687131 # Nu system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18102313 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls system.cpu.num_int_insts 279584925 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index b8945b754..131483c9e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index d16dcf9af..310ad361e 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:22:39 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:18:43 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 736384204000 because target called exit() +Exiting @ tick 735495062500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index a4d9e3173..2ea6fdf18 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.736384 # Number of seconds simulated -sim_ticks 736384204000 # Number of ticks simulated -final_tick 736384204000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.735495 # Number of seconds simulated +sim_ticks 735495062500 # Number of ticks simulated +final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107029 # Simulator instruction rate (inst/s) -host_op_rate 145759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56931535 # Simulator tick rate (ticks/s) -host_mem_usage 233236 # Number of bytes of host memory used -host_seconds 12934.56 # Real time elapsed on the host -sim_insts 1384379033 # Number of instructions simulated -sim_ops 1885333786 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94833536 # Number of bytes read from this memory -system.physmem.bytes_inst_read 209216 # Number of instructions bytes read from this memory +host_inst_rate 126424 # Simulator instruction rate (inst/s) +host_op_rate 172171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67166483 # Simulator tick rate (ticks/s) +host_mem_usage 230552 # Number of bytes of host memory used +host_seconds 10950.33 # Real time elapsed on the host +sim_insts 1384379503 # Number of instructions simulated +sim_ops 1885334256 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 94839680 # Number of bytes read from this memory +system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1481774 # Number of read requests responded to by this memory +system.physmem.num_reads 1481870 # Number of read requests responded to by this memory system.physmem.num_writes 66099 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 128782686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 284113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5744740 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 134527427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 128946726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 290895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5751685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 134698411 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1472768409 # number of cpu cycles simulated +system.cpu.numCycles 1470990126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 522739689 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 397666770 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 35592388 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 329507474 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 283194756 # Number of BTB hits +system.cpu.BPredUnit.lookups 524657246 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 401089358 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 35661760 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 339540356 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 278948773 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59112231 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2837995 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 446610303 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2608281266 # Number of instructions fetch has processed -system.cpu.fetch.Branches 522739689 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 342306987 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 709905843 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 224599686 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 101691904 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 28872 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 415462379 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10233497 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1441668699 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.553094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.169508 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 59722038 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2842670 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 444619593 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2613573524 # Number of instructions fetch has processed +system.cpu.fetch.Branches 524657246 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 338670811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 712273911 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 223851331 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 98512911 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 29657 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 414743940 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11577936 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1438039773 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.556437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.167543 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 731812218 50.76% 50.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 54028478 3.75% 54.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 112774395 7.82% 62.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 69112712 4.79% 67.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 82239849 5.70% 72.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54732676 3.80% 76.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35582945 2.47% 79.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33403067 2.32% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 267982359 18.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 725823899 50.47% 50.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 56807029 3.95% 54.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 112550044 7.83% 62.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 69779758 4.85% 67.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 84813159 5.90% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 53785792 3.74% 76.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34099274 2.37% 79.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30811930 2.14% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 269568888 18.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1441668699 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.354937 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.771006 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 492629108 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 81861101 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 672684141 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11080003 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 183414346 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 82040809 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15532 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3552890515 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32736 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 183414346 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 530589836 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29829797 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3588754 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 644081795 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50164171 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3435316942 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 112 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4205507 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40993124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3332970891 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16270156364 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15618651087 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 651505277 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1339817292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 273156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 268372 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 142469911 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1057917040 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 579962844 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32519670 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 39211966 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3198933227 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 269334 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2725360235 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 26814777 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1313459573 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3048227605 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 58004 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1441668699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.890421 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.914096 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1438039773 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.356669 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.776744 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 492128614 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 78582078 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 673411779 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11338206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 182579096 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 79653725 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 23825 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3539524175 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 54394 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 182579096 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 529782652 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 30198632 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 660985 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 645094382 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49724026 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3431194053 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4188042 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40587721 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1707 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3342681891 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16249059655 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15604311677 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 644747978 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993154351 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1349527540 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 64268 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 59597 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138053548 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1061160981 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 575711799 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 34121400 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 39206197 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3192585936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 69047 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2718019401 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 27726721 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1306902480 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3048220381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45882 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1438039773 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.890086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.916332 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 524357405 36.37% 36.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 197522511 13.70% 50.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 215009168 14.91% 64.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 179008270 12.42% 77.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 156604882 10.86% 88.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 103164450 7.16% 95.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 49203607 3.41% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11056090 0.77% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5742316 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 521512118 36.27% 36.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 198246164 13.79% 50.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216916723 15.08% 65.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 178677193 12.43% 77.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 155355732 10.80% 88.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 100852221 7.01% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48369591 3.36% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10873615 0.76% 99.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7236416 0.50% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1441668699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1438039773 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2118699 2.21% 2.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23832 0.02% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56614089 59.02% 61.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37163288 38.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1743579 1.83% 1.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23896 0.03% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56969230 59.63% 61.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36797024 38.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1266333715 46.46% 46.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11230148 0.41% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876563 0.25% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503497 0.20% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 38 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23211520 0.85% 48.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 900219934 33.03% 81.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 510609530 18.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1258053988 46.29% 46.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11231448 0.41% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876560 0.25% 47.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5503486 0.20% 47.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 73 0.00% 47.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23204970 0.85% 48.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 902246151 33.19% 81.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 509527435 18.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2725360235 # Type of FU issued -system.cpu.iq.rate 1.850502 # Inst issue rate -system.cpu.iq.fu_busy_cnt 95919908 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035195 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6880679936 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4410033557 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2496172626 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 134443918 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 102684223 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 60255652 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2752299483 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 68980660 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 71230775 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2718019401 # Type of FU issued +system.cpu.iq.rate 1.847748 # Inst issue rate +system.cpu.iq.fu_busy_cnt 95533729 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035148 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6864166409 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4398397135 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2490268759 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 133172616 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 101224152 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59789124 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2745104459 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68448671 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 72240187 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 426528171 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 281369 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1323673 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 302965860 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 429772018 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 278201 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1347099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 298714721 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 92 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 183414346 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16249953 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1608700 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3199274316 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7370103 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1057917040 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 579962844 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 258370 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1607775 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 215 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1323673 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 37204877 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8928711 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 46133588 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2624820303 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 845791055 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100539932 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 182579096 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16373982 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1591067 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3192732241 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7809183 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1061160981 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 575711799 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 58058 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1589162 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 317 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1347099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36984086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8972300 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 45956386 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2617990910 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 846641153 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 100028491 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 71755 # number of nop insts executed -system.cpu.iew.exec_refs 1327328363 # number of memory reference insts executed -system.cpu.iew.exec_branches 362158100 # Number of branches executed -system.cpu.iew.exec_stores 481537308 # Number of stores executed -system.cpu.iew.exec_rate 1.782236 # Inst execution rate -system.cpu.iew.wb_sent 2584846968 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2556428278 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1474733618 # num instructions producing a value -system.cpu.iew.wb_consumers 2760579704 # num instructions consuming a value +system.cpu.iew.exec_nop 77258 # number of nop insts executed +system.cpu.iew.exec_refs 1326395495 # number of memory reference insts executed +system.cpu.iew.exec_branches 359930496 # Number of branches executed +system.cpu.iew.exec_stores 479754342 # Number of stores executed +system.cpu.iew.exec_rate 1.779747 # Inst execution rate +system.cpu.iew.wb_sent 2578580051 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2550057883 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1472840060 # num instructions producing a value +system.cpu.iew.wb_consumers 2760220207 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.735798 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534212 # average fanout of values written-back +system.cpu.iew.wb_rate 1.733566 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533595 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1313929852 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 41115032 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1258254355 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.498381 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.211057 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1384390519 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1885345272 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1307387427 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 23165 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 41179561 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1255460679 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.501716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.213055 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 578553729 45.98% 45.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 316892144 25.19% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 101707631 8.08% 79.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79187361 6.29% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 52970249 4.21% 89.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24190672 1.92% 91.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17058373 1.36% 93.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9262849 0.74% 93.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78431347 6.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 576199063 45.90% 45.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 316668907 25.22% 71.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 101245126 8.06% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79298067 6.32% 85.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 52885974 4.21% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24348674 1.94% 91.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17176683 1.37% 93.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9160932 0.73% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78477253 6.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1258254355 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390049 # Number of instructions committed -system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1255460679 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384390519 # Number of instructions committed +system.cpu.commit.committedOps 1885345272 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385853 # Number of memory references committed -system.cpu.commit.loads 631388869 # Number of loads committed +system.cpu.commit.refs 908386041 # Number of memory references committed +system.cpu.commit.loads 631388963 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350232 # Number of branches committed +system.cpu.commit.branches 291350326 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705999 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78431347 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78477253 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4379079317 # The number of ROB reads -system.cpu.rob.rob_writes 6581974646 # The number of ROB writes -system.cpu.timesIdled 1328714 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31099710 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379033 # Number of Instructions Simulated -system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated -system.cpu.cpi 1.063848 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.063848 # CPI: Total CPI of All Threads -system.cpu.ipc 0.939984 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.939984 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12935043618 # number of integer regfile reads -system.cpu.int_regfile_writes 2425775909 # number of integer regfile writes -system.cpu.fp_regfile_reads 71439411 # number of floating regfile reads -system.cpu.fp_regfile_writes 51051626 # number of floating regfile writes -system.cpu.misc_regfile_reads 4084910091 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes -system.cpu.icache.replacements 28501 # number of replacements -system.cpu.icache.tagsinuse 1662.292931 # Cycle average of tags in use -system.cpu.icache.total_refs 415426412 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30198 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13756.752500 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4369697780 # The number of ROB reads +system.cpu.rob.rob_writes 6568059146 # The number of ROB writes +system.cpu.timesIdled 1341236 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32950353 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384379503 # Number of Instructions Simulated +system.cpu.committedOps 1885334256 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384379503 # Number of Instructions Simulated +system.cpu.cpi 1.062563 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.062563 # CPI: Total CPI of All Threads +system.cpu.ipc 0.941121 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.941121 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12914363689 # number of integer regfile reads +system.cpu.int_regfile_writes 2421503464 # number of integer regfile writes +system.cpu.fp_regfile_reads 71102089 # number of floating regfile reads +system.cpu.fp_regfile_writes 50855882 # number of floating regfile writes +system.cpu.misc_regfile_reads 4088825153 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776464 # number of misc regfile writes +system.cpu.icache.replacements 29072 # number of replacements +system.cpu.icache.tagsinuse 1666.420003 # Cycle average of tags in use +system.cpu.icache.total_refs 414707358 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30775 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13475.462486 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1662.292931 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.811666 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.811666 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 415426419 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 415426419 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 415426419 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 415426419 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 415426419 # number of overall hits -system.cpu.icache.overall_hits::total 415426419 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35960 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35960 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35960 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35960 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35960 # number of overall misses -system.cpu.icache.overall_misses::total 35960 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 314726500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 314726500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 314726500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 314726500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 314726500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 314726500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 415462379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 415462379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 415462379 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 415462379 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 415462379 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 415462379 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8752.127364 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8752.127364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8752.127364 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1666.420003 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.813682 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.813682 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 414707364 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 414707364 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 414707364 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 414707364 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 414707364 # number of overall hits +system.cpu.icache.overall_hits::total 414707364 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 36576 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36576 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36576 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36576 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36576 # number of overall misses +system.cpu.icache.overall_misses::total 36576 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 322136500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 322136500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 322136500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 322136500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 322136500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 322136500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 414743940 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 414743940 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 414743940 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 414743940 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,237 +382,221 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 780 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 780 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 780 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 780 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 780 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 780 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35180 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 35180 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 35180 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 35180 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 35180 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 35180 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 188682500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 188682500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 188682500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 188682500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 188682500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 188682500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5363.345651 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5363.345651 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5363.345651 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 853 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 853 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 853 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35723 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 35723 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 35723 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 35723 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 35723 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 35723 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192601000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 192601000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192601000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 192601000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532334 # number of replacements -system.cpu.dcache.tagsinuse 4094.808393 # Cycle average of tags in use -system.cpu.dcache.total_refs 1033081236 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536430 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 672.390695 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 312649000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.808393 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999709 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999709 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 756924525 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 756924525 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276114347 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276114347 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 12957 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 12957 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11669 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11669 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1033038872 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1033038872 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1033038872 # number of overall hits -system.cpu.dcache.overall_hits::total 1033038872 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2432909 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2432909 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 821331 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 821331 # number of WriteReq misses +system.cpu.dcache.replacements 1532415 # number of replacements +system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use +system.cpu.dcache.total_refs 1032974400 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1536511 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 672.285717 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 290267000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.914319 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999735 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999735 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 756817928 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 756817928 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276114576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276114576 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13150 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13150 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11766 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11766 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1032932504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1032932504 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1032932504 # number of overall hits +system.cpu.dcache.overall_hits::total 1032932504 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2368566 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2368566 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 821102 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 821102 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3254240 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3254240 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3254240 # number of overall misses -system.cpu.dcache.overall_misses::total 3254240 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 81657017500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81657017500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28588903000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28588903000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 108000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 108000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 16500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 16500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 110245920500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 110245920500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 110245920500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 110245920500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 759357434 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 759357434 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3189668 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3189668 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3189668 # number of overall misses +system.cpu.dcache.overall_misses::total 3189668 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80139479500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80139479500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28569168500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28569168500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 114500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 114500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 108708648000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 108708648000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 108708648000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 108708648000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 759186494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 759186494 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12960 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12960 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11672 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11672 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1036293112 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1036293112 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1036293112 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1036293112 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003204 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002966 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000231 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000257 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003140 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003140 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33563.531353 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34808.016500 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36000 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 5500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33877.624422 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33877.624422 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13153 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13153 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11766 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11766 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1036122172 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1036122172 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 80000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 106562 # number of writebacks -system.cpu.dcache.writebacks::total 106562 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 969189 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 969189 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743643 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743643 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 106560 # number of writebacks +system.cpu.dcache.writebacks::total 106560 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904767 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 904767 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743443 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743443 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1712832 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1712832 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1712832 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1712832 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463720 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1463720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77688 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77688 # number of WriteReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541408 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541408 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541408 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541408 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029308500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029308500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2504136000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2504136000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 7500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 7500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52533444500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52533444500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52533444500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52533444500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1648210 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1648210 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1648210 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1648210 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463799 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1463799 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77659 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 77659 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541458 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541458 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029877000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029877000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502958500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502958500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52532835500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000281 # mshr miss rate for WriteReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000257 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34179.562006 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32233.240655 # average WriteReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 2500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34081.466101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34081.466101 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480213 # number of replacements -system.cpu.l2cache.tagsinuse 31972.758917 # Cycle average of tags in use -system.cpu.l2cache.total_refs 86473 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512931 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.057156 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480284 # number of replacements +system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use +system.cpu.l2cache.total_refs 87070 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.057548 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 2964.503438 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 60.794216 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28947.461262 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.090469 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001855 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.883406 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.975731 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26928 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048525000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103877000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931558500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46035435500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103877000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.907990 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 9ae0bbe5f..0e51a5093 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 31662be21..a30e96fb9 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:09:56 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:20:21 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 5256776b5..97c60e977 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu sim_ticks 945613131000 # Number of ticks simulated final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2461578 # Simulator instruction rate (inst/s) -host_op_rate 3352328 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1681400523 # Simulator tick rate (ticks/s) -host_mem_usage 221408 # Number of bytes of host memory used -host_seconds 562.40 # Real time elapsed on the host +host_inst_rate 2176707 # Simulator instruction rate (inst/s) +host_op_rate 2964374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1486817392 # Simulator tick rate (ticks/s) +host_mem_usage 218836 # Number of bytes of host memory used +host_seconds 636.00 # Real time elapsed on the host sim_insts 1384381614 # Number of instructions simulated sim_ops 1885336367 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8025491315 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1885336367 # Nu system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223764558 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698876 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 4f1c04844..91ae9c597 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 608f1b673..d0e2e4ad0 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:19:22 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:31:08 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 17c70c66c..cae7de027 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.369902 # Nu sim_ticks 2369901960000 # Number of ticks simulated final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1323415 # Simulator instruction rate (inst/s) -host_op_rate 1795307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2270088736 # Simulator tick rate (ticks/s) -host_mem_usage 230320 # Number of bytes of host memory used -host_seconds 1043.97 # Real time elapsed on the host +host_inst_rate 1363943 # Simulator instruction rate (inst/s) +host_op_rate 1850286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2339607262 # Simulator tick rate (ticks/s) +host_mem_usage 227748 # Number of bytes of host memory used +host_seconds 1012.95 # Real time elapsed on the host sim_insts 1381604347 # Number of instructions simulated sim_ops 1874244950 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94696320 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1874244950 # Nu system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223764558 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698876 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 466d8993c..f2b092df6 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index bc6c11a64..82550ab1e 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:25:21 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:35:27 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 30755543500 because target called exit() +Exiting @ tick 24560764000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 324eff178..aa06eed4d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030756 # Number of seconds simulated -sim_ticks 30755543500 # Number of ticks simulated -final_tick 30755543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024561 # Number of seconds simulated +sim_ticks 24560764000 # Number of ticks simulated +final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147147 # Simulator instruction rate (inst/s) -host_op_rate 208812 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63815156 # Simulator tick rate (ticks/s) -host_mem_usage 235936 # Number of bytes of host memory used -host_seconds 481.95 # Real time elapsed on the host -sim_insts 70917252 # Number of instructions simulated -sim_ops 100636500 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8681216 # Number of bytes read from this memory -system.physmem.bytes_inst_read 364288 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5661440 # Number of bytes written to this memory -system.physmem.num_reads 135644 # Number of read requests responded to by this memory -system.physmem.num_writes 88460 # Number of write requests responded to by this memory +host_inst_rate 175313 # Simulator instruction rate (inst/s) +host_op_rate 248779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60713797 # Simulator tick rate (ticks/s) +host_mem_usage 233096 # Number of bytes of host memory used +host_seconds 404.53 # Real time elapsed on the host +sim_insts 70920072 # Number of instructions simulated +sim_ops 100639320 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 8687232 # Number of bytes read from this memory +system.physmem.bytes_inst_read 367552 # Number of instructions bytes read from this memory +system.physmem.bytes_written 5661632 # Number of bytes written to this memory +system.physmem.num_reads 135738 # Number of read requests responded to by this memory +system.physmem.num_writes 88463 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 282265082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 11844629 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 184078685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 466343767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 353703655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 14965007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 230515305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 584218960 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 61511088 # number of cpu cycles simulated +system.cpu.numCycles 49121529 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17165899 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13150342 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 741670 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12130394 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8128680 # Number of BTB hits +system.cpu.BPredUnit.lookups 17484643 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 13346532 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 763895 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12042742 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8272877 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1854457 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 183977 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13000354 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87655737 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17165899 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9983137 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21873848 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2772277 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 23278441 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2074 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12226708 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 230090 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 60107424 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.046912 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.144766 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1873235 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 186435 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13233353 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 89314081 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17484643 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10146112 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22235900 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3054378 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 9993886 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 494 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12432222 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 242141 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47666513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.625620 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.342151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 38251797 63.64% 63.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2252747 3.75% 67.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1977441 3.29% 70.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2053713 3.42% 74.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1587290 2.64% 76.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1440263 2.40% 79.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 985496 1.64% 80.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1267048 2.11% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10291629 17.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25452916 53.40% 53.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2276272 4.78% 58.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2010669 4.22% 62.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2082167 4.37% 66.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1606372 3.37% 70.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1473384 3.09% 73.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1003270 2.10% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1293693 2.71% 78.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10467770 21.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 60107424 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.279070 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.425040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14856562 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 22001240 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20371729 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1846089 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3466450 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109251 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119897530 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 366577 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1846089 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16668221 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1965297 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15638738 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19567499 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4421580 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116607925 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4528 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3022237 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 40 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 116831766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536941360 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536932869 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8491 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99148069 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17683697 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 794887 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 794929 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12663863 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29905745 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22497839 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2550433 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3605599 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111646205 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 783462 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107783359 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 315194 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11596172 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28526322 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 79963 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 60107424 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.793179 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.923398 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47666513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.355947 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.818227 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15402794 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8395926 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20419082 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1357324 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2091387 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3552582 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 114889 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 122010152 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 381349 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2091387 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17235553 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2381046 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 774700 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19895179 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5288648 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 118965286 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 65 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 10051 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4471697 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 173 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 119289544 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 547314245 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 547305502 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8743 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99152581 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 20136963 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 50089 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 50062 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12897670 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30342934 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22764283 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3373932 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4070444 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 114201865 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 59946 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108885427 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 355885 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13447173 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32642565 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23673 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47666513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.284317 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.003120 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21602316 35.94% 35.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11403464 18.97% 54.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8200759 13.64% 68.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7319332 12.18% 80.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4922118 8.19% 88.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3558954 5.92% 94.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1700735 2.83% 97.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 865239 1.44% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 534507 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11902735 24.97% 24.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8314690 17.44% 42.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7496951 15.73% 58.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7072171 14.84% 72.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5553695 11.65% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3902484 8.19% 92.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1926147 4.04% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 904880 1.90% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 592760 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 60107424 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47666513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 107169 4.01% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1504678 56.36% 60.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1057992 39.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112261 4.35% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1423319 55.12% 59.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1046695 40.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56937666 52.83% 52.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 88934 0.08% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 306 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29100662 27.00% 79.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21655782 20.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57627292 52.92% 52.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 88925 0.08% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 277 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29380371 26.98% 79.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21788555 20.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107783359 # Type of FU issued -system.cpu.iq.rate 1.752259 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2669841 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024770 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 278658374 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124040880 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105647232 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 803 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1299 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 239 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110452800 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 400 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1897681 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108885427 # Type of FU issued +system.cpu.iq.rate 2.216654 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2582277 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023716 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 268374678 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127734912 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106613834 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 851 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 211 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 111467277 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 427 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2219770 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2596713 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5092 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1940178 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3033338 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8348 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28761 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2206058 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 48 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1846089 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 949061 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28680 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112509386 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 471926 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29905745 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22497839 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 767420 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1122 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1174 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17660 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 518600 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 257124 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 775724 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106553535 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28745908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1229824 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2091387 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 991755 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 31052 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 114342127 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 442332 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30342934 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22764283 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 43712 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1891 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1967 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28761 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 532244 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 266639 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 798883 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107583415 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28980389 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1302012 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 79719 # number of nop insts executed -system.cpu.iew.exec_refs 50100729 # number of memory reference insts executed -system.cpu.iew.exec_branches 14610772 # Number of branches executed -system.cpu.iew.exec_stores 21354821 # Number of stores executed -system.cpu.iew.exec_rate 1.732265 # Inst execution rate -system.cpu.iew.wb_sent 105985847 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105647471 # cumulative count of insts written-back -system.cpu.iew.wb_producers 52628676 # num instructions producing a value -system.cpu.iew.wb_consumers 101773898 # num instructions consuming a value +system.cpu.iew.exec_nop 80316 # number of nop insts executed +system.cpu.iew.exec_refs 50461236 # number of memory reference insts executed +system.cpu.iew.exec_branches 14752818 # Number of branches executed +system.cpu.iew.exec_stores 21480847 # Number of stores executed +system.cpu.iew.exec_rate 2.190148 # Inst execution rate +system.cpu.iew.wb_sent 106971474 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106614045 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53628736 # num instructions producing a value +system.cpu.iew.wb_consumers 104822222 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.717535 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.517114 # average fanout of values written-back +system.cpu.iew.wb_rate 2.170414 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70922804 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100642052 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11867683 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 703499 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 697454 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 58261336 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.727424 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.444675 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70925624 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100644872 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 13697900 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 36273 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 715054 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45575127 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.208329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.734720 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25494739 43.76% 43.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14514509 24.91% 68.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4165612 7.15% 75.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3613399 6.20% 82.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2299623 3.95% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1924742 3.30% 89.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 677832 1.16% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 500112 0.86% 91.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5070768 8.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16228357 35.61% 35.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11797211 25.89% 61.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3508330 7.70% 69.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2972714 6.52% 75.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1972056 4.33% 80.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1932722 4.24% 84.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 698627 1.53% 85.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 551617 1.21% 87.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5913493 12.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 58261336 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70922804 # Number of instructions committed -system.cpu.commit.committedOps 100642052 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45575127 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70925624 # Number of instructions committed +system.cpu.commit.committedOps 100644872 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47866693 # Number of memory references committed -system.cpu.commit.loads 27309032 # Number of loads committed +system.cpu.commit.refs 47867821 # Number of memory references committed +system.cpu.commit.loads 27309596 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13670551 # Number of branches committed +system.cpu.commit.branches 13671115 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91480479 # Number of committed integer instructions. +system.cpu.commit.int_insts 91482735 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5070768 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5913493 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 165675004 # The number of ROB reads -system.cpu.rob.rob_writes 226873042 # The number of ROB writes -system.cpu.timesIdled 61564 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1403664 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70917252 # Number of Instructions Simulated -system.cpu.committedOps 100636500 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70917252 # Number of Instructions Simulated -system.cpu.cpi 0.867364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.867364 # CPI: Total CPI of All Threads -system.cpu.ipc 1.152918 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.152918 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 512909735 # number of integer regfile reads -system.cpu.int_regfile_writes 103521788 # number of integer regfile writes -system.cpu.fp_regfile_reads 1198 # number of floating regfile reads -system.cpu.fp_regfile_writes 998 # number of floating regfile writes -system.cpu.misc_regfile_reads 145684870 # number of misc regfile reads -system.cpu.misc_regfile_writes 35686 # number of misc regfile writes -system.cpu.icache.replacements 28916 # number of replacements -system.cpu.icache.tagsinuse 1823.894979 # Cycle average of tags in use -system.cpu.icache.total_refs 12194402 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30952 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 393.977837 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 153979107 # The number of ROB reads +system.cpu.rob.rob_writes 230788170 # The number of ROB writes +system.cpu.timesIdled 64143 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1455016 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70920072 # Number of Instructions Simulated +system.cpu.committedOps 100639320 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70920072 # Number of Instructions Simulated +system.cpu.cpi 0.692632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.692632 # CPI: Total CPI of All Threads +system.cpu.ipc 1.443768 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.443768 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 517371049 # number of integer regfile reads +system.cpu.int_regfile_writes 104514948 # number of integer regfile writes +system.cpu.fp_regfile_reads 1051 # number of floating regfile reads +system.cpu.fp_regfile_writes 886 # number of floating regfile writes +system.cpu.misc_regfile_reads 147913903 # number of misc regfile reads +system.cpu.misc_regfile_writes 36814 # number of misc regfile writes +system.cpu.icache.replacements 31518 # number of replacements +system.cpu.icache.tagsinuse 1822.469235 # Cycle average of tags in use +system.cpu.icache.total_refs 12397113 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 33561 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 369.390453 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1823.894979 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.890574 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.890574 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12194406 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12194406 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12194406 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12194406 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12194406 # number of overall hits -system.cpu.icache.overall_hits::total 12194406 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 32302 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 32302 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 32302 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 32302 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 32302 # number of overall misses -system.cpu.icache.overall_misses::total 32302 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 385546000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 385546000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 385546000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 385546000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 385546000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 385546000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12226708 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12226708 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12226708 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12226708 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12226708 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12226708 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002642 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002642 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002642 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11935.669618 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1822.469235 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.889878 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.889878 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12397114 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12397114 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12397114 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12397114 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12397114 # number of overall hits +system.cpu.icache.overall_hits::total 12397114 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35108 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35108 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35108 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35108 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35108 # number of overall misses +system.cpu.icache.overall_misses::total 35108 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 406151000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 406151000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 406151000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 406151000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 406151000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,224 +382,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1300 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1300 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1300 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1300 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1300 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1300 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31002 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31002 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31002 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31002 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31002 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31002 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 260426000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 260426000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 260426000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 260426000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 260426000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 260426000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8400.296755 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8400.296755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8400.296755 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1474 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1474 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1474 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1474 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1474 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33634 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 33634 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 33634 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 33634 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 33634 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158739 # number of replacements -system.cpu.dcache.tagsinuse 4072.206882 # Cycle average of tags in use -system.cpu.dcache.total_refs 44824724 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162835 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 275.276961 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 306509000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.206882 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994191 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994191 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26477714 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26477714 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18310173 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18310173 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18862 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18862 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 17842 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 17842 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44787887 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44787887 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44787887 # number of overall hits -system.cpu.dcache.overall_hits::total 44787887 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 109145 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 109145 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1539728 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1539728 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 32 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 32 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1648873 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1648873 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1648873 # number of overall misses -system.cpu.dcache.overall_misses::total 1648873 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2419748500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2419748500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 52564184000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52564184000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 414000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 414000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54983932500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54983932500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54983932500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54983932500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26586859 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26586859 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 158907 # number of replacements +system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use +system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.993836 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.993836 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26393302 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26393302 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18309799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18309799 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 19644 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 19644 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 18406 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 18406 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44703101 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44703101 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44703101 # number of overall hits +system.cpu.dcache.overall_hits::total 44703101 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 110193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 110193 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1540102 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1540102 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1650295 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1650295 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1650295 # number of overall misses +system.cpu.dcache.overall_misses::total 1650295 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2434975500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2434975500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52525381000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52525381000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 425000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 425000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54960356500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54960356500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54960356500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54960356500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26503495 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26503495 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18894 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 18894 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 17842 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 17842 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46436760 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46436760 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46436760 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46436760 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004105 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077569 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001694 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035508 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035508 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22170.035274 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34138.616691 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12937.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33346.372037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33346.372037 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19679 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19900 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123771 # number of writebacks -system.cpu.dcache.writebacks::total 123771 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432805 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1432805 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 32 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1485988 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1485988 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1485988 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1485988 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55962 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55962 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106923 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106923 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162885 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162885 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162885 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162885 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1045315000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1045315000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3667070000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3667070000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4712385000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4712385000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4712385000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4712385000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005387 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003508 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003508 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18679.014331 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.362803 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28930.748688 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28930.748688 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 123795 # number of writebacks +system.cpu.dcache.writebacks::total 123795 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54073 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 54073 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1433145 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1433145 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1487218 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1487218 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1487218 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1487218 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56120 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 56120 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106957 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106957 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 163077 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 163077 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 163077 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 163077 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1049489500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115379 # number of replacements -system.cpu.l2cache.tagsinuse 18377.888131 # Cycle average of tags in use -system.cpu.l2cache.total_refs 75936 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 134247 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.565644 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 115487 # number of replacements +system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use +system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15924.740551 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 876.929097 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1576.218483 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.485985 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.026762 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.048102 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.560849 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 25235 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 28501 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 53736 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 123771 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 123771 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 880.199051 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1614.762848 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.483750 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.026862 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.049279 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.559891 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27786 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 28611 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129995 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 135738 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178439000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 852007500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1030446500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1955000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1955000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3195019500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3195019500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4225466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index fc20c8ede..141b1144a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index 1d79bb34d..fe99a5f18 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:26:23 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:42:22 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 34e49ce66..3df28546e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932162000 # Number of ticks simulated final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2398112 # Simulator instruction rate (inst/s) -host_op_rate 3403143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1823852749 # Simulator tick rate (ticks/s) -host_mem_usage 223920 # Number of bytes of host memory used -host_seconds 29.57 # Real time elapsed on the host +host_inst_rate 2274185 # Simulator instruction rate (inst/s) +host_op_rate 3227279 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1729602132 # Simulator tick rate (ticks/s) +host_mem_usage 221076 # Number of bytes of host memory used +host_seconds 31.18 # Real time elapsed on the host sim_insts 70913189 # Number of instructions simulated sim_ops 100632437 # Number of ops (including micro ops) simulated system.physmem.bytes_read 419153654 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 100632437 # Nu system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10735849 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls system.cpu.num_int_insts 91472788 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 69f507d60..ddcce578b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index 3a0d84b6b..e1c016ba1 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:27:02 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:43:04 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 37dcac738..a19c3fe41 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133117 # Nu sim_ticks 133117442000 # Number of ticks simulated final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1310173 # Simulator instruction rate (inst/s) -host_op_rate 1857860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2478297620 # Simulator tick rate (ticks/s) -host_mem_usage 232836 # Number of bytes of host memory used -host_seconds 53.71 # Real time elapsed on the host +host_inst_rate 1304890 # Simulator instruction rate (inst/s) +host_op_rate 1850368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2468304183 # Simulator tick rate (ticks/s) +host_mem_usage 230248 # Number of bytes of host memory used +host_seconds 53.93 # Real time elapsed on the host sim_insts 70373636 # Number of instructions simulated sim_ops 99791663 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8570688 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 99791663 # Nu system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10735849 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls system.cpu.num_int_insts 91472788 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index cdbe03d5f..be1f1b29f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index d23947013..e85e89203 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:27:07 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:44:10 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 464094642500 because target called exit() +Exiting @ tick 463993693500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index b46ca3b4f..45a43d0ac 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.464095 # Number of seconds simulated -sim_ticks 464094642500 # Number of ticks simulated -final_tick 464094642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.463994 # Number of seconds simulated +sim_ticks 463993693500 # Number of ticks simulated +final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178110 # Simulator instruction rate (inst/s) -host_op_rate 198694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53516537 # Simulator tick rate (ticks/s) -host_mem_usage 227392 # Number of bytes of host memory used -host_seconds 8671.99 # Real time elapsed on the host -sim_insts 1544563041 # Number of instructions simulated -sim_ops 1723073854 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 189817088 # Number of bytes read from this memory -system.physmem.bytes_inst_read 48640 # Number of instructions bytes read from this memory -system.physmem.bytes_written 78237376 # Number of bytes written to this memory -system.physmem.num_reads 2965892 # Number of read requests responded to by this memory -system.physmem.num_writes 1222459 # Number of write requests responded to by this memory +host_inst_rate 212934 # Simulator instruction rate (inst/s) +host_op_rate 237543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63966219 # Simulator tick rate (ticks/s) +host_mem_usage 224764 # Number of bytes of host memory used +host_seconds 7253.73 # Real time elapsed on the host +sim_insts 1544563066 # Number of instructions simulated +sim_ops 1723073879 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 189795648 # Number of bytes read from this memory +system.physmem.bytes_inst_read 49344 # Number of instructions bytes read from this memory +system.physmem.bytes_written 78222144 # Number of bytes written to this memory +system.physmem.num_reads 2965557 # Number of read requests responded to by this memory +system.physmem.num_writes 1222221 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 409005127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 104806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 168580649 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 577585776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 409047904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 106346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 168584498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 577632403 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,107 +64,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 928189286 # number of cpu cycles simulated +system.cpu.numCycles 927987388 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 300558884 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 246363041 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16110008 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 171748174 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156362542 # Number of BTB hits +system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18325675 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 390 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 292832773 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2158671516 # Number of instructions fetch has processed -system.cpu.fetch.Branches 300558884 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174688217 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 429285540 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83802150 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 129138530 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 283809493 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5370008 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 918527985 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.613925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.238783 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed +system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 489242491 53.26% 53.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23031671 2.51% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38788083 4.22% 59.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47826065 5.21% 65.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40763412 4.44% 69.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46954546 5.11% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39099426 4.26% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18124481 1.97% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174697810 19.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 918527985 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323812 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325680 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322137890 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 109173401 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403303983 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16642613 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 67270098 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46182318 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 747 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2347171741 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2550 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 67270098 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343773810 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50758192 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21988 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397138305 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 59565592 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2290275122 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23158 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4666704 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 46265569 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2264842596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10571584644 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10571581459 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3185 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319959 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 558522637 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5679 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5674 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136915079 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624891325 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218844969 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86018221 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66187056 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2190772661 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1712 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016120341 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4885308 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 463006686 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1075673735 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1208 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 918527985 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.194947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.923224 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 251260735 27.35% 27.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 138867546 15.12% 42.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158222967 17.23% 59.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116427032 12.68% 72.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125736326 13.69% 86.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75508875 8.22% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39162431 4.26% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10675084 1.16% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2666989 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 251194344 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 918527985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 822239 3.28% 3.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4824 0.02% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 824240 3.28% 3.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available @@ -192,13 +192,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19001190 75.81% 79.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5234373 20.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234297815 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 931066 0.05% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued @@ -220,160 +220,160 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 50 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587044073 29.12% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193847304 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016120341 # Type of FU issued -system.cpu.iq.rate 2.172100 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25062626 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4980716257 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2653967070 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958162011 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 344 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041182792 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 175 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63608263 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued +system.cpu.iq.rate 2.172504 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138964553 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 284704 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189296 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43997922 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451252 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 67270098 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23165985 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1316827 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2190782552 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5581738 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624891325 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218844969 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1648 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 207697 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 50017 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189296 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8647984 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10198062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18846046 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986617242 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 572452659 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29503099 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 67239337 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5585867 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218742392 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 626 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189336 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8626288 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10208500 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18834788 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 572477440 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29472204 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8179 # number of nop insts executed -system.cpu.iew.exec_refs 763318356 # number of memory reference insts executed -system.cpu.iew.exec_branches 238198091 # Number of branches executed -system.cpu.iew.exec_stores 190865697 # Number of stores executed -system.cpu.iew.exec_rate 2.140315 # Inst execution rate -system.cpu.iew.wb_sent 1967150761 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958162143 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296167059 # num instructions producing a value -system.cpu.iew.wb_consumers 2068734310 # num instructions consuming a value +system.cpu.iew.exec_nop 8125 # number of nop insts executed +system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed +system.cpu.iew.exec_branches 238194699 # Number of branches executed +system.cpu.iew.exec_stores 190834919 # Number of stores executed +system.cpu.iew.exec_rate 2.140744 # Inst execution rate +system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296093484 # num instructions producing a value +system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.109658 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626551 # average fanout of values written-back +system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563059 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073872 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 467775476 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 504 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16109498 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 851257888 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.024150 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756084 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073897 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 467569115 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 177 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.024270 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 363004636 42.64% 42.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192697561 22.64% 65.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73553862 8.64% 73.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35091204 4.12% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18733793 2.20% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30684966 3.60% 83.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19668934 2.31% 86.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10962087 1.29% 87.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106860845 12.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 851257888 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563059 # Number of instructions committed -system.cpu.commit.committedOps 1723073872 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563084 # Number of instructions committed +system.cpu.commit.committedOps 1723073897 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773819 # Number of memory references committed -system.cpu.commit.loads 485926772 # Number of loads committed +system.cpu.commit.refs 660773829 # Number of memory references committed +system.cpu.commit.loads 485926777 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462366 # Number of branches committed +system.cpu.commit.branches 213462371 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941877 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106860845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2935245792 # The number of ROB reads -system.cpu.rob.rob_writes 4449143808 # The number of ROB writes -system.cpu.timesIdled 899784 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9661301 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563041 # Number of Instructions Simulated -system.cpu.committedOps 1723073854 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563041 # Number of Instructions Simulated -system.cpu.cpi 0.600940 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600940 # CPI: Total CPI of All Threads -system.cpu.ipc 1.664060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.664060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9952061686 # number of integer regfile reads -system.cpu.int_regfile_writes 1938314522 # number of integer regfile writes -system.cpu.fp_regfile_reads 132 # number of floating regfile reads -system.cpu.fp_regfile_writes 135 # number of floating regfile writes -system.cpu.misc_regfile_reads 2898335768 # number of misc regfile reads -system.cpu.misc_regfile_writes 128 # number of misc regfile writes -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 636.409684 # Cycle average of tags in use -system.cpu.icache.total_refs 283808312 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 793 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 357891.944515 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2934966123 # The number of ROB reads +system.cpu.rob.rob_writes 4448699546 # The number of ROB writes +system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563066 # Number of Instructions Simulated +system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated +system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads +system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads +system.cpu.int_regfile_writes 1938266429 # number of integer regfile writes +system.cpu.fp_regfile_reads 186 # number of floating regfile reads +system.cpu.fp_regfile_writes 205 # number of floating regfile writes +system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads +system.cpu.misc_regfile_writes 138 # number of misc regfile writes +system.cpu.icache.replacements 28 # number of replacements +system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use +system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 636.409684 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310747 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310747 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 283808312 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 283808312 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 283808312 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 283808312 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 283808312 # number of overall hits -system.cpu.icache.overall_hits::total 283808312 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses -system.cpu.icache.overall_misses::total 1181 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39284000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39284000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39284000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39284000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39284000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39284000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 283809493 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 283809493 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 283809493 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 283809493 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 283809493 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 283809493 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 283729068 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 283729068 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 283729068 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits +system.cpu.icache.overall_hits::total 283729068 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1197 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1197 # number of overall misses +system.cpu.icache.overall_misses::total 1197 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39840000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39840000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39840000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39840000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33263.336156 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,269 +382,269 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 388 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 388 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27229500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27229500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27229500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27229500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # 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number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34337.326608 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34337.326608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34337.326608 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9619385 # number of replacements -system.cpu.dcache.tagsinuse 4087.714803 # Cycle average of tags in use -system.cpu.dcache.total_refs 660788859 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9623481 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.664224 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3348066000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.714803 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 493410063 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 493410063 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167378645 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167378645 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 88 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 88 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 63 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 63 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660788708 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660788708 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660788708 # number of overall hits -system.cpu.dcache.overall_hits::total 660788708 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10697227 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10697227 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5207402 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5207402 # number of WriteReq misses +system.cpu.dcache.replacements 9619302 # number of replacements +system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use +system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997987 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997987 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 493348220 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 493348220 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167378287 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167378287 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 68 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 68 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660726507 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660726507 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660726507 # number of overall hits +system.cpu.dcache.overall_hits::total 660726507 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10693817 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10693817 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5207760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5207760 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15904629 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15904629 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15904629 # number of overall misses -system.cpu.dcache.overall_misses::total 15904629 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 189148262000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 189148262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129349741794 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129349741794 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 15901577 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15901577 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15901577 # number of overall misses +system.cpu.dcache.overall_misses::total 15901577 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 189065481500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 189065481500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129319032251 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129319032251 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318498003794 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318498003794 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318498003794 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318498003794 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 504107290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 504107290 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 318384513751 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318384513751 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318384513751 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318384513751 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 504042037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 504042037 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 91 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 91 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 63 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 63 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 676693337 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 676693337 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 676693337 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 676693337 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021220 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030173 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032967 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.990108 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24839.592141 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 271743722 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 161500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91838 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2958.946427 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20187.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3133740 # number of writebacks -system.cpu.dcache.writebacks::total 3133740 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2967640 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2967640 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313508 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3313508 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3133684 # number of writebacks +system.cpu.dcache.writebacks::total 3133684 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2964371 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2964371 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313808 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3313808 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6281148 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6281148 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6281148 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6281148 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729587 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7729587 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893894 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893894 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9623481 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9623481 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9623481 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9623481 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93074627500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 93074627500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45380366039 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 45380366039 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138454993539 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138454993539 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138454993539 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138454993539 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015333 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 6278179 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6278179 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6278179 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6278179 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729446 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7729446 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893952 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893952 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9623398 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9623398 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9623398 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9623398 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93061119500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12041.345482 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23961.407576 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14387.204956 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14387.204956 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2953454 # number of replacements -system.cpu.l2cache.tagsinuse 26874.371014 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7878176 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2980778 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.642993 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 100977467500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10760.004135 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 11.346810 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16103.020070 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.328369 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000346 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.491425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.820141 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2953110 # number of replacements +system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7878336 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2980430 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.643355 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 100989511500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 10758.137226 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 11.396468 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16105.809458 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.328312 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000348 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.491510 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.820170 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5680110 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5680139 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3133740 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3133740 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 978232 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 978232 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5680299 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5680328 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3133684 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3133684 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 978305 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 978305 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 6658342 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6658371 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 6658604 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102120924500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102147132500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 793 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7729587 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7730380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3133740 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3133740 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893894 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893894 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 793 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9623481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9624274 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 793 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9623481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9624274 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963430 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483481 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963430 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.308115 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963430 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.308115 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.664921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34327.991727 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34692.381031 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.664921 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.518471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.664921 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.518471 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 58178500 # number of cycles access was blocked +system.cpu.l2cache.overall_hits::cpu.data 6658604 # number of overall hits +system.cpu.l2cache.overall_hits::total 6658633 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 772 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70370492000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31764549000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 31764549000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26523500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102108517500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102135041000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26523500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102108517500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102135041000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7729444 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7730245 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3133684 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3133684 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893954 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893954 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9623398 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9624199 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9623398 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 6799 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8556.920135 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8512.175204 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1222459 # number of writebacks -system.cpu.l2cache.writebacks::total 1222459 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 760 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049470 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2050230 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915662 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 915662 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 760 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2965132 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2965892 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 760 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2965132 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2965892 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63915816500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63939496500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922990000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922990000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92838806500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 92862486500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92838806500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 92862486500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265146 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483481 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.894737 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.509927 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.972049 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1222221 # number of writebacks +system.cpu.l2cache.writebacks::total 1222221 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 771 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049137 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2049908 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915649 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 915649 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 771 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2964786 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2965557 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 771 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2964786 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2965557 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24050500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63906561000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63930611500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28918183500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28918183500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24050500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92824744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 92848795000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24050500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 9508b6eff..2b19687c3 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 1bac004a3..d2789ef63 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:28:58 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:48:11 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index bd3b0790d..a81ef68d7 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538205000 # Number of ticks simulated final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3009474 # Simulator instruction rate (inst/s) -host_op_rate 3357290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1678647401 # Simulator tick rate (ticks/s) -host_mem_usage 216676 # Number of bytes of host memory used -host_seconds 513.23 # Real time elapsed on the host +host_inst_rate 2870592 # Simulator instruction rate (inst/s) +host_op_rate 3202357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1601180723 # Simulator tick rate (ticks/s) +host_mem_usage 213836 # Number of bytes of host memory used +host_seconds 538.06 # Real time elapsed on the host sim_insts 1544563049 # Number of instructions simulated sim_ops 1723073862 # Number of ops (including micro ops) simulated system.physmem.bytes_read 7759650064 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1723073862 # Nu system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498450 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index ce3f8d9d1..a5aadfde9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 424d2bbd8..cbd722a94 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:33:49 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:53:56 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 515a2d834..ce1a1d893 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.431420 # Nu sim_ticks 2431419954000 # Number of ticks simulated final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1665877 # Simulator instruction rate (inst/s) -host_op_rate 1859134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2632279795 # Simulator tick rate (ticks/s) -host_mem_usage 225588 # Number of bytes of host memory used -host_seconds 923.69 # Real time elapsed on the host +host_inst_rate 1812626 # Simulator instruction rate (inst/s) +host_op_rate 2022908 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2864161367 # Simulator tick rate (ticks/s) +host_mem_usage 223004 # Number of bytes of host memory used +host_seconds 848.91 # Real time elapsed on the host sim_insts 1538759609 # Number of instructions simulated sim_ops 1717270343 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172766016 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1717270343 # Nu system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498450 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index b5f680e0c..81b928843 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 85e384123..79676436b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:41:00 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:57:20 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 88752965000 because target called exit() +122 123 124 Exiting @ tick 76322764500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index dd675185f..cd7596c98 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.088753 # Number of seconds simulated -sim_ticks 88752965000 # Number of ticks simulated -final_tick 88752965000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.076323 # Number of seconds simulated +sim_ticks 76322764500 # Number of ticks simulated +final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137389 # Simulator instruction rate (inst/s) -host_op_rate 150427 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70763677 # Simulator tick rate (ticks/s) -host_mem_usage 230996 # Number of bytes of host memory used -host_seconds 1254.22 # Real time elapsed on the host -sim_insts 172315134 # Number of instructions simulated -sim_ops 188668617 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 245120 # Number of bytes read from this memory -system.physmem.bytes_inst_read 132800 # Number of instructions bytes read from this memory +host_inst_rate 160991 # Simulator instruction rate (inst/s) +host_op_rate 176268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71299389 # Simulator tick rate (ticks/s) +host_mem_usage 228164 # Number of bytes of host memory used +host_seconds 1070.45 # Real time elapsed on the host +sim_insts 172333279 # Number of instructions simulated +sim_ops 188686762 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 246592 # Number of bytes read from this memory +system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3830 # Number of read requests responded to by this memory +system.physmem.num_reads 3853 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2761823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1496288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2761823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,316 +63,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 177505931 # number of cpu cycles simulated +system.cpu.numCycles 152645530 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 95571520 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 75157417 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6614903 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 45712904 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 43519744 # Number of BTB hits +system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4405793 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115592 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 39981641 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 379098511 # Number of instructions fetch has processed -system.cpu.fetch.Branches 95571520 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47925537 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80419547 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27360994 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36321255 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9619 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 36794328 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1674379 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 177448059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.339145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.059886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 97198391 54.78% 54.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5418485 3.05% 57.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10378909 5.85% 63.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10238278 5.77% 69.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8615978 4.86% 74.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6776678 3.82% 78.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6211591 3.50% 81.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8309244 4.68% 86.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24300505 13.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 177448059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.538413 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.135695 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46244696 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 34742594 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74394013 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1503955 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20562801 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14594283 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162509 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 391670680 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 678477 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20562801 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52453090 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 543058 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28975165 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 69650922 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5263023 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 366605935 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 86833 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2872425 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 626371131 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1557311065 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1540047768 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17263297 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298063520 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 328307611 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2289898 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2280879 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 22663777 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 42181045 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 15903489 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4032649 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2834648 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 323955475 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2094173 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249134070 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 566766 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 135834494 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 345192034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 457957 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 177448059 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.403983 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.631604 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 78553048 44.27% 44.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 28575726 16.10% 60.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26790293 15.10% 75.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 21442072 12.08% 87.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12420165 7.00% 94.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5896079 3.32% 97.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3065113 1.73% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 544695 0.31% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 160868 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 177448059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 586662 26.53% 26.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5526 0.25% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 139 0.01% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 26 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1170221 52.93% 79.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 448459 20.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194883965 78.22% 78.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995226 0.40% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33040 0.01% 78.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164177 0.07% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 253566 0.10% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76466 0.03% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 466502 0.19% 79.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206303 0.08% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71862 0.03% 79.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38048843 15.27% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13933800 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249134070 # Type of FU issued -system.cpu.iq.rate 1.403525 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2211033 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008875 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 674734020 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 459694658 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237377529 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3759978 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2202441 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1840495 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 249450810 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1894293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1632018 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued +system.cpu.iq.rate 1.659274 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12329139 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13400 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3256434 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 152 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20562801 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11850 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 518 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 326106294 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1027766 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 42181045 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 15903489 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2071684 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 257 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13400 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4154974 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3938016 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8092990 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242315384 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36530974 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6818686 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 56646 # number of nop insts executed -system.cpu.iew.exec_refs 50147755 # number of memory reference insts executed -system.cpu.iew.exec_branches 53661515 # Number of branches executed -system.cpu.iew.exec_stores 13616781 # Number of stores executed -system.cpu.iew.exec_rate 1.365111 # Inst execution rate -system.cpu.iew.wb_sent 240126243 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239218024 # cumulative count of insts written-back -system.cpu.iew.wb_producers 143974107 # num instructions producing a value -system.cpu.iew.wb_consumers 250982237 # num instructions consuming a value +system.cpu.iew.exec_nop 58893 # number of nop insts executed +system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed +system.cpu.iew.exec_branches 54101167 # Number of branches executed +system.cpu.iew.exec_stores 13816344 # Number of stores executed +system.cpu.iew.exec_rate 1.612486 # Inst execution rate +system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150184249 # num instructions producing a value +system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.347662 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.573643 # average fanout of values written-back +system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172329522 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188683005 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 137423310 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1636216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6480810 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 156885259 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.202682 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.914186 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79822518 50.88% 50.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 37410215 23.85% 74.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15894720 10.13% 84.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8464339 5.40% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4786654 3.05% 93.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1458057 0.93% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1746360 1.11% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1243896 0.79% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6058500 3.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 156885259 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172329522 # Number of instructions committed -system.cpu.commit.committedOps 188683005 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347667 # Number of instructions committed +system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498961 # Number of memory references committed -system.cpu.commit.loads 29851906 # Number of loads committed +system.cpu.commit.refs 42506219 # Number of memory references committed +system.cpu.commit.loads 29855535 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40284104 # Number of branches committed +system.cpu.commit.branches 40287733 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115909 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130425 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6058500 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 476927873 # The number of ROB reads -system.cpu.rob.rob_writes 672877067 # The number of ROB writes -system.cpu.timesIdled 1694 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 57872 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172315134 # Number of Instructions Simulated -system.cpu.committedOps 188668617 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172315134 # Number of Instructions Simulated -system.cpu.cpi 1.030124 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.030124 # CPI: Total CPI of All Threads -system.cpu.ipc 0.970757 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.970757 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1076172941 # number of integer regfile reads -system.cpu.int_regfile_writes 384809064 # number of integer regfile writes -system.cpu.fp_regfile_reads 2908130 # number of floating regfile reads -system.cpu.fp_regfile_writes 2493684 # number of floating regfile writes -system.cpu.misc_regfile_reads 462718931 # number of misc regfile reads -system.cpu.misc_regfile_writes 824878 # number of misc regfile writes -system.cpu.icache.replacements 2566 # number of replacements -system.cpu.icache.tagsinuse 1372.206162 # Cycle average of tags in use -system.cpu.icache.total_refs 36789295 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4311 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8533.819299 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 458778355 # The number of ROB reads +system.cpu.rob.rob_writes 693498788 # The number of ROB writes +system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333279 # Number of Instructions Simulated +system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated +system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads +system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads +system.cpu.int_regfile_writes 388952433 # number of integer regfile writes +system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads +system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes +system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads +system.cpu.misc_regfile_writes 832136 # number of misc regfile writes +system.cpu.icache.replacements 2645 # number of replacements +system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use +system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1372.206162 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.670023 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.670023 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36789295 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36789295 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36789295 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36789295 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36789295 # number of overall hits -system.cpu.icache.overall_hits::total 36789295 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5033 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5033 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5033 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5033 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5033 # number of overall misses -system.cpu.icache.overall_misses::total 5033 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 109886500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 109886500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 109886500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 109886500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 109886500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 109886500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36794328 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36794328 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36794328 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36794328 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36794328 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36794328 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits +system.cpu.icache.overall_hits::total 37836261 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses +system.cpu.icache.overall_misses::total 5199 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21833.200874 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21833.200874 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21833.200874 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,214 +381,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 722 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 722 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 722 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 722 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 722 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 722 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4311 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4311 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4311 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4311 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4311 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4311 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78475000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 78475000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78475000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 78475000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78475000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 78475000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18203.433078 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18203.433078 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18203.433078 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4395 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4395 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4395 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4395 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4395 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78893000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1411.383328 # Cycle average of tags in use -system.cpu.dcache.total_refs 46835892 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25126.551502 # Average number of references to valid blocks. +system.cpu.dcache.replacements 59 # number of replacements +system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use +system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1411.383328 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.344576 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.344576 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34426629 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34426629 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356789 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356789 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 27646 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 27646 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 24828 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 24828 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46783418 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46783418 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46783418 # number of overall hits -system.cpu.dcache.overall_hits::total 46783418 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1806 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1806 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7498 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7498 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.347081 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.347081 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34919209 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34919209 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356677 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356677 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 30319 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 30319 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28457 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28457 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 47275886 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47275886 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47275886 # number of overall hits +system.cpu.dcache.overall_hits::total 47275886 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1860 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1860 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7610 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7610 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9304 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9304 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9304 # number of overall misses -system.cpu.dcache.overall_misses::total 9304 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59300000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59300000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 235066000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 235066000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9470 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9470 # 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number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 294366000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34428435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34428435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 297920500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 297920500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 297920500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 297920500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34921069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34921069 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000199 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000199 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32834.994463 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31350.493465 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30321 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31638.650043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31638.650043 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # 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number of overall misses +system.cpu.l2cache.overall_misses::total 3871 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71492500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24574000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 96066500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36706000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 36706000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 71492500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 61280000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 132772500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 71492500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 61280000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 132772500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 804 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5199 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1077 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1077 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4395 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1881 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6276 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4395 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1881 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -598,50 +598,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3830 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3830 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64436000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20976000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85412000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33589000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33589000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64436000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54565000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 119001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64436000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54565000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 119001000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869509 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992661 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.493976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31167.904903 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31043.438078 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.493976 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31091.168091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.493976 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31091.168091 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2084 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 701 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2785 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1068 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1068 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2084 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3853 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2084 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1769 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3853 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64692000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21857000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 86549000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33156000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33156000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64692000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 55013000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 7c9dcfcb7..3c665fa33 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 36b361cbc..a15e6fee3 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:37:27 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 18:08:16 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index d09b5d511..ffec0c1d3 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106771000 # Number of ticks simulated final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3116971 # Simulator instruction rate (inst/s) -host_op_rate 3412781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1865050079 # Simulator tick rate (ticks/s) -host_mem_usage 219792 # Number of bytes of host memory used -host_seconds 55.28 # Real time elapsed on the host +host_inst_rate 2490166 # Simulator instruction rate (inst/s) +host_op_rate 2726490 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1489999442 # Simulator tick rate (ticks/s) +host_mem_usage 216948 # Number of bytes of host memory used +host_seconds 69.20 # Real time elapsed on the host sim_insts 172317417 # Number of instructions simulated sim_ops 188670900 # Number of ops (including micro ops) simulated system.physmem.bytes_read 869973902 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 188670900 # Nu system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32534025 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls system.cpu.num_int_insts 150106226 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_int_register_reads 809396650 # number of times the integer registers were read diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index f911a437c..a0f7615f4 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 322e5b2f2..1602e57ed 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:38:33 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 18:09:36 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 96e0b8441..843b32b30 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232077 # Nu sim_ticks 232077154000 # Number of ticks simulated final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1962361 # Simulator instruction rate (inst/s) -host_op_rate 2148995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2650211347 # Simulator tick rate (ticks/s) -host_mem_usage 228700 # Number of bytes of host memory used -host_seconds 87.57 # Real time elapsed on the host +host_inst_rate 1841932 # Simulator instruction rate (inst/s) +host_op_rate 2017113 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2487570299 # Simulator tick rate (ticks/s) +host_mem_usage 226116 # Number of bytes of host memory used +host_seconds 93.29 # Real time elapsed on the host sim_insts 171842491 # Number of instructions simulated sim_ops 188185929 # Number of ops (including micro ops) simulated system.physmem.bytes_read 220992 # Number of bytes read from this memory @@ -71,7 +71,7 @@ system.cpu.committedOps 188185929 # Nu system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32534025 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls system.cpu.num_int_insts 150106226 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read |