diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/se | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/se')
29 files changed, 5636 insertions, 5649 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 508ed63ed..5d753bb44 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061241 # Nu sim_ticks 61241011500 # Number of ticks simulated final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 266495 # Simulator instruction rate (inst/s) -host_op_rate 267822 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 180131185 # Simulator tick rate (ticks/s) -host_mem_usage 451088 # Number of bytes of host memory used -host_seconds 339.98 # Real time elapsed on the host +host_inst_rate 253883 # Simulator instruction rate (inst/s) +host_op_rate 255147 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171606317 # Simulator tick rate (ticks/s) +host_mem_usage 452068 # Number of bytes of host memory used +host_seconds 356.87 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -791,18 +791,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2670 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2848092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 950995 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 8cda29cfd..9603ee85e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058178 # Number of seconds simulated -sim_ticks 58178156500 # Number of ticks simulated -final_tick 58178156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058179 # Number of seconds simulated +sim_ticks 58178990500 # Number of ticks simulated +final_tick 58178990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123327 # Simulator instruction rate (inst/s) -host_op_rate 123942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79202629 # Simulator tick rate (ticks/s) -host_mem_usage 528964 # Number of bytes of host memory used -host_seconds 734.55 # Real time elapsed on the host +host_inst_rate 122973 # Simulator instruction rate (inst/s) +host_op_rate 123585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78976040 # Simulator tick rate (ticks/s) +host_mem_usage 539340 # Number of bytes of host memory used +host_seconds 736.67 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 55744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 924288 # Number of bytes read from this memory -system.physmem.bytes_read::total 1024768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10048 # Number of bytes written to this memory -system.physmem.bytes_written::total 10048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16012 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 157 # Number of write requests responded to by this memory -system.physmem.num_writes::total 157 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 768948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 958160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15887200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17614309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 768948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 768948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 172711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 172711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 172711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 768948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 958160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15887200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16013 # Number of read requests accepted -system.physmem.writeReqs 157 # Number of write requests accepted -system.physmem.readBursts 16013 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1017152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 8064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1024832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10048 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 56 # Number of requests that are neither read nor write +system.physmem.bytes_read::cpu.inst 44864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 57344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 923968 # Number of bytes read from this memory +system.physmem.bytes_read::total 1026176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10880 # Number of bytes written to this memory +system.physmem.bytes_written::total 10880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 701 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14437 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16034 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 170 # Number of write requests responded to by this memory +system.physmem.num_writes::total 170 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 771137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 985648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15881472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17638257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 771137 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 771137 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 771137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 985648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15881472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17825266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16035 # Number of read requests accepted +system.physmem.writeReqs 170 # Number of write requests accepted +system.physmem.readBursts 16035 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 170 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1017600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue +system.physmem.bytesWritten 9088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1026240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1166 # Per bank write bursts system.physmem.perBankRdBursts::1 919 # Per bank write bursts -system.physmem.perBankRdBursts::2 952 # Per bank write bursts -system.physmem.perBankRdBursts::3 1030 # Per bank write bursts +system.physmem.perBankRdBursts::2 953 # Per bank write bursts +system.physmem.perBankRdBursts::3 1033 # Per bank write bursts system.physmem.perBankRdBursts::4 1062 # Per bank write bursts -system.physmem.perBankRdBursts::5 1117 # Per bank write bursts -system.physmem.perBankRdBursts::6 1098 # Per bank write bursts -system.physmem.perBankRdBursts::7 1090 # Per bank write bursts +system.physmem.perBankRdBursts::5 1116 # Per bank write bursts +system.physmem.perBankRdBursts::6 1091 # Per bank write bursts +system.physmem.perBankRdBursts::7 1089 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 936 # Per bank write bursts -system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 905 # Per bank write bursts -system.physmem.perBankRdBursts::13 898 # Per bank write bursts -system.physmem.perBankRdBursts::14 901 # Per bank write bursts -system.physmem.perBankRdBursts::15 934 # Per bank write bursts +system.physmem.perBankRdBursts::10 937 # Per bank write bursts +system.physmem.perBankRdBursts::11 900 # Per bank write bursts +system.physmem.perBankRdBursts::12 906 # Per bank write bursts +system.physmem.perBankRdBursts::13 899 # Per bank write bursts +system.physmem.perBankRdBursts::14 910 # Per bank write bursts +system.physmem.perBankRdBursts::15 933 # Per bank write bursts system.physmem.perBankWrBursts::0 7 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 6 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 8 # Per bank write bursts +system.physmem.perBankWrBursts::2 12 # Per bank write bursts +system.physmem.perBankWrBursts::3 4 # Per bank write bursts +system.physmem.perBankWrBursts::4 3 # Per bank write bursts system.physmem.perBankWrBursts::5 12 # Per bank write bursts -system.physmem.perBankWrBursts::6 30 # Per bank write bursts +system.physmem.perBankWrBursts::6 37 # Per bank write bursts system.physmem.perBankWrBursts::7 2 # Per bank write bursts -system.physmem.perBankWrBursts::8 5 # Per bank write bursts +system.physmem.perBankWrBursts::8 2 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 11 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 4 # Per bank write bursts -system.physmem.perBankWrBursts::13 16 # Per bank write bursts -system.physmem.perBankWrBursts::14 23 # Per bank write bursts -system.physmem.perBankWrBursts::15 2 # Per bank write bursts +system.physmem.perBankWrBursts::10 6 # Per bank write bursts +system.physmem.perBankWrBursts::11 4 # Per bank write bursts +system.physmem.perBankWrBursts::12 7 # Per bank write bursts +system.physmem.perBankWrBursts::13 12 # Per bank write bursts +system.physmem.perBankWrBursts::14 33 # Per bank write bursts +system.physmem.perBankWrBursts::15 1 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58178148000 # Total gap between requests +system.physmem.totGap 58178982000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16013 # Read request sizes (log2) +system.physmem.readPktSize::6 16035 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2533 # What read queue length does an incoming req see +system.physmem.writePktSize::6 170 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2530 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 292 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 315 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 291 # What read queue length does an incoming req see @@ -150,22 +150,22 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,90 +197,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 579.332201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 345.781267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 429.630743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 460 26.03% 26.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 205 11.60% 37.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 5.26% 42.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 3.57% 46.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 46 2.60% 49.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 3.23% 52.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 50 2.83% 55.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 49 2.77% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 744 42.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1767 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2257.857143 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 93.171857 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 5824.405132 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 6 85.71% 85.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 14.29% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 7 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.physmem.totQLat 173222344 # Total ticks spent queuing -system.physmem.totMemAccLat 471216094 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79465000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10899.29 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29649.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s +system.physmem.bytesPerActivate::samples 1792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 572.928571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 339.689561 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 430.205419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 476 26.56% 26.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 210 11.72% 38.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 5.41% 43.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 3.52% 47.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 46 2.57% 49.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 3.18% 52.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 50 2.79% 55.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 48 2.68% 58.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 745 41.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1792 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1980.250000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 75.328493 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 5451.280656 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.750000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.736929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.707107 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 7 87.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads +system.physmem.totQLat 173529353 # Total ticks spent queuing +system.physmem.totMemAccLat 471654353 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10913.11 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.69 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29661.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.20 # Average write queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.26 # Average write queue length when enqueuing system.physmem.readRowHits 14205 # Number of row buffer hits during reads -system.physmem.writeRowHits 38 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 25.00 # Row buffer hit rate for writes -system.physmem.avgGap 3597906.49 # Average gap between requests -system.physmem.pageHitRate 88.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7673400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4186875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 65488800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 421200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2652037290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32576451750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39105711075 # Total energy per rank (pJ) -system.physmem_0.averagePower 672.250549 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54182179525 # Time in different power states +system.physmem.writeRowHits 45 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 27.11 # Row buffer hit rate for writes +system.physmem.avgGap 3590187.10 # Average gap between requests +system.physmem.pageHitRate 88.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7794360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4252875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 65746200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 498960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2649738195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32583140250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39111131160 # Total energy per rank (pJ) +system.physmem_0.averagePower 672.253743 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54193285294 # Time in different power states system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2046707975 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2043128456 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58141200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 395280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2310125355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32876366250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39053220225 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.348359 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54689145986 # Time in different power states +system.physmem_1.actEnergy 5753160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3139125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58273800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 421200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2342596545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32852562750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39062706900 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.421412 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54644034494 # Time in different power states system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1544922014 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1592379256 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257532 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279536 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837837 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842353 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784700 # Number of BTB hits +system.cpu.branchPred.lookups 28257760 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279733 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837848 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842330 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784674 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513163 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.513136 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75804 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -400,83 +402,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116356314 # number of cpu cycles simulated +system.cpu.numCycles 116357982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748715 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134987552 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257532 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860500 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114713884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679087 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 748703 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134988401 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257760 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860478 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114715121 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679113 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32302381 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 573 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116303952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165899 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 32302514 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 574 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116305190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165894 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.319044 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58732386 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13942591 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230864 7.94% 70.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398111 29.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58733287 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13942631 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230901 7.94% 70.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398371 29.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116303952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242853 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160122 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839872 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64043721 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33034735 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558318 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827306 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101307 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 116305190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242852 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.160113 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839704 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64044923 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33035218 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558027 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827318 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101316 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114430502 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996250 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15281424 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49886472 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109365 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35424721 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14774664 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110898746 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1414946 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11132654 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1143672 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1526966 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 487708 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483272295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119473751 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 114430969 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996281 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827318 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15281065 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49888125 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109559 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35425090 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14774033 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110899108 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1414941 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11132282 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1143663 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1527047 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 487517 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129956871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483273963 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119474159 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22643952 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4359 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21508806 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812600 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5350060 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 518904 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 253933 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109691142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21508074 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812702 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5350076 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 518927 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253927 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109691489 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8248 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101388881 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1075842 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18658360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41690770 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101389067 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1075877 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18658707 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41691247 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116303952 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871758 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116305190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871750 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989327 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54663353 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31360946 26.96% 73.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22009705 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7071580 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1198055 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54664640 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31360805 26.96% 73.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22009670 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7071691 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1198071 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -484,9 +486,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116303952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116305190 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9787032 48.68% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9787073 48.68% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.68% # attempts to use FU when none available @@ -515,12 +517,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614737 47.82% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 704136 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614641 47.82% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 704123 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71984931 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71985140 71.00% 71.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10711 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued @@ -549,82 +551,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343463 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049594 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343416 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049618 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101388881 # Type of FU issued -system.cpu.iq.rate 0.871366 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20105968 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198305 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340263064 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128358435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99626003 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101389067 # Type of FU issued +system.cpu.iq.rate 0.871355 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20105900 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198304 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340264641 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128359131 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99626279 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121494609 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121494727 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 289420 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 289423 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4336689 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336791 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1514 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1345 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 605216 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1348 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 605232 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7563 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130752 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7566 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130606 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8114677 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684104 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109712059 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827318 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8114310 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 683997 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109712406 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812600 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5350060 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26812702 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5350076 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4360 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178830 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1345 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436596 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412868 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849464 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100127809 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806782 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1261072 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 178818 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342272 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1348 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436595 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849476 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100127969 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806710 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1261098 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12669 # number of nop insts executed -system.cpu.iew.exec_refs 28724706 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624810 # Number of branches executed -system.cpu.iew.exec_stores 4917924 # Number of stores executed -system.cpu.iew.exec_rate 0.860528 # Inst execution rate -system.cpu.iew.wb_sent 99710755 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99626115 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59703966 # num instructions producing a value -system.cpu.iew.wb_consumers 95545842 # num instructions consuming a value -system.cpu.iew.wb_rate 0.856216 # insts written-back per cycle +system.cpu.iew.exec_refs 28724643 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624882 # Number of branches executed +system.cpu.iew.exec_stores 4917933 # Number of stores executed +system.cpu.iew.exec_rate 0.860517 # Inst execution rate +system.cpu.iew.wb_sent 99711034 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99626392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59704097 # num instructions producing a value +system.cpu.iew.wb_consumers 95546076 # num instructions consuming a value +system.cpu.iew.wb_rate 0.856206 # insts written-back per cycle system.cpu.iew.wb_fanout 0.624872 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17384633 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17384953 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825600 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113611791 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801445 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737925 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825610 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113612998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737923 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77186972 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18613328 16.38% 84.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7152554 6.30% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469014 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644498 1.45% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541954 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704210 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178949 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120312 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77188479 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18612991 16.38% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7152574 6.30% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3468909 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644585 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541952 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704226 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178939 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120343 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113611791 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113612998 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -670,78 +672,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120312 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217924017 # The number of ROB reads -system.cpu.rob.rob_writes 219569293 # The number of ROB writes -system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 52362 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120343 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217925513 # The number of ROB reads +system.cpu.rob.rob_writes 219569964 # The number of ROB writes +system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52792 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284431 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284431 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778555 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778555 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108111974 # number of integer regfile reads -system.cpu.int_regfile_writes 58701043 # number of integer regfile writes +system.cpu.cpi 1.284449 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284449 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778544 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778544 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108112150 # number of integer regfile reads +system.cpu.int_regfile_writes 58701199 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 92 # number of floating regfile writes -system.cpu.cc_regfile_reads 369066936 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693781 # number of cc regfile writes -system.cpu.misc_regfile_reads 28415091 # number of misc regfile reads +system.cpu.fp_regfile_writes 93 # number of floating regfile writes +system.cpu.cc_regfile_reads 369067542 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693892 # number of cc regfile writes +system.cpu.misc_regfile_reads 28415154 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470182 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.784909 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18253071 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470694 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336518 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 5470195 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.784912 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18253010 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470707 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336499 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 35707500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.784909 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.784912 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999580 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61911082 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61911082 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13891036 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13891036 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353748 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353748 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61911209 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61911209 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13890997 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13890997 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353726 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353726 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18244784 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18244784 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18245306 # number of overall hits -system.cpu.dcache.overall_hits::total 18245306 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585874 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585874 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381233 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381233 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18244723 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18244723 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18245245 # number of overall hits +system.cpu.dcache.overall_hits::total 18245245 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585970 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585970 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381255 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381255 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9967107 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9967107 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9967114 # number of overall misses -system.cpu.dcache.overall_misses::total 9967114 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88735069500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88735069500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002231848 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4002231848 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9967225 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9967225 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9967232 # number of overall misses +system.cpu.dcache.overall_misses::total 9967232 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88736242500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88736242500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002302858 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4002302858 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92737301348 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92737301348 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92737301348 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92737301348 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23476910 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23476910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 92738545358 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92738545358 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92738545358 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92738545358 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23476967 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23476967 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -750,100 +752,100 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28211891 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28211891 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28212420 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28212420 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408311 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408311 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28211948 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28211948 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28212477 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28212477 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408314 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408314 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080519 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080519 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353295 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353295 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353288 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353288 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.857486 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.857486 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10498.125419 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10498.125419 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353298 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353298 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353292 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353292 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.887149 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.887149 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10497.705887 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10497.705887 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.334884 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9304.334884 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.328349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9304.328349 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329976 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 109342 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121408 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12843 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717910 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.513743 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.349541 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9304.349541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.343007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9304.343007 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 330007 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 109189 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121421 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12842 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717874 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.502492 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5470182 # number of writebacks -system.cpu.dcache.writebacks::total 5470182 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337666 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337666 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158748 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158748 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5470195 # number of writebacks +system.cpu.dcache.writebacks::total 5470195 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337753 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337753 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158766 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158766 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496414 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496414 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496414 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496414 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248208 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248208 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222485 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222485 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496519 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496519 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496519 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496519 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248217 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248217 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222489 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222489 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470693 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470693 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470697 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470697 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43256008000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43256008000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285824228 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285824228 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5470706 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470706 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470710 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470710 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43257355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43257355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285854739 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285854739 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45541832228 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45541832228 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45542046728 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45542046728 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223548 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223548 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45543210239 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45543210239 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45543424739 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45543424739 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223547 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223547 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193914 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193915 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.052906 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.052906 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.059950 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.059950 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.295526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.295526 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.012374 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.012374 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.691630 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.691630 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.724752 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.724752 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.923737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.923737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.956859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.956859 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 452 # number of replacements -system.cpu.icache.tags.tagsinuse 428.759370 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32301211 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 428.759642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32301343 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 911 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35456.872667 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35457.017563 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.759370 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 428.759642 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.837421 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.837421 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id @@ -852,208 +854,207 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 52 system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64605645 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64605645 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32301211 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32301211 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32301211 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32301211 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61324481 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32302367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32302367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32302367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32302367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32302367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32302367 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64605911 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64605911 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32301343 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32301343 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32301343 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32301343 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32301343 # number of overall hits +system.cpu.icache.overall_hits::total 32301343 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1157 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1157 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1157 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1157 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1157 # number of overall misses +system.cpu.icache.overall_misses::total 1157 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61697981 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61697981 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61697981 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61697981 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61697981 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61697981 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32302500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32302500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32302500 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32302500 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32302500 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32302500 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53048.858997 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53048.858997 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53048.858997 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53048.858997 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53048.858997 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53048.858997 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18977 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53325.826275 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53325.826275 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53325.826275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53325.826275 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18986 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 108 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.342222 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84.382222 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 21.600000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 452 # number of writebacks system.cpu.icache.writebacks::total 452 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 912 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 912 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50084985 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50084985 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50084985 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50084985 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50084985 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50084985 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50324485 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50324485 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50324485 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50324485 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50324485 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50324485 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54917.746711 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54917.746711 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54917.746711 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54917.746711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54917.746711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54917.746711 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55180.356360 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55180.356360 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4981768 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14883 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 357.232547 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14075593 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 236 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11228.158132 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5318864 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14906 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 356.827050 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11063.435293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 164.424136 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.675259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010036 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.685294 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 174 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14497 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11064.722538 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 163.435594 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.675337 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009975 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.685312 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 176 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14494 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3710 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 891 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010620 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 890 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010742 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884644 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180495153 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180495153 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 5450602 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5450602 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 17129 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17129 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 226024 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 226024 # 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number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 703 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1087 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1790 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 703 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1087 # number of overall misses +system.cpu.l2cache.overall_misses::total 1790 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 60500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41219500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41219500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48001500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 48001500 # 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number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17129 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226523 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 226523 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 912 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 912 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244175 # 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number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 170 # number of writebacks +system.cpu.l2cache.writebacks::total 170 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 193 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 190 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316256 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 317829 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852114791 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852114791 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 50000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 50000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32658500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32658500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43494500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43494500 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35150000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43736000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67834500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 111570500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43736000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67834500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 851895298 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 963465798 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.767544 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000101 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000287 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000160 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.769737 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000106 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000106 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000292 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058087 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.383003 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.383003 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16666.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16666.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95492.690058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95492.690058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62135 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62135 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64145.951036 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64145.951036 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62135 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76426.116838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70066.433566 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62135 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76426.116838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.383003 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3027.820907 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058077 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.370534 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95848.973607 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95848.973607 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62301.994302 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62301.994302 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63219.424460 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63219.424460 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69775.171982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3031.911881 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 10942243 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470651 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 10942269 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470664 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2916 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 303048 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302740 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 303004 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302696 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 308 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5245086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5453690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1285 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5245095 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5450772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 20045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226523 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244175 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16410940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700030528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700116992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 319578 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5791182 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052888 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.224048 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244184 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2275 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16411619 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16413894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 87232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700217984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700305216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 319547 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5791165 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052881 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.224033 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485204 94.72% 94.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305670 5.28% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485231 94.72% 94.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305626 5.28% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 308 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5791182 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10941755515 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5791165 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10941781515 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 7525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1367997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1367498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206046991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206066491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15672 # Transaction distribution -system.membus.trans_dist::WritebackDirty 157 # Transaction distribution -system.membus.trans_dist::CleanEvict 51 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5 # Transaction distribution +system.membus.trans_dist::ReadResp 15694 # Transaction distribution +system.membus.trans_dist::WritebackDirty 170 # Transaction distribution +system.membus.trans_dist::CleanEvict 58 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4 # Transaction distribution system.membus.trans_dist::ReadExReq 340 # Transaction distribution system.membus.trans_dist::ReadExResp 340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15673 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32243 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32243 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1034816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1034816 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 15695 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32301 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1037056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1037056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16226 # Request fanout histogram +system.membus.snoop_fanout::samples 16267 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16226 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16267 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16226 # Request fanout histogram -system.membus.reqLayer0.occupancy 26763807 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16267 # Request fanout histogram +system.membus.reqLayer0.occupancy 26872796 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 83802056 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 83907066 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 5dc111e3a..4cc0ff469 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361598 # Nu sim_ticks 361597758500 # Number of ticks simulated final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1135132 # Simulator instruction rate (inst/s) -host_op_rate 1135179 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1683423955 # Simulator tick rate (ticks/s) -host_mem_usage 429008 # Number of bytes of host memory used -host_seconds 214.80 # Real time elapsed on the host +host_inst_rate 1193747 # Simulator instruction rate (inst/s) +host_op_rate 1193796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1770350920 # Simulator tick rate (ticks/s) +host_mem_usage 429888 # Number of bytes of host memory used +host_seconds 204.25 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -473,14 +473,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index ddbe14f27..9741f69fb 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061602 # Nu sim_ticks 61602281500 # Number of ticks simulated final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108860 # Simulator instruction rate (inst/s) -host_op_rate 191684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42446103 # Simulator tick rate (ticks/s) -host_mem_usage 458164 # Number of bytes of host memory used -host_seconds 1451.31 # Real time elapsed on the host +host_inst_rate 110070 # Simulator instruction rate (inst/s) +host_op_rate 193816 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42918086 # Simulator tick rate (ticks/s) +host_mem_usage 460124 # Number of bytes of host memory used +host_seconds 1435.35 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 1947008 # To system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 24 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1928 # Per bank write bursts system.physmem.perBankRdBursts::1 2059 # Per bank write bursts system.physmem.perBankRdBursts::2 2023 # Per bank write bursts @@ -343,15 +343,15 @@ system.cpu.rename.tempSerializingInsts 490 # co system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49402348 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322302018 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 63884608 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 63882730 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle @@ -467,7 +467,7 @@ system.cpu.iew.iewDispatchedInsts 322303732 # Nu system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispNonSpecInsts 1101 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations @@ -486,9 +486,9 @@ system.cpu.iew.exec_rate 2.476830 # In system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back system.cpu.iew.wb_producers 230213909 # num instructions producing a value -system.cpu.iew.wb_consumers 333860979 # num instructions consuming a value +system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back +system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted @@ -956,7 +956,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5974 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6015 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution @@ -964,8 +964,8 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # T system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225133 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6227214 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 168253993..c6f6cfa54 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.412076 # Nu sim_ticks 412076211500 # Number of ticks simulated final_tick 412076211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 332870 # Simulator instruction rate (inst/s) -host_op_rate 332870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 224166223 # Simulator tick rate (ticks/s) -host_mem_usage 300688 # Number of bytes of host memory used -host_seconds 1838.26 # Real time elapsed on the host +host_inst_rate 319842 # Simulator instruction rate (inst/s) +host_op_rate 319842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215393213 # Simulator tick rate (ticks/s) +host_mem_usage 301832 # Number of bytes of host memory used +host_seconds 1913.13 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 24299648 # To system.physmem.bytesWrittenSys 18790784 # Total written bytes from the system interface side system.physmem.servicedByWrQ 352 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 51706 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 23686 # Per bank write bursts system.physmem.perBankRdBursts::1 23158 # Per bank write bursts system.physmem.perBankRdBursts::2 23442 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 17195 # Pe system.physmem.perBankWrBursts::15 17131 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 412076182000 # Total gap between requests +system.physmem.totGap 412076123500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -256,7 +256,7 @@ system.physmem.readRowHits 314253 # Nu system.physmem.writeRowHits 216307 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.67 # Row buffer hit rate for writes -system.physmem.avgGap 612035.54 # Average gap between requests +system.physmem.avgGap 612035.45 # Average gap between requests system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 548334360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 299190375 # Energy for precharge commands per rank (pJ) diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 232b217c8..2d282091b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.363578 # Nu sim_ticks 363578056500 # Number of ticks simulated final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237399 # Simulator instruction rate (inst/s) -host_op_rate 257134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 170382928 # Simulator tick rate (ticks/s) -host_mem_usage 321244 # Number of bytes of host memory used -host_seconds 2133.89 # Real time elapsed on the host +host_inst_rate 233007 # Simulator instruction rate (inst/s) +host_op_rate 252377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167231069 # Simulator tick rate (ticks/s) +host_mem_usage 322224 # Number of bytes of host memory used +host_seconds 2174.11 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 9212032 # To system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12571 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9337 # Per bank write bursts system.physmem.perBankRdBursts::1 8920 # Per bank write bursts system.physmem.perBankRdBursts::2 8993 # Per bank write bursts @@ -835,18 +835,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 17475 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 82243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 86920 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56641 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423464 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3480105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2371712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56877 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3428141 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3485018 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2386816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 143961216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 143976320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 112366 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 4134d7329..965a91be2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.234001 # Number of seconds simulated -sim_ticks 234001297000 # Number of ticks simulated -final_tick 234001297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233976 # Number of seconds simulated +sim_ticks 233975583000 # Number of ticks simulated +final_tick 233975583000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134504 # Simulator instruction rate (inst/s) -host_op_rate 145716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62295833 # Simulator tick rate (ticks/s) -host_mem_usage 343376 # Number of bytes of host memory used -host_seconds 3756.29 # Real time elapsed on the host +host_inst_rate 134400 # Simulator instruction rate (inst/s) +host_op_rate 145602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62240486 # Simulator tick rate (ticks/s) +host_mem_usage 347620 # Number of bytes of host memory used +host_seconds 3759.22 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 517504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10131008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16480064 # Number of bytes read from this memory -system.physmem.bytes_read::total 27128576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 517504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 517504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18730688 # Number of bytes written to this memory -system.physmem.bytes_written::total 18730688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8086 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257501 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423884 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292667 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292667 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2211543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43294666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70427234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 115933443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2211543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2211543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80045232 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80045232 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80045232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2211543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43294666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70427234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195978674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423884 # Number of read requests accepted -system.physmem.writeReqs 292667 # Number of write requests accepted -system.physmem.readBursts 423884 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292667 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26972992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 155584 # Total number of bytes read from write queue -system.physmem.bytesWritten 18728832 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27128576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18730688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2431 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 98651 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26584 # Per bank write bursts -system.physmem.perBankRdBursts::1 25337 # Per bank write bursts -system.physmem.perBankRdBursts::2 25274 # Per bank write bursts -system.physmem.perBankRdBursts::3 32197 # Per bank write bursts -system.physmem.perBankRdBursts::4 27335 # Per bank write bursts -system.physmem.perBankRdBursts::5 28299 # Per bank write bursts -system.physmem.perBankRdBursts::6 25126 # Per bank write bursts -system.physmem.perBankRdBursts::7 24198 # Per bank write bursts -system.physmem.perBankRdBursts::8 25368 # Per bank write bursts -system.physmem.perBankRdBursts::9 25926 # Per bank write bursts -system.physmem.perBankRdBursts::10 25318 # Per bank write bursts -system.physmem.perBankRdBursts::11 26278 # Per bank write bursts -system.physmem.perBankRdBursts::12 27572 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 519680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10101184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16452992 # Number of bytes read from this memory +system.physmem.bytes_read::total 27073856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 519680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 519680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18693440 # Number of bytes written to this memory +system.physmem.bytes_written::total 18693440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257078 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423029 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292085 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292085 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2221086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43171958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70319269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 115712313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2221086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2221086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79894832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79894832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79894832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2221086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43171958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70319269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195607146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423029 # Number of read requests accepted +system.physmem.writeReqs 292085 # Number of write requests accepted +system.physmem.readBursts 423029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292085 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26921664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue +system.physmem.bytesWritten 18690816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27073856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18693440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26587 # Per bank write bursts +system.physmem.perBankRdBursts::1 25566 # Per bank write bursts +system.physmem.perBankRdBursts::2 25266 # Per bank write bursts +system.physmem.perBankRdBursts::3 32149 # Per bank write bursts +system.physmem.perBankRdBursts::4 27127 # Per bank write bursts +system.physmem.perBankRdBursts::5 28227 # Per bank write bursts +system.physmem.perBankRdBursts::6 25084 # Per bank write bursts +system.physmem.perBankRdBursts::7 24199 # Per bank write bursts +system.physmem.perBankRdBursts::8 25413 # Per bank write bursts +system.physmem.perBankRdBursts::9 25760 # Per bank write bursts +system.physmem.perBankRdBursts::10 25321 # Per bank write bursts +system.physmem.perBankRdBursts::11 26053 # Per bank write bursts +system.physmem.perBankRdBursts::12 27496 # Per bank write bursts system.physmem.perBankRdBursts::13 25872 # Per bank write bursts -system.physmem.perBankRdBursts::14 25056 # Per bank write bursts -system.physmem.perBankRdBursts::15 25713 # Per bank write bursts -system.physmem.perBankWrBursts::0 18662 # Per bank write bursts -system.physmem.perBankWrBursts::1 18231 # Per bank write bursts -system.physmem.perBankWrBursts::2 18003 # Per bank write bursts -system.physmem.perBankWrBursts::3 17875 # Per bank write bursts -system.physmem.perBankWrBursts::4 18721 # Per bank write bursts -system.physmem.perBankWrBursts::5 18310 # Per bank write bursts -system.physmem.perBankWrBursts::6 17836 # Per bank write bursts -system.physmem.perBankWrBursts::7 17744 # Per bank write bursts -system.physmem.perBankWrBursts::8 17983 # Per bank write bursts -system.physmem.perBankWrBursts::9 17940 # Per bank write bursts -system.physmem.perBankWrBursts::10 18239 # Per bank write bursts -system.physmem.perBankWrBursts::11 18938 # Per bank write bursts -system.physmem.perBankWrBursts::12 18976 # Per bank write bursts -system.physmem.perBankWrBursts::13 18211 # Per bank write bursts -system.physmem.perBankWrBursts::14 18390 # Per bank write bursts -system.physmem.perBankWrBursts::15 18579 # Per bank write bursts +system.physmem.perBankRdBursts::14 24848 # Per bank write bursts +system.physmem.perBankRdBursts::15 25683 # Per bank write bursts +system.physmem.perBankWrBursts::0 18549 # Per bank write bursts +system.physmem.perBankWrBursts::1 18359 # Per bank write bursts +system.physmem.perBankWrBursts::2 17952 # Per bank write bursts +system.physmem.perBankWrBursts::3 17851 # Per bank write bursts +system.physmem.perBankWrBursts::4 18559 # Per bank write bursts +system.physmem.perBankWrBursts::5 18328 # Per bank write bursts +system.physmem.perBankWrBursts::6 17864 # Per bank write bursts +system.physmem.perBankWrBursts::7 17725 # Per bank write bursts +system.physmem.perBankWrBursts::8 17897 # Per bank write bursts +system.physmem.perBankWrBursts::9 17869 # Per bank write bursts +system.physmem.perBankWrBursts::10 18218 # Per bank write bursts +system.physmem.perBankWrBursts::11 18760 # Per bank write bursts +system.physmem.perBankWrBursts::12 18894 # Per bank write bursts +system.physmem.perBankWrBursts::13 18283 # Per bank write bursts +system.physmem.perBankWrBursts::14 18348 # Per bank write bursts +system.physmem.perBankWrBursts::15 18588 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 234001244500 # Total gap between requests +system.physmem.totGap 233975530500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423884 # Read request sizes (log2) +system.physmem.readPktSize::6 423029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292667 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 323806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292085 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 323238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,35 +148,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -197,112 +197,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 322061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.901068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.764285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 180.057081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 202493 62.87% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79759 24.77% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15144 4.70% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7279 2.26% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4961 1.54% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2580 0.80% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1828 0.57% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1538 0.48% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6479 2.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 322061 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17076 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.676095 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 143.384257 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17074 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 321539 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.852976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.721857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 179.991773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 202400 62.95% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79393 24.69% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15074 4.69% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7330 2.28% 94.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4928 1.53% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2561 0.80% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1887 0.59% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1542 0.48% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6424 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 321539 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.666979 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 143.647395 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17048 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17076 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17076 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.137386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.076722 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.519222 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9254 54.19% 54.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 359 2.10% 56.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5270 30.86% 87.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1365 7.99% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 405 2.37% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 163 0.95% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 106 0.62% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 62 0.36% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 41 0.24% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 19 0.11% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17050 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.128680 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.068427 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.524733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9277 54.41% 54.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 307 1.80% 56.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5331 31.27% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1349 7.91% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 375 2.20% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 167 0.98% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 95 0.56% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 68 0.40% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 36 0.21% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.09% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.05% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17076 # Writes before turning the bus around for reads -system.physmem.totQLat 8693371575 # Total ticks spent queuing -system.physmem.totMemAccLat 16595615325 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2107265000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20627.14 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::42 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17050 # Writes before turning the bus around for reads +system.physmem.totQLat 8699002486 # Total ticks spent queuing +system.physmem.totMemAccLat 16586208736 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2103255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20679.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39377.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 115.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39429.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.88 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 115.71 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.89 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage +system.physmem.busUtil 1.52 # Data bus utilization in percentage system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.60 # Average write queue length when enqueuing -system.physmem.readRowHits 306420 # Number of row buffer hits during reads -system.physmem.writeRowHits 85606 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.25 # Row buffer hit rate for writes -system.physmem.avgGap 326566.07 # Average gap between requests -system.physmem.pageHitRate 54.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1224553680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 668159250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1671883200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942075360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82043634285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 68432158500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 170266217955 # Total energy per rank (pJ) -system.physmem_0.averagePower 727.632069 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 113312610225 # Time in different power states -system.physmem_0.memoryStateTime::REF 7813780000 # Time in different power states +system.physmem.avgWrQLen 21.61 # Average write queue length when enqueuing +system.physmem.readRowHits 305767 # Number of row buffer hits during reads +system.physmem.writeRowHits 85381 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.23 # Row buffer hit rate for writes +system.physmem.avgGap 327186.34 # Average gap between requests +system.physmem.pageHitRate 54.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1223691840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 667689000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1670487000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 940811760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 82095857685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 68367661500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170247918225 # Total energy per rank (pJ) +system.physmem_0.averagePower 727.650714 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 113204918849 # Time in different power states +system.physmem_0.memoryStateTime::REF 7812740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112874154775 # Time in different power states +system.physmem_0.memoryStateTime::ACT 112953795651 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1210227480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 660342375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1615325400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 954218880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79914700530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70299646500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169938214845 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.230337 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 116426727240 # Time in different power states -system.physmem_1.memoryStateTime::REF 7813780000 # Time in different power states +system.physmem_1.actEnergy 1207044720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 658605750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1610044800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 951633360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79725813930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 70446639000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169881501000 # Total energy per rank (pJ) +system.physmem_1.averagePower 726.084666 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 116677189668 # Time in different power states +system.physmem_1.memoryStateTime::REF 7812740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109759940510 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109482083332 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175128597 # Number of BP lookups -system.cpu.branchPred.condPredicted 131371974 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444955 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90537565 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83893856 # Number of BTB hits +system.cpu.branchPred.lookups 175127231 # Number of BP lookups +system.cpu.branchPred.condPredicted 131371482 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444734 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90531038 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83892410 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.661931 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12111370 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104180 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.667014 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12111505 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,94 +421,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 468002595 # number of cpu cycles simulated +system.cpu.numCycles 467951167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7807530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731939592 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175128597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 96005226 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 452073756 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14942657 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4553 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11657 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236761982 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 33954 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 467369003 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.696062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.181505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7807571 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731933483 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175127231 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 96003915 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 452021991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942209 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11591 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236759344 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34037 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 467317920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696233 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.181442 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95368751 20.41% 20.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132719598 28.40% 48.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57874720 12.38% 61.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181405934 38.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95319924 20.40% 20.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132721002 28.40% 48.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57871857 12.38% 61.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181405137 38.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 467369003 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374204 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.563965 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32359971 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 118993599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 286955454 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22077159 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982820 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24051378 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496211 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715838012 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30014698 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982820 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63444256 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55810223 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40372652 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276569326 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24189726 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686622974 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13340540 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9445783 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2386683 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1668073 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1901045 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831058832 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019300335 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723953090 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 467317920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374243 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.564124 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32360208 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118941905 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 286956233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22076930 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982644 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24050421 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715840292 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30013840 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982644 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63442941 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55755110 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40375220 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276571280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24190725 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686624983 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13341882 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9442632 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2386991 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1673870 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1900758 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831052151 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019309313 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723953553 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176935081 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544712 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1535132 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42423418 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143529755 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67982396 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12868793 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11217167 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668185878 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978339 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610253474 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5862945 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123813272 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319307246 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 707 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 467369003 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.305721 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.102066 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176928400 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1535125 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42420493 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143531079 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67984063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12865529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11219958 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668189770 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978336 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610255971 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5862329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123817161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319322709 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 704 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 467317920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.305869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 150209828 32.14% 32.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101164226 21.65% 53.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145806231 31.20% 84.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63278562 13.54% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6909680 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 476 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 150163836 32.13% 32.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101159501 21.65% 53.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145796763 31.20% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63288828 13.54% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6908500 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 492 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 467369003 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 467317920 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71905667 52.96% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71905236 52.96% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available @@ -537,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44557603 32.82% 85.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19305643 14.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44555950 32.82% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19306846 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413150420 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413151233 67.70% 67.70% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued @@ -571,82 +571,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134216313 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62534943 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134217204 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62535736 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610253474 # Type of FU issued -system.cpu.iq.rate 1.303953 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135768943 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829507546 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 795005708 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594983942 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610255971 # Type of FU issued +system.cpu.iq.rate 1.304102 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135768062 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829459960 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 795013485 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594984726 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746022240 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746023856 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7274295 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7274448 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27644999 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25509 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28969 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11121919 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27646323 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25541 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28976 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11123586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225058 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22341 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225332 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22431 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982820 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22939909 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 921157 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672651686 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982644 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22928683 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 924923 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672655804 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143529755 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67982396 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489797 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258383 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 526747 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28969 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822799 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731713 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7554512 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599398028 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129575309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10855446 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143531079 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67984063 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489794 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258689 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 530260 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28976 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822816 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731718 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554534 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599400071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129576716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10855900 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487469 # number of nop insts executed -system.cpu.iew.exec_refs 190532110 # number of memory reference insts executed -system.cpu.iew.exec_branches 131373386 # Number of branches executed -system.cpu.iew.exec_stores 60956801 # Number of stores executed -system.cpu.iew.exec_rate 1.280758 # Inst execution rate -system.cpu.iew.wb_sent 596278477 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594983958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349895185 # num instructions producing a value -system.cpu.iew.wb_consumers 570621697 # num instructions consuming a value -system.cpu.iew.wb_rate 1.271326 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613182 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 110038028 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1487698 # number of nop insts executed +system.cpu.iew.exec_refs 190533409 # number of memory reference insts executed +system.cpu.iew.exec_branches 131373584 # Number of branches executed +system.cpu.iew.exec_stores 60956693 # Number of stores executed +system.cpu.iew.exec_rate 1.280903 # Inst execution rate +system.cpu.iew.wb_sent 596279806 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594984742 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349898988 # num instructions producing a value +system.cpu.iew.wb_consumers 570632014 # num instructions consuming a value +system.cpu.iew.wb_rate 1.271468 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613178 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 110042423 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6956447 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 450252376 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.218638 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.886273 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956274 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 450200687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.218778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.886375 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 221217275 49.13% 49.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116327442 25.84% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43752953 9.72% 84.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23318372 5.18% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11527046 2.56% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7779334 1.73% 94.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8252081 1.83% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4233959 0.94% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13843914 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 221166453 49.13% 49.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116327626 25.84% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43750418 9.72% 84.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23323090 5.18% 89.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11527236 2.56% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7779283 1.73% 94.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8247237 1.83% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4226436 0.94% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13852908 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 450252376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 450200687 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -692,78 +692,78 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13843914 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1095134181 # The number of ROB reads -system.cpu.rob.rob_writes 1334612111 # The number of ROB writes -system.cpu.timesIdled 12504 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 633592 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13852908 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095077893 # The number of ROB reads +system.cpu.rob.rob_writes 1334621527 # The number of ROB writes +system.cpu.timesIdled 12496 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 633247 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.926302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.926302 # CPI: Total CPI of All Threads -system.cpu.ipc 1.079562 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.079562 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611088799 # number of integer regfile reads -system.cpu.int_regfile_writes 328120173 # number of integer regfile writes +system.cpu.cpi 0.926200 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.926200 # CPI: Total CPI of All Threads +system.cpu.ipc 1.079680 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.079680 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611089761 # number of integer regfile reads +system.cpu.int_regfile_writes 328120494 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170182732 # number of cc regfile reads -system.cpu.cc_regfile_writes 376542810 # number of cc regfile writes -system.cpu.misc_regfile_reads 217972310 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170189724 # number of cc regfile reads +system.cpu.cc_regfile_writes 376542500 # number of cc regfile writes +system.cpu.misc_regfile_reads 217973496 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820726 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.629844 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169352944 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821238 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.027883 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2820720 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.629803 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169353985 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821232 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.028379 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.629844 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.629803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356245422 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356245422 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114648159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114648159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51724842 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51724842 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 356246516 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356246516 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114648880 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114648880 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51725160 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51725160 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166373001 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166373001 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166375784 # number of overall hits -system.cpu.dcache.overall_hits::total 166375784 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4844666 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4844666 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2514464 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2514464 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 166374040 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166374040 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166376823 # number of overall hits +system.cpu.dcache.overall_hits::total 166376823 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4844495 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4844495 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2514146 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2514146 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7359130 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7359130 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7359142 # number of overall misses -system.cpu.dcache.overall_misses::total 7359142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57569719500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57569719500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18925127941 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18925127941 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 7358641 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7358641 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7358653 # number of overall misses +system.cpu.dcache.overall_misses::total 7358653 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57544876000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57544876000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18904875439 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18904875439 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76494847441 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76494847441 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76494847441 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76494847441 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119492825 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119492825 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 76449751439 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 76449751439 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 76449751439 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 76449751439 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119493375 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119493375 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) @@ -772,72 +772,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173732131 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173732131 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173734926 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173734926 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040544 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040544 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046359 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046359 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173732681 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173732681 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173735476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173735476 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040542 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040542 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046353 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046353 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042359 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042359 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042358 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042358 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7526.505824 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7526.505824 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.042356 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042356 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11878.405489 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11878.405489 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7519.402389 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7519.402389 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10394.550367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10394.533417 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 905651 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221227 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.093763 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10389.112805 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10389.112805 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10389.095863 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10389.095863 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 904831 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221213 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.090316 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2820726 # number of writebacks -system.cpu.dcache.writebacks::total 2820726 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542974 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2542974 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994900 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1994900 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2820720 # number of writebacks +system.cpu.dcache.writebacks::total 2820720 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542826 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2542826 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994565 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1994565 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4537874 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4537874 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4537874 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4537874 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301692 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301692 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519564 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519564 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4537391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4537391 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4537391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4537391 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301669 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301669 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519581 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519581 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821256 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821256 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821266 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821266 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29568664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29568664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603651495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603651495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 644000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 644000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34172315995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34172315995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34172959995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34172959995 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2821250 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821250 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821260 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821260 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29551116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29551116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4600493494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4600493494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 704500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 704500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34151609494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34151609494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34152313994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34152313994 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses @@ -848,235 +848,237 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 system.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12846.490538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12846.490538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8860.605229 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8860.605229 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64400 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64400 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.447787 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.447787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.633121 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.633121 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12838.994660 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12838.994660 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8854.237345 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8854.237345 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70450 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70450 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12105.134070 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12105.134070 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12105.340874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12105.340874 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73505 # number of replacements -system.cpu.icache.tags.tagsinuse 466.324466 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236680067 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 74017 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3197.644690 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115567558500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.324466 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910790 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910790 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73492 # number of replacements +system.cpu.icache.tags.tagsinuse 466.319606 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236677467 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 74004 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.171275 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115561804500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.319606 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910780 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473597840 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473597840 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236680067 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236680067 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236680067 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236680067 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236680067 # number of overall hits -system.cpu.icache.overall_hits::total 236680067 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 81831 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 81831 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 81831 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 81831 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 81831 # number of overall misses -system.cpu.icache.overall_misses::total 81831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1321953198 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1321953198 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1321953198 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1321953198 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1321953198 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1321953198 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236761898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236761898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236761898 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236761898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236761898 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236761898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16154.674854 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16154.674854 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16154.674854 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16154.674854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16154.674854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16154.674854 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 160057 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 121 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6454 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.799659 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.200000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 473592523 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473592523 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236677467 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236677467 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236677467 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236677467 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236677467 # number of overall hits +system.cpu.icache.overall_hits::total 236677467 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 81779 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 81779 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 81779 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 81779 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 81779 # number of overall misses +system.cpu.icache.overall_misses::total 81779 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1323960223 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1323960223 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1323960223 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1323960223 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1323960223 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1323960223 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236759246 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236759246 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236759246 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236759246 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236759246 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236759246 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000345 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000345 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000345 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000345 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000345 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000345 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16189.489025 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16189.489025 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16189.489025 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16189.489025 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 155623 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6523 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 23.857581 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 73505 # number of writebacks -system.cpu.icache.writebacks::total 73505 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7785 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7785 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7785 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7785 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7785 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7785 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74046 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 74046 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 74046 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 74046 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 74046 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 74046 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1096634301 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1096634301 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1096634301 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1096634301 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1096634301 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1096634301 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 73492 # number of writebacks +system.cpu.icache.writebacks::total 73492 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7746 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7746 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7746 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74033 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74033 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74033 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74033 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74033 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74033 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1098365314 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1098365314 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1098365314 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1098365314 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1098365314 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1098365314 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14810.176120 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14810.176120 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14810.176120 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14810.176120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14810.176120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14810.176120 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14836.158389 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14836.158389 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513868 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8515266 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 405 # 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Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 170394344500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13787.674482 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 0.001651 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1343.185923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.841533 # Average percentage of cache occupancy +system.cpu.l2cache.prefetcher.pfSpanPage 743612 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 395043 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15130.846704 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3180527 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 410976 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.738960 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 5544 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5551 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 351023 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 351023 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3657 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3657 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8121 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8121 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154177 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 389000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 334746500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 334746500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 540727000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 540727000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10842464500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10842464500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 540727000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11177211000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11717938000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 540727000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11177211000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30364771753 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007070 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007070 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067242 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067242 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057468 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109740 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067055 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067055 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057320 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.178650 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.178562 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53121.401598 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14407.407407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14407.407407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91535.821712 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91535.821712 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66583.795099 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66583.795099 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70324.785798 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70324.785798 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70609.128981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58735.133319 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5789543 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894272 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23735 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 260412 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244232 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 2373325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2649267 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 513929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 265680 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 392283 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5789505 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894253 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23731 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 260682 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16011 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2373290 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2650619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 535678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 265254 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 392218 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 74046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299281 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220710 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8661120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9386496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359623424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 369009920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 950663 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3845942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283574 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 521973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 74033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299259 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221525 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8463241 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8684766 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9439488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361084992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370524480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 949589 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3844850 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.078147 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283493 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3561756 92.61% 92.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268006 6.97% 99.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 16180 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3560398 92.60% 92.60% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 268441 6.98% 99.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 16011 0.42% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3845942 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5789002505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3844850 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788964505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111143345 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 111128336 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4231890461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4231881960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 420198 # Transaction distribution -system.membus.trans_dist::WritebackDirty 292667 # Transaction distribution -system.membus.trans_dist::CleanEvict 98618 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33 # Transaction distribution -system.membus.trans_dist::ReadExReq 3685 # Transaction distribution -system.membus.trans_dist::ReadExResp 3685 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420199 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1239118 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45859200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45859200 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 419375 # Transaction distribution +system.membus.trans_dist::WritebackDirty 292085 # Transaction distribution +system.membus.trans_dist::CleanEvict 98517 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31 # Transaction distribution +system.membus.trans_dist::ReadExReq 3653 # Transaction distribution +system.membus.trans_dist::ReadExResp 3653 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 419376 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1236690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1236690 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45767232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45767232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 815202 # Request fanout histogram +system.membus.snoop_fanout::samples 813662 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 815202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 813662 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 815202 # Request fanout histogram -system.membus.reqLayer0.occupancy 2212929834 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 813662 # Request fanout histogram +system.membus.reqLayer0.occupancy 2208946039 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2242544064 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2237977923 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index d23424e24..d35883c7b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.708526 # Nu sim_ticks 708526400500 # Number of ticks simulated final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 974268 # Simulator instruction rate (inst/s) -host_op_rate 1055088 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1366955379 # Simulator tick rate (ticks/s) -host_mem_usage 319428 # Number of bytes of host memory used -host_seconds 518.32 # Real time elapsed on the host +host_inst_rate 942956 # Simulator instruction rate (inst/s) +host_op_rate 1021179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1323022561 # Simulator tick rate (ticks/s) +host_mem_usage 320452 # Number of bytes of host memory used +host_seconds 535.54 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -608,18 +608,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 80784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 84208 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1361408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3412658 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3445488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142391552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142393920 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 110394 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1285bd093..b098baae5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403750 # Number of seconds simulated -sim_ticks 403750101500 # Number of ticks simulated -final_tick 403750101500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403427 # Number of seconds simulated +sim_ticks 403427114500 # Number of ticks simulated +final_tick 403427114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79008 # Simulator instruction rate (inst/s) -host_op_rate 146095 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38578288 # Simulator tick rate (ticks/s) -host_mem_usage 372460 # Number of bytes of host memory used -host_seconds 10465.73 # Real time elapsed on the host +host_inst_rate 97075 # Simulator instruction rate (inst/s) +host_op_rate 179503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47362243 # Simulator tick rate (ticks/s) +host_mem_usage 432836 # Number of bytes of host memory used +host_seconds 8517.91 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24546112 # Number of bytes read from this memory -system.physmem.bytes_read::total 24709696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory -system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 405162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60795309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61200470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 405162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 405162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46787436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46787436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46787436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 405162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60795309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107987906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386089 # Number of read requests accepted -system.physmem.writeReqs 295163 # Number of write requests accepted -system.physmem.readBursts 386089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24690880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18816 # Total number of bytes read from write queue -system.physmem.bytesWritten 18889216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24709696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 294 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 163328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24540032 # Number of bytes read from this memory +system.physmem.bytes_read::total 24703360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory +system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2552 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385990 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 404851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60828911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61233762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 404851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 404851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46816645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46816645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46816645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 404851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60828911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 108050407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385990 # Number of read requests accepted +system.physmem.writeReqs 295111 # Number of write requests accepted +system.physmem.readBursts 385990 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24683712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24703360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 250150 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24088 # Per bank write bursts -system.physmem.perBankRdBursts::1 26446 # Per bank write bursts -system.physmem.perBankRdBursts::2 24837 # Per bank write bursts -system.physmem.perBankRdBursts::3 24496 # Per bank write bursts -system.physmem.perBankRdBursts::4 23228 # Per bank write bursts -system.physmem.perBankRdBursts::5 23719 # Per bank write bursts -system.physmem.perBankRdBursts::6 24505 # Per bank write bursts -system.physmem.perBankRdBursts::7 24301 # Per bank write bursts -system.physmem.perBankRdBursts::8 23634 # Per bank write bursts -system.physmem.perBankRdBursts::9 23532 # Per bank write bursts -system.physmem.perBankRdBursts::10 24794 # Per bank write bursts -system.physmem.perBankRdBursts::11 23986 # Per bank write bursts -system.physmem.perBankRdBursts::12 23318 # Per bank write bursts -system.physmem.perBankRdBursts::13 22932 # Per bank write bursts -system.physmem.perBankRdBursts::14 24086 # Per bank write bursts -system.physmem.perBankRdBursts::15 23893 # Per bank write bursts -system.physmem.perBankWrBursts::0 18617 # Per bank write bursts -system.physmem.perBankWrBursts::1 19942 # Per bank write bursts -system.physmem.perBankWrBursts::2 19199 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24081 # Per bank write bursts +system.physmem.perBankRdBursts::1 26417 # Per bank write bursts +system.physmem.perBankRdBursts::2 24826 # Per bank write bursts +system.physmem.perBankRdBursts::3 24490 # Per bank write bursts +system.physmem.perBankRdBursts::4 23233 # Per bank write bursts +system.physmem.perBankRdBursts::5 23715 # Per bank write bursts +system.physmem.perBankRdBursts::6 24493 # Per bank write bursts +system.physmem.perBankRdBursts::7 24296 # Per bank write bursts +system.physmem.perBankRdBursts::8 23625 # Per bank write bursts +system.physmem.perBankRdBursts::9 23520 # Per bank write bursts +system.physmem.perBankRdBursts::10 24786 # Per bank write bursts +system.physmem.perBankRdBursts::11 23961 # Per bank write bursts +system.physmem.perBankRdBursts::12 23329 # Per bank write bursts +system.physmem.perBankRdBursts::13 22937 # Per bank write bursts +system.physmem.perBankRdBursts::14 24074 # Per bank write bursts +system.physmem.perBankRdBursts::15 23900 # Per bank write bursts +system.physmem.perBankWrBursts::0 18616 # Per bank write bursts +system.physmem.perBankWrBursts::1 19936 # Per bank write bursts +system.physmem.perBankWrBursts::2 19195 # Per bank write bursts system.physmem.perBankWrBursts::3 19026 # Per bank write bursts -system.physmem.perBankWrBursts::4 18119 # Per bank write bursts -system.physmem.perBankWrBursts::5 18516 # Per bank write bursts -system.physmem.perBankWrBursts::6 19139 # Per bank write bursts +system.physmem.perBankWrBursts::4 18116 # Per bank write bursts +system.physmem.perBankWrBursts::5 18513 # Per bank write bursts +system.physmem.perBankWrBursts::6 19137 # Per bank write bursts system.physmem.perBankWrBursts::7 19093 # Per bank write bursts -system.physmem.perBankWrBursts::8 18647 # Per bank write bursts -system.physmem.perBankWrBursts::9 17956 # Per bank write bursts -system.physmem.perBankWrBursts::10 18916 # Per bank write bursts -system.physmem.perBankWrBursts::11 17762 # Per bank write bursts -system.physmem.perBankWrBursts::12 17409 # Per bank write bursts -system.physmem.perBankWrBursts::13 17014 # Per bank write bursts -system.physmem.perBankWrBursts::14 17906 # Per bank write bursts -system.physmem.perBankWrBursts::15 17883 # Per bank write bursts +system.physmem.perBankWrBursts::8 18645 # Per bank write bursts +system.physmem.perBankWrBursts::9 17955 # Per bank write bursts +system.physmem.perBankWrBursts::10 18907 # Per bank write bursts +system.physmem.perBankWrBursts::11 17752 # Per bank write bursts +system.physmem.perBankWrBursts::12 17408 # Per bank write bursts +system.physmem.perBankWrBursts::13 17006 # Per bank write bursts +system.physmem.perBankWrBursts::14 17895 # Per bank write bursts +system.physmem.perBankWrBursts::15 17879 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403750059500 # Total gap between requests +system.physmem.totGap 403427072500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386089 # Read request sizes (log2) +system.physmem.readPktSize::6 385990 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380878 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4562 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295111 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17662 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see @@ -193,43 +193,43 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146856 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.750885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.556415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.540822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54126 36.86% 36.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39800 27.10% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13820 9.41% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7615 5.19% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5593 3.81% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4060 2.76% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2963 2.02% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2671 1.82% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16208 11.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146856 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.039017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 217.962707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17495 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.528440 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.268112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.869611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54238 36.92% 36.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39906 27.16% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13861 9.43% 73.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7527 5.12% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5392 3.67% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3977 2.71% 85.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3022 2.06% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16198 11.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146923 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.029360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 217.887118 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17505 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17505 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.860554 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.781765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.832914 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17316 98.92% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 135 0.77% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 27 0.15% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.854915 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.776896 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.816664 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17316 98.91% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 131 0.75% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 34 0.19% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads @@ -238,202 +238,202 @@ system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17505 # Writes before turning the bus around for reads -system.physmem.totQLat 4284897750 # Total ticks spent queuing -system.physmem.totMemAccLat 11518554000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1928975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11106.67 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads +system.physmem.totQLat 4287997000 # Total ticks spent queuing +system.physmem.totMemAccLat 11519553250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1928415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11117.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29856.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29867.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.23 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.88 # Average write queue length when enqueuing -system.physmem.readRowHits 318212 # Number of row buffer hits during reads -system.physmem.writeRowHits 215865 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing +system.physmem.readRowHits 318108 # Number of row buffer hits during reads +system.physmem.writeRowHits 215717 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.13 # Row buffer hit rate for writes -system.physmem.avgGap 592658.90 # Average gap between requests -system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 568406160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310142250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1525828200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 982679040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62107024725 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187769234250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279634184865 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.595037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311821526250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13482040000 # Time in different power states +system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes +system.physmem.avgGap 592316.08 # Average gap between requests +system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 568655640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310278375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1525157400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 982374480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62248054410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187449302250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279433333275 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.658624 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311288113000 # Time in different power states +system.physmem_0.memoryStateTime::REF 13471120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78445652750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78663487000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 541726920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 295585125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1483162200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 929646720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60264291960 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189385666500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279270949665 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.695380 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314524575500 # Time in different power states -system.physmem_1.memoryStateTime::REF 13482040000 # Time in different power states +system.physmem_1.actEnergy 541689120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295564500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1482585000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 929322720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60147053505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189292285500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279038011065 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.678700 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314369366250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13471120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75741865750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75582067750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219275491 # Number of BP lookups -system.cpu.branchPred.condPredicted 219275491 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8530842 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 123996876 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121809369 # Number of BTB hits +system.cpu.branchPred.lookups 219277494 # Number of BP lookups +system.cpu.branchPred.condPredicted 219277494 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8530091 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 124020025 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121811454 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.235837 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27061771 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1406477 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.219182 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27064699 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1406143 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807500204 # number of cpu cycles simulated +system.cpu.numCycles 806854230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175896513 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208663738 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219275491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148871140 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621734900 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17770351 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 224 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 92919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 734617 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1497 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170765697 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2319587 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 175890438 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208681477 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219277494 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148876153 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621110348 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17764353 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 91101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 722324 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1300 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170768195 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2322348 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807345886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.785599 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 806697934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.787860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367990 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417315550 51.69% 51.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32556197 4.03% 55.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31914797 3.95% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32648264 4.04% 63.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26601298 3.29% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26865092 3.33% 70.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35140610 4.35% 74.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31395380 3.89% 78.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172908698 21.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 416692027 51.65% 51.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32514924 4.03% 55.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31852485 3.95% 59.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32737208 4.06% 63.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26535487 3.29% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26940530 3.34% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35175393 4.36% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31366288 3.89% 78.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172883592 21.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807345886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271549 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496797 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120455538 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370723147 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225174137 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82107889 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8885175 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132090689 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8885175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152508786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150703188 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44276 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271505228 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223699233 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088450374 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134027 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138145056 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24847890 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50675847 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190623948 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5277971052 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3356955770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 59583 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 806697934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271768 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.498017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120436174 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370050155 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225346926 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81982503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8882176 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132175908 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8882176 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152549485 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150499256 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 41235 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271495233 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223230549 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088541699 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133771 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138231059 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24777266 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50120464 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190713921 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278163786 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357090809 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 59859 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576583094 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3244 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3058 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 422095496 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507123971 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200816092 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229029695 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68201156 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023089277 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22810 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1789046992 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 413186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494123386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 832685562 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22258 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807345886 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.215961 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.071124 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576673067 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3285 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3078 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422612041 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507148674 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200824572 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 228968697 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68242516 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023165492 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27791 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1789027795 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 414599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494204582 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 832990276 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 27239 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 806697934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.217717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070743 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238839063 29.58% 29.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123555302 15.30% 44.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118726852 14.71% 59.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107721401 13.34% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89742056 11.12% 84.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60203262 7.46% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42304747 5.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18964857 2.35% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7288346 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238149356 29.52% 29.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123576451 15.32% 44.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 118711028 14.72% 59.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107747587 13.36% 72.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89829016 11.14% 84.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60156883 7.46% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42289548 5.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18955760 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7282305 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807345886 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 806697934 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11498108 42.65% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12352662 45.82% 88.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3109525 11.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11505863 42.68% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12343295 45.78% 88.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3110421 11.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2715586 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183095329 66.13% 66.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 369789 0.02% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881135 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2715990 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183116627 66.13% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 369664 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881147 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 118 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 62 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 375 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 58 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -455,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428554849 23.95% 90.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170429736 9.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428537576 23.95% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170406235 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1789046992 # Type of FU issued -system.cpu.iq.rate 2.215538 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26960295 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015070 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412783736 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517485001 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762397634 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 29615 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 68960 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5614 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813278705 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12996 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186120882 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1789027795 # Type of FU issued +system.cpu.iq.rate 2.217287 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26959579 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015069 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412098039 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517646847 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762392188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29663 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69110 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5652 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813258358 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 13026 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185949248 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123024315 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213288 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 372216 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51655906 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123048931 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213773 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 371791 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51664386 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 23026 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 23126 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1127 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8885175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97857746 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6188485 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023112087 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 370282 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507126472 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200816092 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7124 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1833420 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3447634 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 372216 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4845141 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4138975 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8984116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1770027933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423156069 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19019059 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8882176 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97661574 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6126306 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023193283 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371095 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507151088 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200824572 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 12039 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1828108 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3395741 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 371791 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4845230 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4136012 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8981242 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1770011750 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423132476 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19016045 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590393535 # number of memory reference insts executed -system.cpu.iew.exec_branches 168976878 # Number of branches executed -system.cpu.iew.exec_stores 167237466 # Number of stores executed -system.cpu.iew.exec_rate 2.191985 # Inst execution rate -system.cpu.iew.wb_sent 1766902573 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762403248 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339734836 # num instructions producing a value -system.cpu.iew.wb_consumers 2050019870 # num instructions consuming a value -system.cpu.iew.wb_rate 2.182542 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653523 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 494186003 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 590347878 # number of memory reference insts executed +system.cpu.iew.exec_branches 168976982 # Number of branches executed +system.cpu.iew.exec_stores 167215402 # Number of stores executed +system.cpu.iew.exec_rate 2.193719 # Inst execution rate +system.cpu.iew.wb_sent 1766881473 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762397840 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339889750 # num instructions producing a value +system.cpu.iew.wb_consumers 2050179516 # num instructions consuming a value +system.cpu.iew.wb_rate 2.184283 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653548 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 494265381 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8613223 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 740134628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.065825 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.576078 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8610728 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 739482483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.067647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.576172 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276181742 37.32% 37.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172028130 23.24% 60.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55891908 7.55% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86294140 11.66% 79.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25858762 3.49% 83.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26505188 3.58% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9830635 1.33% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9003447 1.22% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78540676 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 275479046 37.25% 37.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172073402 23.27% 60.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 55823940 7.55% 68.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86367064 11.68% 79.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25894199 3.50% 83.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26482728 3.58% 86.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9848964 1.33% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9023113 1.22% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78490027 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 740134628 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 739482483 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,350 +576,350 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78540676 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2684768656 # The number of ROB reads -system.cpu.rob.rob_writes 4113734804 # The number of ROB writes -system.cpu.timesIdled 1976 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 154318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78490027 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2684246538 # The number of ROB reads +system.cpu.rob.rob_writes 4113897788 # The number of ROB writes +system.cpu.timesIdled 1953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 156296 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.976566 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976566 # CPI: Total CPI of All Threads -system.cpu.ipc 1.023996 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.023996 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722734844 # number of integer regfile reads -system.cpu.int_regfile_writes 1435842493 # number of integer regfile writes -system.cpu.fp_regfile_reads 5827 # number of floating regfile reads -system.cpu.fp_regfile_writes 544 # number of floating regfile writes -system.cpu.cc_regfile_reads 596643147 # number of cc regfile reads -system.cpu.cc_regfile_writes 405466657 # number of cc regfile writes -system.cpu.misc_regfile_reads 971667313 # number of misc regfile reads +system.cpu.cpi 0.975785 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.975785 # CPI: Total CPI of All Threads +system.cpu.ipc 1.024816 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024816 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722631435 # number of integer regfile reads +system.cpu.int_regfile_writes 1435841734 # number of integer regfile writes +system.cpu.fp_regfile_reads 5845 # number of floating regfile reads +system.cpu.fp_regfile_writes 533 # number of floating regfile writes +system.cpu.cc_regfile_reads 596631944 # number of cc regfile reads +system.cpu.cc_regfile_writes 405465564 # number of cc regfile writes +system.cpu.misc_regfile_reads 971632310 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2531012 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.814248 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381842819 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2535108 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.621914 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530979 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.807694 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381987598 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535075 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.680985 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.814248 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.807694 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998000 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998000 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 866 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3174 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772778472 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772778472 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233189012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233189012 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148175395 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148175395 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381364407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381364407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381364407 # number of overall hits -system.cpu.dcache.overall_hits::total 381364407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2772468 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2772468 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 984807 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 984807 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3757275 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3757275 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3757275 # number of overall misses -system.cpu.dcache.overall_misses::total 3757275 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59137035000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59137035000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31243406496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31243406496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90380441496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90380441496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90380441496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90380441496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235961480 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235961480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 773071261 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 773071261 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233342532 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233342532 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148176085 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148176085 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381518617 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381518617 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381518617 # number of overall hits +system.cpu.dcache.overall_hits::total 381518617 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2765359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2765359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 984117 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 984117 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3749476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3749476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3749476 # number of overall misses +system.cpu.dcache.overall_misses::total 3749476 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58561335000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58561335000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30709347495 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30709347495 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89270682495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89270682495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89270682495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89270682495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 236107891 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 236107891 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385121682 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385121682 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385121682 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385121682 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006602 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006602 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009756 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009756 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009756 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009756 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21330.105523 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21330.105523 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31725.410660 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31725.410660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24054.784783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24054.784783 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9718 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 22 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1069 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385268093 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385268093 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385268093 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385268093 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011712 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011712 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006598 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006598 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009732 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009732 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009732 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009732 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21176.756797 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21176.756797 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31204.976131 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31204.976131 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23808.842221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23808.842221 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9995 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1075 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.090739 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.297674 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330580 # number of writebacks -system.cpu.dcache.writebacks::total 2330580 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007465 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1007465 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19412 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19412 # 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number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33567375500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33567375500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30021732998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 30021732998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63589108498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63589108498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63589108498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63589108498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006472 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006472 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007090 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007090 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.310734 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.310734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31097.874961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31097.874961 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330614 # number of writebacks +system.cpu.dcache.writebacks::total 2330614 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000418 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1000418 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19400 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19400 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1019818 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1019818 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33563285500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29489872497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29489872497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63053157997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63053157997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63053157997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63053157997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007475 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007475 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006468 # 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Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8206 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20784.791860 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.831951 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506754 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506754 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.931814 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 323 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341735047 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341735047 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170559843 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170559843 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170559843 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170559843 # 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miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001205 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001205 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001205 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5830.026767 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 5830.026767 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 5830.026767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 5830.026767 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1227 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 316 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1161 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341739287 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341739287 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170563080 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170563080 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170563080 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170563080 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170563080 # number of overall hits +system.cpu.icache.overall_hits::total 170563080 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 205114 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 205114 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 205114 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 205114 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 205114 # number of overall misses +system.cpu.icache.overall_misses::total 205114 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1195791500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1195791500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1195791500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1195791500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1195791500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1195791500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170768194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170768194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170768194 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170768194 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170768194 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170768194 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001201 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001201 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001201 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001201 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001201 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001201 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5829.887282 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 5829.887282 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 5829.887282 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 5829.887282 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 5829.887282 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 5829.887282 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 766 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.384615 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 76.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 6646 # number of writebacks -system.cpu.icache.writebacks::total 6646 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2196 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2196 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2196 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2196 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2196 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2196 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 203657 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 203657 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 203657 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 203657 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 203657 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 203657 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915942000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 915942000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915942000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 915942000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915942000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 915942000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001193 # 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average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79330.398828 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79330.398828 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82127.055599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82127.055599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80381.809275 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80381.809275 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82127.055599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79814.529903 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79829.829370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82127.055599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79814.529903 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79829.829370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -928,143 +928,142 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 295163 # number of writebacks -system.cpu.l2cache.writebacks::total 295163 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 295111 # number of writebacks +system.cpu.l2cache.writebacks::total 295111 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 8 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 193439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206924 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206924 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176660 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176660 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383584 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383584 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386141 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4268097007 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4268097007 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14346312000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14346312000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182391500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182391500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12431373500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12431373500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182391500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26777685500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26960077000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182391500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26777685500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26960077000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 192758 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 192758 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206906 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206906 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2553 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2553 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176579 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176579 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2553 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386038 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2553 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386038 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3718916993 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3718916993 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14344875500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14344875500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184165500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184165500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12427929541 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12427929541 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184165500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26772805041 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26956970541 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184165500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26772805041 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26956970541 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990522 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990522 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268556 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268556 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310353 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100113 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100113 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151824 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151824 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22064.304546 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22064.304546 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69331.310046 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69331.310046 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71330.269847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71330.269847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70368.920525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70368.920525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990621 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990621 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.311646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100070 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100070 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151788 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19293.191427 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19293.191427 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69330.398828 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69330.398828 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72136.897767 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72136.897767 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70381.696244 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70381.696244 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72136.897767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.477857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69829.836806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72136.897767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.477857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69829.836806 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5471713 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729811 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 210473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3600 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3600 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5470136 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729158 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 209637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3579 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3579 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1968256 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2625743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 249948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 195290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 195290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 203657 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764601 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 218138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7981134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8199272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 926784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312330816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 550771 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3289408 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.123462 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.328967 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1967447 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2625725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 260490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 194583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 194583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 202901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764548 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217689 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7990295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8207984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 946432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312350528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 549945 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3287795 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.123088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.328538 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2883292 87.65% 87.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 406116 12.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2883107 87.69% 87.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 404688 12.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3289408 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5101560430 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3287795 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5100517412 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 305490983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 304355486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3900309572 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3899906073 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179215 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution -system.membus.trans_dist::CleanEvict 56660 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193490 # Transaction distribution -system.membus.trans_dist::UpgradeResp 193490 # Transaction distribution -system.membus.trans_dist::ReadExReq 206873 # Transaction distribution -system.membus.trans_dist::ReadExResp 206873 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179216 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43600064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43600064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43600064 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179130 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution +system.membus.trans_dist::CleanEvict 56614 # Transaction distribution +system.membus.trans_dist::UpgradeReq 192805 # Transaction distribution +system.membus.trans_dist::ReadExReq 206859 # Transaction distribution +system.membus.trans_dist::ReadExResp 206859 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179131 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43590400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43590400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43590400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 931402 # Request fanout histogram +system.membus.snoop_fanout::samples 930520 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 931402 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 930520 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 931402 # Request fanout histogram -system.membus.reqLayer0.occupancy 2242581485 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 930520 # Request fanout histogram +system.membus.reqLayer0.occupancy 2239434504 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2429056686 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2041939000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 54314baaf..84e6b72bf 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.215512 # Nu sim_ticks 215512229500 # Number of ticks simulated final_tick 215512229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175368 # Simulator instruction rate (inst/s) -host_op_rate 210548 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138419960 # Simulator tick rate (ticks/s) -host_mem_usage 326400 # Number of bytes of host memory used -host_seconds 1556.94 # Real time elapsed on the host +host_inst_rate 167901 # Simulator instruction rate (inst/s) +host_op_rate 201584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132526721 # Simulator tick rate (ticks/s) +host_mem_usage 327404 # Number of bytes of host memory used +host_seconds 1626.18 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -795,18 +795,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 40448 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 21970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 36871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 344 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 38808 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99585 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 109845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3889728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 114486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 124862 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4843392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4243072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 5196736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 43319 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.349062 # Request fanout histogram diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d3ae1eec4..ac901384d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.116576 # Nu sim_ticks 116576497500 # Number of ticks simulated final_tick 116576497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122787 # Simulator instruction rate (inst/s) -host_op_rate 147419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52425325 # Simulator tick rate (ticks/s) -host_mem_usage 336136 # Number of bytes of host memory used -host_seconds 2223.67 # Real time elapsed on the host +host_inst_rate 117910 # Simulator instruction rate (inst/s) +host_op_rate 141564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50343079 # Simulator tick rate (ticks/s) +host_mem_usage 339456 # Number of bytes of host memory used +host_seconds 2315.64 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -44,7 +44,7 @@ system.physmem.bytesReadSys 5414912 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 955 # Per bank write bursts system.physmem.perBankRdBursts::1 811 # Per bank write bursts system.physmem.perBankRdBursts::2 833 # Per bank write bursts @@ -204,12 +204,12 @@ system.physmem.bytesPerActivate::768-895 32 0.14% 98.92% # By system.physmem.bytesPerActivate::896-1023 31 0.14% 99.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 209 0.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 22133 # Bytes accessed per row activation -system.physmem.totQLat 841966540 # Total ticks spent queuing -system.physmem.totMemAccLat 2428366540 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 841969540 # Total ticks spent queuing +system.physmem.totMemAccLat 2428369540 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 423040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9951.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9951.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28701.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28701.42 # Average memory access latency per DRAM burst system.physmem.avgRdBW 46.45 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 46.45 # Average system read bandwidth in MiByte/s @@ -231,28 +231,28 @@ system.physmem_0.preEnergy 78007875 # En system.physmem_0.readEnergy 595896600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63983016135 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 13820144250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 86234192340 # Total energy per rank (pJ) -system.physmem_0.averagePower 739.725124 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22625694019 # Time in different power states +system.physmem_0.actBackEnergy 63983019555 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 13820141250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 86234192760 # Total energy per rank (pJ) +system.physmem_0.averagePower 739.725127 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22625688019 # Time in different power states system.physmem_0.memoryStateTime::REF 3892720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 90057594731 # Time in different power states +system.physmem_0.memoryStateTime::ACT 90057600731 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 24358320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 13290750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 63999000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11183516280 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 60135495000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 79034819670 # Total energy per rank (pJ) -system.physmem_1.averagePower 677.968219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 99984327847 # Time in different power states +system.physmem_1.actBackEnergy 11183518845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 60135492750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 79034819985 # Total energy per rank (pJ) +system.physmem_1.averagePower 677.968221 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 99984324847 # Time in different power states system.physmem_1.memoryStateTime::REF 3892720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 12698960903 # Time in different power states +system.physmem_1.memoryStateTime::ACT 12698963903 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 37744347 # Number of BP lookups system.cpu.branchPred.condPredicted 20165678 # Number of conditional branches predicted @@ -388,29 +388,29 @@ system.cpu.fetch.icacheStallCycles 12613908 # Nu system.cpu.fetch.Insts 334078036 # Number of instructions fetch has processed system.cpu.fetch.Branches 37744347 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 24523917 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 217730983 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 217730977 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3511013 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 89097958 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 22048 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 232104146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 232104140 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.745924 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.249191 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58364727 25.15% 25.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58364721 25.15% 25.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 42980177 18.52% 43.66% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 30021674 12.93% 56.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 100737568 43.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 232104146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 232104140 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.161887 # Number of branch fetches per cycle system.cpu.fetch.rate 1.432870 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 28023980 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70770838 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 70770832 # Number of cycles decode is blocked system.cpu.decode.RunCycles 108573375 # Number of cycles decode is running system.cpu.decode.UnblockCycles 23115192 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1620761 # Number of cycles decode is squashing @@ -421,7 +421,7 @@ system.cpu.decode.SquashedInsts 6170266 # Nu system.cpu.rename.SquashCycles 1620761 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 45363672 # Number of cycles rename is idle system.cpu.rename.BlockCycles 24814789 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341990 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 341984 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 113350212 # Number of cycles rename is running system.cpu.rename.UnblockCycles 46612722 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 355770088 # Number of instructions processed by rename @@ -451,11 +451,11 @@ system.cpu.iq.iqSquashedInstsIssued 2301561 # Nu system.cpu.iq.iqSquashedInstsExamined 25470529 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 73751649 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5712 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 232104146 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 232104140 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.492598 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.113201 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47511470 20.47% 20.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47511464 20.47% 20.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 78618745 33.87% 54.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 60884809 26.23% 80.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 34936770 15.05% 95.63% # Number of insts issued each cycle @@ -467,7 +467,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 232104146 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 232104140 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9573854 7.69% 7.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 7345 0.01% 7.69% # attempts to use FU when none available @@ -540,7 +540,7 @@ system.cpu.iq.FU_type_0::total 346438253 # Ty system.cpu.iq.rate 1.485884 # Inst issue rate system.cpu.iq.fu_busy_cnt 124543678 # FU busy when requested system.cpu.iq.fu_busy_rate 0.359497 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 764166784 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 764166778 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 251741027 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 223260031 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 287659107 # Number of floating instruction queue reads @@ -591,11 +591,11 @@ system.cpu.iew.wb_fanout 0.576282 # av system.cpu.commit.commitSquashedInsts 23083392 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1611406 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 228378919 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 228378913 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.435387 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.036441 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 94653053 41.45% 41.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 94653047 41.45% 41.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 70419351 30.83% 72.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 20855772 9.13% 81.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 13391170 5.86% 87.28% # Number of insts commited each cycle @@ -607,7 +607,7 @@ system.cpu.commit.committed_per_cycle::8 10359612 4.54% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 228378919 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 228378913 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,10 +654,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction system.cpu.commit.bw_lim_events 10359612 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 568912390 # The number of ROB reads +system.cpu.rob.rob_reads 568912384 # The number of ROB reads system.cpu.rob.rob_writes 705520379 # The number of ROB writes system.cpu.timesIdled 58444 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1048850 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 1048856 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.853924 # CPI: Cycles Per Instruction @@ -717,14 +717,14 @@ system.cpu.dcache.overall_misses::cpu.data 3911467 # system.cpu.dcache.overall_misses::total 3911467 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 31000710000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 31000710000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8973516996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8973516996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8973513996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8973513996 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39974226996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39974226996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39974226996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39974226996 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39974223996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39974223996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39974223996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39974223996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 85407824 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 85407824 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) @@ -753,14 +753,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.023348 system.cpu.dcache.overall_miss_rate::total 0.023348 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11074.775169 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 11074.775169 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8068.033525 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8068.033525 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8068.030828 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8068.030828 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.800129 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10219.800129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.753099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10219.753099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.799362 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10219.799362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.752332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10219.752332 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1061203 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,14 +793,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1534352 system.cpu.dcache.overall_mshr_misses::total 1534352 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15231288500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 15231288500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828351773 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828351773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828348773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828348773 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17059640273 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17059640273 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17060321773 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17060321773 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17059637273 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17059637273 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17060318773 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17060318773 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015381 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015381 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses @@ -813,14 +813,14 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11594.314395 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11594.314395 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.020136 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.020136 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.006540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.006540 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61954.545455 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61954.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.545534 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.545534 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.909985 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.909985 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.543579 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.543579 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.908030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.908030 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 715978 # number of replacements system.cpu.icache.tags.tagsinuse 511.829667 # Cycle average of tags in use @@ -852,12 +852,12 @@ system.cpu.icache.demand_misses::cpu.inst 722244 # n system.cpu.icache.demand_misses::total 722244 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 722244 # number of overall misses system.cpu.icache.overall_misses::total 722244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 6486041445 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 6486041445 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 6486041445 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 6486041445 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 6486041445 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 6486041445 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 6486047445 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 6486047445 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 6486047445 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 6486047445 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 6486047445 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 6486047445 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 89097944 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 89097944 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 89097944 # number of demand (read+write) accesses @@ -870,12 +870,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.008106 system.cpu.icache.demand_miss_rate::total 0.008106 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.008106 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.008106 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8980.401976 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8980.401976 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8980.401976 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8980.401976 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8980.401976 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8980.401976 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8980.410284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8980.410284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8980.410284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8980.410284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8980.410284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8980.410284 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 66919 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2190 # number of cycles access was blocked @@ -898,38 +898,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 716491 system.cpu.icache.demand_mshr_misses::total 716491 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 716491 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 716491 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6035132455 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6035132455 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6035132455 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6035132455 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6035132455 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6035132455 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6035135455 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6035135455 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6035135455 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6035135455 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6035135455 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6035135455 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008042 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.008042 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.008042 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8423.179712 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8423.179712 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8423.179712 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8423.179712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8423.179712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8423.179712 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8423.183899 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8423.183899 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8423.183899 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8423.183899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8423.183899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8423.183899 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 404824 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 404865 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 404830 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404871 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 38 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28167 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 28177 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5610.545510 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 5610.545509 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3011470 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 6745 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 446.474426 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5502.326452 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 5502.326450 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 108.219059 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.335835 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006605 # Average percentage of cache occupancy @@ -982,20 +982,20 @@ system.cpu.l2cache.demand_misses::total 82055 # nu system.cpu.l2cache.overall_misses::cpu.inst 9709 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 72346 # number of overall misses system.cpu.l2cache.overall_misses::total 82055 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 19500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 19500 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55912000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 55912000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 697537000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 697537000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 697540000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 697540000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5069165500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5069165500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 697537000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 697540000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 5125077500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 5822614500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 697537000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 5822617500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 697540000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 5125077500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 5822614500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 5822617500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 965413 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 965413 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1035068 # number of WritebackClean accesses(hits+misses) @@ -1028,20 +1028,20 @@ system.cpu.l2cache.demand_miss_rate::total 0.036464 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013561 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.047151 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.036464 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19500 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72424.870466 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72424.870466 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71844.371202 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71844.371202 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71844.680194 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71844.680194 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70824.119094 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70824.119094 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71844.371202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71844.680194 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70841.200619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70959.898848 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.371202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70959.935409 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.680194 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70841.200619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70959.898848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70959.935409 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1062,8 +1062,8 @@ system.cpu.l2cache.demand_mshr_hits::total 89 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 77 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 89 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51607 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 51607 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51610 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 51610 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 728 # number of ReadExReq MSHR misses @@ -1077,25 +1077,25 @@ system.cpu.l2cache.demand_mshr_misses::cpu.data 72269 system.cpu.l2cache.demand_mshr_misses::total 81966 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 9697 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 72269 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51607 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 133573 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51610 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 133576 # number of overall MSHR misses system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180856312 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50141500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50141500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 638751500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 638751500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 638754500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 638754500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4638052000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4638052000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 638751500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 638754500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4688193500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5326945000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 638751500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5326948000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 638754500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4688193500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5507801312 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5507804312 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses @@ -1112,60 +1112,60 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.036424 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059358 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.491871 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3504.491871 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059359 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.288161 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3504.288161 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13500 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68875.686813 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68875.686813 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.042590 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.042590 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.351965 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.351965 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64830.684503 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64830.684503 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.042590 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.351965 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.690847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.042590 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.727448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.351965 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.491871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41234.391022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.288161 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41233.487393 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4500659 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249836 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249343 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 130203 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52857 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 130206 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77346 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 2030188 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 965413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1035068 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1284403 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 81238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 52995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 52998 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 716491 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313697 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2123993 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6501639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 90080128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 181970688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 272050816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134761 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2385076 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.191571 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2148432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4602542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6750974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91644224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 196364032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 288008256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134764 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2385079 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.191572 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.468754 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 2005511 84.09% 84.09% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 302219 12.67% 96.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 302222 12.67% 96.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 77346 3.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2385076 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2385079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4500145500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1075017936 # Layer occupancy (ticks) @@ -1174,12 +1174,11 @@ system.cpu.toL2Bus.respLayer1.occupancy 2302043463 # La system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 83880 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 728 # Transaction distribution system.membus.trans_dist::ReadExResp 728 # Transaction distribution system.membus.trans_dist::ReadSharedReq 83880 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169218 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 169218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169217 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 169217 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5414912 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 5414912 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) @@ -1195,7 +1194,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 84609 # Request fanout histogram system.membus.reqLayer0.occupancy 103435410 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 446650667 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 446648668 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 863619ff4..42b8a5c86 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517291 # Nu sim_ticks 517291025500 # Number of ticks simulated final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 635145 # Simulator instruction rate (inst/s) -host_op_rate 762516 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1204648551 # Simulator tick rate (ticks/s) -host_mem_usage 323584 # Number of bytes of host memory used -host_seconds 429.41 # Real time elapsed on the host +host_inst_rate 634406 # Simulator instruction rate (inst/s) +host_op_rate 761628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1203245454 # Simulator tick rate (ticks/s) +host_mem_usage 324572 # Number of bytes of host memory used +host_seconds 429.91 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -602,18 +602,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37418 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10207 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 47625 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1396160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1746624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 1ecb81d4d..fb73a0a48 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.560955 # Nu sim_ticks 560955232000 # Number of ticks simulated final_tick 560955232000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340981 # Simulator instruction rate (inst/s) -host_op_rate 340981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 205940379 # Simulator tick rate (ticks/s) -host_mem_usage 308844 # Number of bytes of host memory used -host_seconds 2723.87 # Real time elapsed on the host +host_inst_rate 326346 # Simulator instruction rate (inst/s) +host_op_rate 326346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197101410 # Simulator tick rate (ticks/s) +host_mem_usage 309500 # Number of bytes of host memory used +host_seconds 2846.02 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18704768 # To system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 191173 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18033 # Per bank write bursts system.physmem.perBankRdBursts::1 18359 # Per bank write bursts system.physmem.perBankRdBursts::2 18394 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 560955208000 # Total gap between requests +system.physmem.totGap 560955150000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -248,7 +248,7 @@ system.physmem.readRowHits 202530 # Nu system.physmem.writeRowHits 52011 # Number of row buffer hits during writes system.physmem.readRowHitRate 69.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate 78.00 # Row buffer hit rate for writes -system.physmem.avgGap 1562788.75 # Average gap between requests +system.physmem.avgGap 1562788.59 # Average gap between requests system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 392416920 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 214116375 # Energy for precharge commands per rank (pJ) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index a16b516f4..72a187780 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.276414 # Nu sim_ticks 276414065500 # Number of ticks simulated final_tick 276414065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180346 # Simulator instruction rate (inst/s) -host_op_rate 180346 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59177560 # Simulator tick rate (ticks/s) -host_mem_usage 308352 # Number of bytes of host memory used -host_seconds 4670.93 # Real time elapsed on the host +host_inst_rate 168860 # Simulator instruction rate (inst/s) +host_op_rate 168860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55408638 # Simulator tick rate (ticks/s) +host_mem_usage 309496 # Number of bytes of host memory used +host_seconds 4988.65 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18696320 # To system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 191079 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18006 # Per bank write bursts system.physmem.perBankRdBursts::1 18321 # Per bank write bursts system.physmem.perBankRdBursts::2 18379 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 276414034500 # Total gap between requests +system.physmem.totGap 276413976000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -247,7 +247,7 @@ system.physmem.readRowHits 207034 # Nu system.physmem.writeRowHits 52000 # Number of row buffer hits during writes system.physmem.readRowHitRate 70.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes -system.physmem.avgGap 770356.80 # Average gap between requests +system.physmem.avgGap 770356.64 # Average gap between requests system.physmem.pageHitRate 72.26 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 374197320 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 204175125 # Energy for precharge commands per rank (pJ) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index c95abda26..5f2d8e18a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.542265 # Nu sim_ticks 542265386500 # Number of ticks simulated final_tick 542265386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179877 # Simulator instruction rate (inst/s) -host_op_rate 221452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152251725 # Simulator tick rate (ticks/s) -host_mem_usage 325476 # Number of bytes of host memory used -host_seconds 3561.64 # Real time elapsed on the host +host_inst_rate 173269 # Simulator instruction rate (inst/s) +host_op_rate 213317 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 146659072 # Simulator tick rate (ticks/s) +host_mem_usage 328008 # Number of bytes of host memory used +host_seconds 3697.46 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18637888 # To system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 190686 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18283 # Per bank write bursts system.physmem.perBankRdBursts::1 18129 # Per bank write bursts system.physmem.perBankRdBursts::2 18220 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 542265360500 # Total gap between requests +system.physmem.totGap 542265292000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -243,7 +243,7 @@ system.physmem.readRowHits 194203 # Nu system.physmem.writeRowHits 51643 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes -system.physmem.avgGap 1517611.52 # Average gap between requests +system.physmem.avgGap 1517611.33 # Average gap between requests system.physmem.pageHitRate 68.86 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 420789600 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 229597500 # Energy for precharge commands per rank (pJ) @@ -818,18 +818,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 154791 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 22257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 23591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882361 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 25343 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 713113 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2414134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3046336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343209 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2417485 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3131712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 58798528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 58883904 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 258813 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1066591 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.005113 # Request fanout histogram diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 9a207ffb1..9b1e23041 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.452586 # Number of seconds simulated -sim_ticks 452585997000 # Number of ticks simulated -final_tick 452585997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.452564 # Number of seconds simulated +sim_ticks 452563515000 # Number of ticks simulated +final_tick 452563515000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89374 # Simulator instruction rate (inst/s) -host_op_rate 110031 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63138171 # Simulator tick rate (ticks/s) -host_mem_usage 323296 # Number of bytes of host memory used -host_seconds 7168.18 # Real time elapsed on the host +host_inst_rate 88595 # Simulator instruction rate (inst/s) +host_op_rate 109072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62584453 # Simulator tick rate (ticks/s) +host_mem_usage 324544 # Number of bytes of host memory used +host_seconds 7231.25 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 234368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47997568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12828032 # Number of bytes read from this memory -system.physmem.bytes_read::total 61059968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 234368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 234368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4243520 # Number of bytes written to this memory -system.physmem.bytes_written::total 4243520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 749962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 954062 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66305 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66305 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 106051818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 28343855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134913516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9376163 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9376163 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9376163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 106051818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 28343855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 144289678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 954063 # Number of read requests accepted -system.physmem.writeReqs 66305 # Number of write requests accepted -system.physmem.readBursts 954063 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66305 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61041664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18368 # Total number of bytes read from write queue +system.physmem.bytes_read::cpu.inst 234304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48000768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12823616 # Number of bytes read from this memory +system.physmem.bytes_read::total 61058688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 234304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 234304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4243456 # Number of bytes written to this memory +system.physmem.bytes_written::total 4243456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 200369 # Number of read requests responded to by this memory +system.physmem.num_reads::total 954042 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 106064158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 28335506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134917389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517726 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517726 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9376487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9376487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9376487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 106064158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 28335506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 144293877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 954043 # Number of read requests accepted +system.physmem.writeReqs 66304 # Number of write requests accepted +system.physmem.readBursts 954043 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61040512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61060032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4243520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 287 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 227627 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19636 # Per bank write bursts -system.physmem.perBankRdBursts::1 19225 # Per bank write bursts -system.physmem.perBankRdBursts::2 656809 # Per bank write bursts -system.physmem.perBankRdBursts::3 20104 # Per bank write bursts -system.physmem.perBankRdBursts::4 19566 # Per bank write bursts -system.physmem.perBankRdBursts::5 20746 # Per bank write bursts -system.physmem.perBankRdBursts::6 19449 # Per bank write bursts -system.physmem.perBankRdBursts::7 19830 # Per bank write bursts -system.physmem.perBankRdBursts::8 19282 # Per bank write bursts -system.physmem.perBankRdBursts::9 19792 # Per bank write bursts -system.physmem.perBankRdBursts::10 19287 # Per bank write bursts -system.physmem.perBankRdBursts::11 19476 # Per bank write bursts -system.physmem.perBankRdBursts::12 19427 # Per bank write bursts -system.physmem.perBankRdBursts::13 20933 # Per bank write bursts -system.physmem.perBankRdBursts::14 19357 # Per bank write bursts -system.physmem.perBankRdBursts::15 20857 # Per bank write bursts +system.physmem.bytesReadSys 61058752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4243456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 53 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19632 # Per bank write bursts +system.physmem.perBankRdBursts::1 19241 # Per bank write bursts +system.physmem.perBankRdBursts::2 656774 # Per bank write bursts +system.physmem.perBankRdBursts::3 20103 # Per bank write bursts +system.physmem.perBankRdBursts::4 19565 # Per bank write bursts +system.physmem.perBankRdBursts::5 20788 # Per bank write bursts +system.physmem.perBankRdBursts::6 19429 # Per bank write bursts +system.physmem.perBankRdBursts::7 19781 # Per bank write bursts +system.physmem.perBankRdBursts::8 19292 # Per bank write bursts +system.physmem.perBankRdBursts::9 19805 # Per bank write bursts +system.physmem.perBankRdBursts::10 19337 # Per bank write bursts +system.physmem.perBankRdBursts::11 19452 # Per bank write bursts +system.physmem.perBankRdBursts::12 19407 # Per bank write bursts +system.physmem.perBankRdBursts::13 20952 # Per bank write bursts +system.physmem.perBankRdBursts::14 19359 # Per bank write bursts +system.physmem.perBankRdBursts::15 20841 # Per bank write bursts system.physmem.perBankWrBursts::0 4254 # Per bank write bursts -system.physmem.perBankWrBursts::1 4108 # Per bank write bursts +system.physmem.perBankWrBursts::1 4107 # Per bank write bursts system.physmem.perBankWrBursts::2 4140 # Per bank write bursts system.physmem.perBankWrBursts::3 4154 # Per bank write bursts system.physmem.perBankWrBursts::4 4243 # Per bank write bursts system.physmem.perBankWrBursts::5 4230 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::7 4093 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts @@ -83,27 +83,27 @@ system.physmem.perBankWrBursts::11 4097 # Pe system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4153 # Per bank write bursts +system.physmem.perBankWrBursts::15 4155 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 452585986500 # Total gap between requests +system.physmem.totGap 452563504500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 954063 # Read request sizes (log2) +system.physmem.readPktSize::6 954043 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66305 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 760072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14330 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 760089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14329 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see @@ -150,15 +150,15 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4997 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see @@ -197,30 +197,32 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 205647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.429381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.568290 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 286.974442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59802 29.08% 29.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 62661 30.47% 59.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15924 7.74% 67.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3207 1.56% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3374 1.64% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48035 23.36% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7705 3.75% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 205577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.529062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.622998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.021434 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59787 29.08% 29.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62582 30.44% 59.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15931 7.75% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3214 1.56% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3392 1.65% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 47997 23.35% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7735 3.76% 97.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 205647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 205577 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 234.045421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.559432 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3989.674296 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4017 99.70% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-16383 7 0.17% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-32767 2 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::90112-98303 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::212992-221183 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 209.250931 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.553257 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2756.803776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 4005 99.40% 99.40% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 2 0.05% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::61440-65535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::94208-98303 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::114688-118783 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads @@ -242,65 +244,65 @@ system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Wr system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads -system.physmem.totQLat 15106541272 # Total ticks spent queuing -system.physmem.totMemAccLat 32989841272 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4768880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15838.67 # Average queueing delay per DRAM burst +system.physmem.totQLat 15078460254 # Total ticks spent queuing +system.physmem.totMemAccLat 32961422754 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4768790000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15809.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34588.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 9.36 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.91 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34559.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 9.37 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.92 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.13 # Data bus utilization in percentage system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 788463 # Number of row buffer hits during reads -system.physmem.writeRowHits 25883 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 788510 # Number of row buffer hits during reads +system.physmem.writeRowHits 25885 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes -system.physmem.avgGap 443551.72 # Average gap between requests +system.physmem.avgGap 443538.82 # Average gap between requests system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1032091200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 563145000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6203792400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216412560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 305512170480 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3557164500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 346645334700 # Total energy per rank (pJ) -system.physmem_0.averagePower 765.925147 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4194914578 # Time in different power states -system.physmem_0.memoryStateTime::REF 15112760000 # Time in different power states +system.physmem_0.actEnergy 1031660280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 562909875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6203308800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216399600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305467849845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3582027000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 346623188280 # Total energy per rank (pJ) +system.physmem_0.averagePower 765.915744 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4235605578 # Time in different power states +system.physmem_0.memoryStateTime::REF 15111980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 433276166672 # Time in different power states +system.physmem_0.memoryStateTime::ACT 433212896922 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 522539640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 285115875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1235348400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96876011835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 186571355250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 315263655000 # Total energy per rank (pJ) -system.physmem_1.averagePower 696.586172 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 309737229647 # Time in different power states -system.physmem_1.memoryStateTime::REF 15112760000 # Time in different power states +system.physmem_1.actEnergy 522411120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 285045750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1235535600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212738400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96975747585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 186469836000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 315260347335 # Total energy per rank (pJ) +system.physmem_1.averagePower 696.614859 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 309568131397 # Time in different power states +system.physmem_1.memoryStateTime::REF 15111980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127733879103 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127880371103 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234612390 # Number of BP lookups -system.cpu.branchPred.condPredicted 162472835 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514556 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121579993 # Number of BTB lookups -system.cpu.branchPred.BTBHits 107625887 # Number of BTB hits +system.cpu.branchPred.lookups 234612924 # Number of BP lookups +system.cpu.branchPred.condPredicted 162473080 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514448 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121580360 # Number of BTB lookups +system.cpu.branchPred.BTBHits 107626063 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.522696 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25035644 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300133 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.522573 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25035646 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300027 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -419,84 +421,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 905171995 # number of cpu cycles simulated +system.cpu.numCycles 905127031 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 86003110 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1202048869 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234612390 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 132661531 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 803279049 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064713 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1868 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85998683 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1202051079 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234612924 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 132661709 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 803240111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064493 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1917 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3204 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370083974 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652982 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 904819618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.657214 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3269 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370084311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652880 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 904776257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.657297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222849160 24.63% 24.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 224059075 24.76% 49.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98313082 10.87% 60.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 359598301 39.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222804793 24.63% 24.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 224059137 24.76% 49.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98313262 10.87% 60.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 359599065 39.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 904819618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259191 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.327978 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121904104 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 244100755 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484657410 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38638668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518681 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24546049 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13811 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248144086 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39968857 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518681 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178914873 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 163328471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207028 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319861 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82530704 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190654266 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 24276153 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24946873 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2269725 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41528835 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1707155 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1226040359 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5813734095 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358184137 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876447 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 904776257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259204 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.328047 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121900634 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 244061321 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484657119 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38638613 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518570 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24546046 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13813 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248144936 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39968729 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518570 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178911503 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 163289745 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 206869 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464319515 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82530055 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190655236 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 24276259 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24947259 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2269584 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41529012 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1706231 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1226042317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5813738555 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358185798 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876436 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 351262129 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 351264087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7264 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108789591 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 367388897 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236094901 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1672944 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5307285 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1169836169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12331 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017123135 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19093941 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 381123542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1038508983 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 177 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 904819618 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.124117 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093910 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108789745 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 367388846 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236095095 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1811043 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5312656 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1169837126 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12332 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017086167 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18990404 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 381124500 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1038523748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 904776257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.124130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.093860 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 347160042 38.37% 38.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227103662 25.10% 63.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217769500 24.07% 87.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96665190 10.68% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16121217 1.78% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 347117204 38.36% 38.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227104713 25.10% 63.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217802755 24.07% 87.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96630403 10.68% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16121175 1.78% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -504,9 +506,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 904819618 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 904776257 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63881232 18.86% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63882217 18.87% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available @@ -535,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 158064095 46.67% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116064822 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 158029640 46.67% 65.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116058922 34.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456367780 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456367665 44.87% 44.87% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued @@ -565,86 +567,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478995 1.13% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322109040 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215596292 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322074351 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215594127 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017123135 # Type of FU issued -system.cpu.iq.rate 1.123679 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338665181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332964 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3234948583 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1507425320 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934275773 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61876427 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565693 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 1017086167 # Type of FU issued +system.cpu.iq.rate 1.123694 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338625811 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3234688378 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1507427240 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934273902 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61876428 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565689 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321978571 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1321902233 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9959468 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 9959480 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 115147959 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 115147908 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107114405 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 107114599 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065764 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19863 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065775 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19869 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518681 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35329232 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 27153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1169854056 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518570 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35329075 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 27772 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1169855013 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 367388897 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236094901 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6591 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29598 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 367388846 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236095095 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6592 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 88 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30218 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437212 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784515 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221727 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974753111 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303296723 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42370024 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 15437101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784620 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221721 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974751329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303296690 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42334838 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497769972 # number of memory reference insts executed -system.cpu.iew.exec_branches 150611064 # Number of branches executed -system.cpu.iew.exec_stores 194473249 # Number of stores executed -system.cpu.iew.exec_rate 1.076871 # Inst execution rate -system.cpu.iew.wb_sent 963726707 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960428223 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536045857 # num instructions producing a value -system.cpu.iew.wb_consumers 893287669 # num instructions consuming a value -system.cpu.iew.wb_rate 1.061045 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600082 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 357425551 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 5555 # number of nop insts executed +system.cpu.iew.exec_refs 497768330 # number of memory reference insts executed +system.cpu.iew.exec_branches 150610966 # Number of branches executed +system.cpu.iew.exec_stores 194471640 # Number of stores executed +system.cpu.iew.exec_rate 1.076922 # Inst execution rate +system.cpu.iew.wb_sent 963724922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960426352 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536046741 # num instructions producing a value +system.cpu.iew.wb_consumers 893290325 # num instructions consuming a value +system.cpu.iew.wb_rate 1.061096 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600081 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 357426439 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 853996264 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.923576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.715161 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500772 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 853952830 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.923623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.715196 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 515355287 60.35% 60.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174404345 20.42% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72937486 8.54% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32899801 3.85% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8539084 1.00% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14259189 1.67% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7267219 0.85% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5975069 0.70% 97.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22358784 2.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 515313788 60.34% 60.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174402011 20.42% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72937800 8.54% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32899590 3.85% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8538808 1.00% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14259214 1.67% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7267758 0.85% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5975049 0.70% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22358812 2.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 853996264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 853952830 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -690,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22358784 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1977784350 # The number of ROB reads -system.cpu.rob.rob_writes 2343138350 # The number of ROB writes -system.cpu.timesIdled 648611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 352377 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22358812 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1977741776 # The number of ROB reads +system.cpu.rob.rob_writes 2343140199 # The number of ROB writes +system.cpu.timesIdled 648615 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 350774 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.412898 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.412898 # CPI: Total CPI of All Threads -system.cpu.ipc 0.707765 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.707765 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995811618 # number of integer regfile reads -system.cpu.int_regfile_writes 567906414 # number of integer regfile writes +system.cpu.cpi 1.412828 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.412828 # CPI: Total CPI of All Threads +system.cpu.ipc 0.707800 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.707800 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995808117 # number of integer regfile reads +system.cpu.int_regfile_writes 567906123 # number of integer regfile writes system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794441379 # number of cc regfile reads -system.cpu.cc_regfile_writes 384896518 # number of cc regfile writes -system.cpu.misc_regfile_reads 715823215 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794435958 # number of cc regfile reads +system.cpu.cc_regfile_writes 384896498 # number of cc regfile writes +system.cpu.misc_regfile_reads 715821566 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756185 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.937157 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216587 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258294 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2756183 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.937153 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216547 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756695 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258388 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.937157 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.937153 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347973 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347973 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906811 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906811 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839347867 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347867 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286293756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286293756 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906808 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906808 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414200611 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414200611 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414203768 # number of overall hits -system.cpu.dcache.overall_hits::total 414203768 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3035079 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3035079 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044666 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414200564 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414200564 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414203721 # number of overall hits +system.cpu.dcache.overall_hits::total 414203721 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3035071 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3035071 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044669 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4079745 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4079745 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4080391 # number of overall misses -system.cpu.dcache.overall_misses::total 4080391 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76869214000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76869214000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10006334850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10006334850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4079740 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4079740 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4080386 # number of overall misses +system.cpu.dcache.overall_misses::total 4080386 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76845731000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76845731000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10002174850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10002174850 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86875548850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86875548850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86875548850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86875548850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 86847905850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86847905850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86847905850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86847905850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328827 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -772,10 +774,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418280356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418280356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418284159 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418284159 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 418280304 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418280304 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418284107 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418284107 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses @@ -788,56 +790,56 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25326.923615 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25326.923615 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9578.501502 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9578.501502 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25319.253158 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25319.253158 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.491873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.491873 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21294.357576 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21294.357576 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21290.986293 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21290.986293 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21287.607997 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21287.607997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21284.237778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21284.237778 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 352038 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 351058 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4878 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4882 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.168512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.908644 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2756185 # number of writebacks -system.cpu.dcache.writebacks::total 2756185 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323643 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323643 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2756183 # number of writebacks +system.cpu.dcache.writebacks::total 2756183 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999866 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999866 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323646 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323646 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1323515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1323515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1323515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1323515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035207 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035207 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1323512 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1323512 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1323512 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1323512 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035205 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035205 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721023 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 721023 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756230 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756230 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756871 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756871 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65569114500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 65569114500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5957184350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5957184350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5576500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5576500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71526298850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 71526298850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71531875350 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 71531875350 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756228 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756228 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756869 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756869 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65547149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 65547149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5956550350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5956550350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5499000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5499000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71503699350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 71503699350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71509198350 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 71509198350 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses @@ -848,229 +850,229 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32217.417933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32217.417933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8262.128046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8262.128046 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8699.687988 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8699.687988 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25950.772922 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25950.772922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25946.761872 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25946.761872 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32206.656823 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32206.656823 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8261.248740 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8261.248740 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8578.783151 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8578.783151 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25942.592322 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25942.592322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25938.555060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25938.555060 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169363 # number of replacements -system.cpu.icache.tags.tagsinuse 510.872217 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 364909729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169873 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.583886 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5169029 # number of replacements +system.cpu.icache.tags.tagsinuse 510.720775 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 364910405 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169539 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.588578 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.872217 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997797 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.720775 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997502 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997502 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745337941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745337941 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364909744 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364909744 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364909744 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364909744 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364909744 # number of overall hits -system.cpu.icache.overall_hits::total 364909744 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174203 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174203 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174203 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174203 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174203 # number of overall misses -system.cpu.icache.overall_misses::total 5174203 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41972246420 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41972246420 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41972246420 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41972246420 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41972246420 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41972246420 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370083947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370083947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370083947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370083947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370083947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370083947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013981 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013981 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013981 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013981 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013981 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013981 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.828318 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8111.828318 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8111.828318 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8111.828318 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 80154 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 745338281 # Number of tag accesses +system.cpu.icache.tags.data_accesses 745338281 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 364910416 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 364910416 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 364910416 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 364910416 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 364910416 # number of overall hits +system.cpu.icache.overall_hits::total 364910416 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5173868 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5173868 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5173868 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5173868 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5173868 # number of overall misses +system.cpu.icache.overall_misses::total 5173868 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41967552420 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41967552420 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41967552420 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41967552420 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41967552420 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41967552420 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370084284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370084284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370084284 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370084284 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370084284 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370084284 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013980 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013980 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013980 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013980 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013980 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013980 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.446295 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8111.446295 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8111.446295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8111.446295 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 79493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3667 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3635 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.858195 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.868776 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 5169363 # number of writebacks -system.cpu.icache.writebacks::total 5169363 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4154 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4154 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4154 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4154 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4154 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4154 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170049 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5170049 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5170049 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5170049 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5170049 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5170049 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39346514434 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39346514434 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39346514434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39346514434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39346514434 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39346514434 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.472248 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.472248 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 5169029 # number of writebacks +system.cpu.icache.writebacks::total 5169029 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169715 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5169715 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5169715 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5169715 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5169715 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5169715 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39342077434 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39342077434 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39342077434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39342077434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39342077434 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39342077434 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013969 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013969 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013969 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.105670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.105670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.105670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.105670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.105670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.105670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350388 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355069 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350427 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355108 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 4095 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790235 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 301561 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16356.089687 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13502376 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 317924 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 42.470452 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4790132 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 301513 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16356.090183 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13598662 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 317875 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 42.779904 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 60356537500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9847.960617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6508.129070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.601072 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397225 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998296 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6319 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 10044 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4867 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7658 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.385681 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.613037 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 244381666 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 244381666 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 9848.276079 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6507.814104 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.601091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6290 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 10072 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4827 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1956 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7712 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.383911 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.614746 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 244370866 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 244370866 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 735261 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 246204000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 246204000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49598643500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49598643500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246204000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49732310000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 49978514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246204000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49732310000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16513318471 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66491832471 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367707 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367707 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.095076 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000708 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367734 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367734 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.095086 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.120374 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82372.666141 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17204.022989 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17204.022989 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97926.061493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97926.061493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67728.091728 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67728.091728 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66284.957440 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66284.957440 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66349.323603 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69716.843102 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120377 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82377.535910 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14097.701149 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14097.701149 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 98139.867841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 98139.867841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67232.113599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67232.113599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66250.776064 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66250.776064 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66313.172539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69688.222157 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 15852468 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 15851796 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925416 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 760150 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116849 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7205895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801566 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6546111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 987513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243924 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 760180 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116881 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7205559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 7189951 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 987519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 243847 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170049 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035848 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23135037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661654912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311653440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 973308352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1297915 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9224662 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.222014 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.558747 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035846 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8269921 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23778205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661668416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352824192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1014492608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1297843 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9224254 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.222027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.558758 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7819958 84.77% 84.77% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 761403 8.25% 93.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 643301 6.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7819520 84.77% 84.77% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 761435 8.25% 93.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 643299 6.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9224662 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15851782000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9224254 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15851110000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755313513 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7754813511 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135165933 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135160937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 952696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66305 # Transaction distribution -system.membus.trans_dist::CleanEvict 227453 # Transaction distribution +system.membus.trans_dist::ReadResp 952680 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66304 # Transaction distribution +system.membus.trans_dist::CleanEvict 227429 # Transaction distribution system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 1366 # Transaction distribution -system.membus.trans_dist::ReadExResp 1366 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 952697 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2202231 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2202231 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65303488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65303488 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 1362 # Transaction distribution +system.membus.trans_dist::ReadExResp 1362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 952681 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2201992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2201992 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65302144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65302144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1247995 # Request fanout histogram +system.membus.snoop_fanout::samples 1247950 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1247995 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1247950 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1247995 # Request fanout histogram -system.membus.reqLayer0.occupancy 1752388071 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1247950 # Request fanout histogram +system.membus.reqLayer0.occupancy 1752348040 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 5021031104 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5020538027 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index dd5f11d63..92b150303 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.045756 # Nu sim_ticks 1045756396500 # Number of ticks simulated final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734670 # Simulator instruction rate (inst/s) -host_op_rate 902587 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1201635964 # Simulator tick rate (ticks/s) -host_mem_usage 323928 # Number of bytes of host memory used -host_seconds 870.28 # Real time elapsed on the host +host_inst_rate 725560 # Simulator instruction rate (inst/s) +host_op_rate 891395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1186735876 # Simulator tick rate (ticks/s) +host_mem_usage 325196 # Number of bytes of host memory used +host_seconds 881.20 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -609,18 +609,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 8752 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1213440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56966208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 257772 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index e086bc978..2126b1202 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.059474 # Nu sim_ticks 59473862000 # Number of ticks simulated final_tick 59473862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 342067 # Simulator instruction rate (inst/s) -host_op_rate 342067 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230037089 # Simulator tick rate (ticks/s) -host_mem_usage 307480 # Number of bytes of host memory used -host_seconds 258.54 # Real time elapsed on the host +host_inst_rate 330532 # Simulator instruction rate (inst/s) +host_op_rate 330532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 222279677 # Simulator tick rate (ticks/s) +host_mem_usage 308876 # Number of bytes of host memory used +host_seconds 267.56 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 10581824 # To system.physmem.bytesWrittenSys 7325760 # Total written bytes from the system interface side system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14983 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10312 # Per bank write bursts system.physmem.perBankRdBursts::1 10359 # Per bank write bursts system.physmem.perBankRdBursts::2 10206 # Per bank write bursts diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index ead89988f..5beee1623 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022297 # Nu sim_ticks 22296591500 # Number of ticks simulated final_tick 22296591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221726 # Simulator instruction rate (inst/s) -host_op_rate 221726 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62113736 # Simulator tick rate (ticks/s) -host_mem_usage 308500 # Number of bytes of host memory used -host_seconds 358.96 # Real time elapsed on the host +host_inst_rate 210659 # Simulator instruction rate (inst/s) +host_op_rate 210659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59013272 # Simulator tick rate (ticks/s) +host_mem_usage 309644 # Number of bytes of host memory used +host_seconds 377.82 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 10563200 # To system.physmem.bytesWrittenSys 7322432 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14730 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10292 # Per bank write bursts system.physmem.perBankRdBursts::1 10329 # Per bank write bursts system.physmem.perBankRdBursts::2 10209 # Per bank write bursts diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c1732fe78..6fa7b21e8 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.056961 # Nu sim_ticks 56960656500 # Number of ticks simulated final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199606 # Simulator instruction rate (inst/s) -host_op_rate 255266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 160327771 # Simulator tick rate (ticks/s) -host_mem_usage 325784 # Number of bytes of host memory used -host_seconds 355.28 # Real time elapsed on the host +host_inst_rate 189048 # Simulator instruction rate (inst/s) +host_op_rate 241764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 151847358 # Simulator tick rate (ticks/s) +host_mem_usage 327812 # Number of bytes of host memory used +host_seconds 375.12 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 8209792 # To system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6908 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8061 # Per bank write bursts system.physmem.perBankRdBursts::1 8314 # Per bank write bursts system.physmem.perBankRdBursts::2 8233 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 5703 # Pe system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56960630500 # Total gap between requests +system.physmem.totGap 56960624500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -247,7 +247,7 @@ system.physmem.readRowHits 111810 # Nu system.physmem.writeRowHits 63793 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 265564.34 # Average gap between requests +system.physmem.avgGap 265564.32 # Average gap between requests system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ) @@ -825,18 +825,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 39288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 42868 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38234 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473266 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 602375 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5388672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132689 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 610189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5617792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 23878848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24107968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 96386 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index b6f1be7c5..56872871d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033788 # Number of seconds simulated -sim_ticks 33787619000 # Number of ticks simulated -final_tick 33787619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033784 # Number of seconds simulated +sim_ticks 33784139000 # Number of ticks simulated +final_tick 33784139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117892 # Simulator instruction rate (inst/s) -host_op_rate 150770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56175899 # Simulator tick rate (ticks/s) -host_mem_usage 326928 # Number of bytes of host memory used -host_seconds 601.46 # Real time elapsed on the host +host_inst_rate 118438 # Simulator instruction rate (inst/s) +host_op_rate 151468 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56430150 # Simulator tick rate (ticks/s) +host_mem_usage 329476 # Number of bytes of host memory used +host_seconds 598.69 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 736896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2854400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6176576 # Number of bytes read from this memory -system.physmem.bytes_read::total 9767872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 736896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 736896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6229632 # Number of bytes written to this memory -system.physmem.bytes_written::total 6229632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 11514 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 44600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96509 # Number of read requests responded to by this memory -system.physmem.num_reads::total 152623 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97338 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21809646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 84480650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 182805897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 289096192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21809646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21809646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 184376176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 184376176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 184376176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21809646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 84480650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 182805897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 473472369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 152624 # Number of read requests accepted -system.physmem.writeReqs 97338 # Number of write requests accepted -system.physmem.readBursts 152624 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97338 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9758080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6227712 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9767936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6229632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 27837 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9027 # Per bank write bursts -system.physmem.perBankRdBursts::1 9355 # Per bank write bursts -system.physmem.perBankRdBursts::2 9548 # Per bank write bursts -system.physmem.perBankRdBursts::3 12185 # Per bank write bursts -system.physmem.perBankRdBursts::4 10599 # Per bank write bursts -system.physmem.perBankRdBursts::5 10432 # Per bank write bursts -system.physmem.perBankRdBursts::6 9787 # Per bank write bursts -system.physmem.perBankRdBursts::7 9285 # Per bank write bursts -system.physmem.perBankRdBursts::8 9499 # Per bank write bursts -system.physmem.perBankRdBursts::9 9569 # Per bank write bursts -system.physmem.perBankRdBursts::10 9134 # Per bank write bursts -system.physmem.perBankRdBursts::11 8776 # Per bank write bursts -system.physmem.perBankRdBursts::12 8706 # Per bank write bursts -system.physmem.perBankRdBursts::13 8772 # Per bank write bursts -system.physmem.perBankRdBursts::14 8686 # Per bank write bursts -system.physmem.perBankRdBursts::15 9110 # Per bank write bursts -system.physmem.perBankWrBursts::0 5979 # Per bank write bursts -system.physmem.perBankWrBursts::1 6226 # Per bank write bursts -system.physmem.perBankWrBursts::2 6146 # Per bank write bursts -system.physmem.perBankWrBursts::3 6158 # Per bank write bursts -system.physmem.perBankWrBursts::4 6081 # Per bank write bursts -system.physmem.perBankWrBursts::5 6325 # Per bank write bursts -system.physmem.perBankWrBursts::6 6021 # Per bank write bursts -system.physmem.perBankWrBursts::7 5966 # Per bank write bursts -system.physmem.perBankWrBursts::8 5954 # Per bank write bursts -system.physmem.perBankWrBursts::9 6102 # Per bank write bursts -system.physmem.perBankWrBursts::10 6248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5872 # Per bank write bursts -system.physmem.perBankWrBursts::12 6030 # Per bank write bursts -system.physmem.perBankWrBursts::13 6061 # Per bank write bursts -system.physmem.perBankWrBursts::14 6151 # Per bank write bursts -system.physmem.perBankWrBursts::15 5988 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 781248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2836288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6167232 # Number of bytes read from this memory +system.physmem.bytes_read::total 9784768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 781248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 781248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6226432 # Number of bytes written to this memory +system.physmem.bytes_written::total 6226432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 12207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 44317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96363 # Number of read requests responded to by this memory +system.physmem.num_reads::total 152887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97288 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97288 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 23124698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 83953242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 182548148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 289626088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 23124698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 23124698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 184300449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 184300449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 184300449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 23124698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 83953242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 182548148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 473926537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 152888 # Number of read requests accepted +system.physmem.writeReqs 97288 # Number of write requests accepted +system.physmem.readBursts 152888 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97288 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9777152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 6224960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9784832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6226432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9124 # Per bank write bursts +system.physmem.perBankRdBursts::1 9348 # Per bank write bursts +system.physmem.perBankRdBursts::2 9757 # Per bank write bursts +system.physmem.perBankRdBursts::3 12566 # Per bank write bursts +system.physmem.perBankRdBursts::4 10929 # Per bank write bursts +system.physmem.perBankRdBursts::5 10090 # Per bank write bursts +system.physmem.perBankRdBursts::6 9786 # Per bank write bursts +system.physmem.perBankRdBursts::7 8974 # Per bank write bursts +system.physmem.perBankRdBursts::8 9178 # Per bank write bursts +system.physmem.perBankRdBursts::9 9832 # Per bank write bursts +system.physmem.perBankRdBursts::10 9165 # Per bank write bursts +system.physmem.perBankRdBursts::11 8819 # Per bank write bursts +system.physmem.perBankRdBursts::12 8693 # Per bank write bursts +system.physmem.perBankRdBursts::13 8672 # Per bank write bursts +system.physmem.perBankRdBursts::14 8813 # Per bank write bursts +system.physmem.perBankRdBursts::15 9022 # Per bank write bursts +system.physmem.perBankWrBursts::0 5950 # Per bank write bursts +system.physmem.perBankWrBursts::1 6192 # Per bank write bursts +system.physmem.perBankWrBursts::2 6162 # Per bank write bursts +system.physmem.perBankWrBursts::3 6171 # Per bank write bursts +system.physmem.perBankWrBursts::4 6089 # Per bank write bursts +system.physmem.perBankWrBursts::5 6262 # Per bank write bursts +system.physmem.perBankWrBursts::6 6013 # Per bank write bursts +system.physmem.perBankWrBursts::7 5971 # Per bank write bursts +system.physmem.perBankWrBursts::8 5978 # Per bank write bursts +system.physmem.perBankWrBursts::9 6080 # Per bank write bursts +system.physmem.perBankWrBursts::10 6215 # Per bank write bursts +system.physmem.perBankWrBursts::11 5915 # Per bank write bursts +system.physmem.perBankWrBursts::12 6050 # Per bank write bursts +system.physmem.perBankWrBursts::13 6057 # Per bank write bursts +system.physmem.perBankWrBursts::14 6142 # Per bank write bursts +system.physmem.perBankWrBursts::15 6018 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33787609500 # Total gap between requests +system.physmem.totGap 33784127500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152624 # Read request sizes (log2) +system.physmem.readPktSize::6 152888 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97338 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97288 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 50168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 39 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,103 +197,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95484 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 167.396422 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 105.401782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 235.895158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59753 62.58% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22097 23.14% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4150 4.35% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1579 1.65% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 956 1.00% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 842 0.88% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 589 0.62% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 882 0.92% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4636 4.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95484 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5850 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.058462 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.495488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5849 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 95539 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 167.474225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 105.587098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 235.887781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59486 62.26% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22475 23.52% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4141 4.33% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1560 1.63% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 915 0.96% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 855 0.89% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 603 0.63% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 793 0.83% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4711 4.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95539 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5851 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.107332 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.473486 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5850 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5850 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5850 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.633846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.583273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.382653 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4554 77.85% 77.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 25 0.43% 78.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 781 13.35% 91.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 204 3.49% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 105 1.79% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 84 1.44% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 47 0.80% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 32 0.55% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.14% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5850 # Writes before turning the bus around for reads -system.physmem.totQLat 6712073801 # Total ticks spent queuing -system.physmem.totMemAccLat 9570886301 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 762350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44022.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5851 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5851 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.623654 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.576655 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.320793 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4551 77.78% 77.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.51% 78.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 752 12.85% 91.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 225 3.85% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 138 2.36% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 80 1.37% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 45 0.77% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.38% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5851 # Writes before turning the bus around for reads +system.physmem.totQLat 6694958033 # Total ticks spent queuing +system.physmem.totMemAccLat 9559358033 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 763840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43824.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62772.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 288.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 184.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 289.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 184.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62574.35 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 289.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 184.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 289.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 184.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.70 # Data bus utilization in percentage system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 121004 # Number of row buffer hits during reads -system.physmem.writeRowHits 33280 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.19 # Row buffer hit rate for writes -system.physmem.avgGap 135170.98 # Average gap between requests -system.physmem.pageHitRate 61.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 375641280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204963000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 625404000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 316826640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15342350850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6812703000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25884530610 # Total energy per rank (pJ) -system.physmem_0.averagePower 766.158096 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11227638574 # Time in different power states -system.physmem_0.memoryStateTime::REF 1128140000 # Time in different power states +system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 121417 # Number of row buffer hits during reads +system.physmem.writeRowHits 33065 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.99 # Row buffer hit rate for writes +system.physmem.avgGap 135041.44 # Average gap between requests +system.physmem.pageHitRate 61.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 374855040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204534000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 627829800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 316068480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15176758725 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6953261250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25859440575 # Total energy per rank (pJ) +system.physmem_0.averagePower 765.592889 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11461051997 # Time in different power states +system.physmem_0.memoryStateTime::REF 1127880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21429077176 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21188094253 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 346043880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 188813625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563401800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313625520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13705423425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8248614750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25572564840 # Total energy per rank (pJ) -system.physmem_1.averagePower 756.923807 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13625050098 # Time in different power states -system.physmem_1.memoryStateTime::REF 1128140000 # Time in different power states +system.physmem_1.actEnergy 346777200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189213750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562754400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313787520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13818315060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8144878500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25581859710 # Total energy per rank (pJ) +system.physmem_1.averagePower 757.374848 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13453093141 # Time in different power states +system.physmem_1.memoryStateTime::REF 1127880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19031683152 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19196289859 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17216173 # Number of BP lookups -system.cpu.branchPred.condPredicted 11524251 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 650211 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9349330 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7678783 # Number of BTB hits +system.cpu.branchPred.lookups 17214384 # Number of BP lookups +system.cpu.branchPred.condPredicted 11522342 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 650449 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9351216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7679376 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.131907 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872954 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101563 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.121683 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872997 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,129 +408,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 67575239 # number of cpu cycles simulated +system.cpu.numCycles 67568279 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5134859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88248834 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17216173 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9551737 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60707500 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1326839 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5160872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88245051 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17214384 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9552373 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60651743 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1327287 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6028 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12635 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22778595 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 70008 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66523790 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.678669 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300955 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 12780 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22780660 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66495093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.679326 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300807 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20715769 31.14% 31.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8270385 12.43% 43.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9211836 13.85% 57.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28325800 42.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20690371 31.12% 31.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8267529 12.43% 43.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9212157 13.85% 57.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28325036 42.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 66495093 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.305934 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8696241 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20116868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31576119 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5641245 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 493317 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3182236 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172097 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101426011 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3049995 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 493317 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13462916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5983097 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 839028 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32232549 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13512883 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99220100 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 979828 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3816376 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 66808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4343458 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5148151 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103925700 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457807646 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115438955 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 552 # Number of floating rename lookups +system.cpu.fetch.rate 1.306013 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8713541 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20066003 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31587262 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5634718 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 493569 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3182821 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172049 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101434518 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3052676 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 493569 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13478922 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5884192 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 838725 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32239032 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13560653 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99228097 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 981180 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3845119 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69162 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4384146 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5165586 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103939784 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457840373 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115445962 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10296474 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18669 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 10310558 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18670 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12740509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24326602 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22004719 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1418947 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2350394 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98183255 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94912265 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 694103 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7535192 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20267739 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66523790 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.426742 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.152135 # Number of insts issued each cycle +system.cpu.rename.skidInsts 12730367 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24327975 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22005134 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1415958 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2369050 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98190630 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34517 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94916965 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 695759 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7542562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20296667 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66495093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.427428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18209770 27.37% 27.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17473699 26.27% 53.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17129113 25.75% 79.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11665460 17.54% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2044780 3.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 968 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18174968 27.33% 27.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17486428 26.30% 53.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17117325 25.74% 79.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11670567 17.55% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2044839 3.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 966 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66523790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66495093 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6707680 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 41 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11186120 37.35% 59.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12052780 40.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6711532 22.43% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11180045 37.36% 59.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12034310 40.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49503200 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89866 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49505832 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89861 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -555,89 +551,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24070106 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21249051 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24073706 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21247526 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94912265 # Type of FU issued -system.cpu.iq.rate 1.404542 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29946621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315519 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286988829 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105764420 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93479370 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124858764 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1365617 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94916965 # Type of FU issued +system.cpu.iq.rate 1.404756 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29925928 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315285 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286950501 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105779157 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93480434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124842774 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1366701 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1460340 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2088 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11950 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1448981 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1461713 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2105 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11942 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1449396 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 137954 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185768 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 140491 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185859 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 493317 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 628934 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 513918 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98227667 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 493569 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 630289 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 523749 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98235038 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24326602 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22004719 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1669 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 509191 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11950 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303594 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221648 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 525242 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93991933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23762441 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 920332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24327975 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22005134 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18597 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1652 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 519239 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11942 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303965 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221737 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 525702 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93996105 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23765772 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 920860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9890 # number of nop insts executed -system.cpu.iew.exec_refs 44753885 # number of memory reference insts executed -system.cpu.iew.exec_branches 14253415 # Number of branches executed -system.cpu.iew.exec_stores 20991444 # Number of stores executed -system.cpu.iew.exec_rate 1.390923 # Inst execution rate -system.cpu.iew.wb_sent 93601796 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93479432 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44975266 # num instructions producing a value -system.cpu.iew.wb_consumers 76559860 # num instructions consuming a value -system.cpu.iew.wb_rate 1.383339 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587452 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6553334 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9891 # number of nop insts executed +system.cpu.iew.exec_refs 44755693 # number of memory reference insts executed +system.cpu.iew.exec_branches 14254152 # Number of branches executed +system.cpu.iew.exec_stores 20989921 # Number of stores executed +system.cpu.iew.exec_rate 1.391128 # Inst execution rate +system.cpu.iew.wb_sent 93602702 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93480493 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44980132 # num instructions producing a value +system.cpu.iew.wb_consumers 76556790 # num instructions consuming a value +system.cpu.iew.wb_rate 1.383497 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587539 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6559945 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 480109 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65462437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.385346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157754 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 480375 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65432608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.385978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157554 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31857215 48.66% 48.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16813031 25.68% 74.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4347273 6.64% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4157866 6.35% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935310 2.96% 90.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1259510 1.92% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 744006 1.14% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 581672 0.89% 94.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3766554 5.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31819625 48.63% 48.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16816004 25.70% 74.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4349451 6.65% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4164400 6.36% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1932309 2.95% 90.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1260445 1.93% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 747040 1.14% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580342 0.89% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3762992 5.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65462437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 65432608 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -683,386 +679,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3766554 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158912055 # The number of ROB reads -system.cpu.rob.rob_writes 195546008 # The number of ROB writes -system.cpu.timesIdled 28044 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1051449 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3762992 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158892399 # The number of ROB reads +system.cpu.rob.rob_writes 195560325 # The number of ROB writes +system.cpu.timesIdled 28658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1073186 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.953004 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.953004 # CPI: Total CPI of All Threads -system.cpu.ipc 1.049314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102290506 # number of integer regfile reads -system.cpu.int_regfile_writes 56802248 # number of integer regfile writes -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 24 # number of floating regfile writes -system.cpu.cc_regfile_reads 346154538 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804906 # number of cc regfile writes -system.cpu.misc_regfile_reads 44219892 # number of misc regfile reads +system.cpu.cpi 0.952906 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.952906 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102292430 # number of integer regfile reads +system.cpu.int_regfile_writes 56802415 # number of integer regfile writes +system.cpu.fp_regfile_reads 38 # number of floating regfile reads +system.cpu.fp_regfile_writes 22 # number of floating regfile writes +system.cpu.cc_regfile_reads 346166780 # number of cc regfile reads +system.cpu.cc_regfile_writes 38809001 # number of cc regfile writes +system.cpu.misc_regfile_reads 44218310 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485017 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.752563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40412566 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.234093 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 485025 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.752435 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40412261 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485537 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.232094 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.752563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997564 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 510.752435 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997563 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997563 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 455 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84615901 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84615901 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21489624 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21489624 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831353 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831353 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60282 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60282 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15348 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15348 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84614979 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84614979 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21489272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21489272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831416 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831416 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60267 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60267 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15347 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15347 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40320977 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40320977 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40381259 # number of overall hits -system.cpu.dcache.overall_hits::total 40381259 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 564963 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 564963 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018548 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018548 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68572 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68572 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1583511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1583511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1652083 # number of overall misses -system.cpu.dcache.overall_misses::total 1652083 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9256149500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9256149500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14245975429 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14245975429 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5465000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5465000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23502124929 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23502124929 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23502124929 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23502124929 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054587 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054587 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40320688 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40320688 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40380955 # number of overall hits +system.cpu.dcache.overall_hits::total 40380955 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 564863 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 564863 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018485 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018485 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68573 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68573 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 579 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 579 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1583348 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583348 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1651921 # number of overall misses +system.cpu.dcache.overall_misses::total 1651921 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9285321000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9285321000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14250906929 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14250906929 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5341000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5341000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23536227929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23536227929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23536227929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23536227929 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128854 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128854 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15925 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128840 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128840 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904488 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904488 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033342 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033342 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025617 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025617 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051312 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051312 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532168 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532168 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037789 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037789 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039304 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039304 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16383.638398 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16383.638398 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13986.552847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13986.552847 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9471.403813 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9471.403813 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14841.781919 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14841.781919 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14225.753143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14225.753143 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2896869 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131288 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.466667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.064995 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904036 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42032876 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42032876 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025613 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025613 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051309 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532234 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532234 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036356 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036356 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037785 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037785 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039301 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039301 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16438.182356 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16438.182356 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13992.260003 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13992.260003 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9224.525043 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9224.525043 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14864.848365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14864.848365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14247.792678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14247.792678 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 81 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2899485 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131229 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.094849 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 485017 # number of writebacks -system.cpu.dcache.writebacks::total 485017 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265550 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 265550 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870019 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870019 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135569 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135569 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135569 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135569 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299413 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299413 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148529 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148529 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 485025 # number of writebacks +system.cpu.dcache.writebacks::total 485025 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265446 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 265446 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 869952 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 869952 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 579 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 579 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1135398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135398 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447942 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447942 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485539 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485539 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3625766000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3625766000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2305447971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2305447971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1884857000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1884857000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5931213971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5931213971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816070971 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 447950 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447950 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485547 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485547 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3589129000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3589129000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306203970 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306203970 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1890576000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1890576000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5895332970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5895332970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7785908970 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7785908970 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291780 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291780 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291812 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12109.581080 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12109.581080 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15521.870954 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15521.870954 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50133.175519 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50133.175519 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13241.031140 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13241.031140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16097.720206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16097.720206 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11987.058183 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11987.058183 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15526.542721 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15526.542721 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50285.288720 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50285.288720 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13160.694207 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13160.694207 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16035.335343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16035.335343 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 323105 # number of replacements -system.cpu.icache.tags.tagsinuse 510.281102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22444187 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323617 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.354166 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 323129 # number of replacements +system.cpu.icache.tags.tagsinuse 510.280955 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22445799 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323641 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.354003 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.281102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996643 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996643 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.280955 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996642 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996642 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 341 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 335 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45880575 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45880575 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22444187 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22444187 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22444187 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22444187 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22444187 # number of overall hits -system.cpu.icache.overall_hits::total 22444187 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 334287 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 334287 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 334287 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 334287 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 334287 # number of overall misses -system.cpu.icache.overall_misses::total 334287 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3550514898 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3550514898 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3550514898 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3550514898 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3550514898 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3550514898 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22778474 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22778474 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22778474 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22778474 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22778474 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22778474 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014676 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014676 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014676 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10621.157562 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10621.157562 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10621.157562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10621.157562 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 261417 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45884745 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45884745 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22445799 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22445799 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22445799 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22445799 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22445799 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3274041434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3274041434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3274041434 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3274041434 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014208 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014208 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014208 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3313255946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3313255946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3313255946 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3313255946 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014207 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014207 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014207 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2702 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 578 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002075 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2752 # 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mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.106701 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069855 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.208803 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91619.328749 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78895.981658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78895.981658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69588.884064 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69588.884064 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76420.909867 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76420.909867 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75384.469393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86227.151487 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.208878 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91764.838551 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78696.723272 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78696.723272 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68924.680537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68924.680537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76348.894451 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76348.894451 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75092.773109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86189.202090 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1617289 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 808162 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79873 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67046 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10433 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 350764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 474834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 78545 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142478 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 1617353 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 808194 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 67170 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10592 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 354016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 551426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 79011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142034 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 939793 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2346582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39434560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 58959360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 98393920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318372 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1127528 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.139590 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.372305 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336970 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 970420 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2426539 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41393152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62115968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103509120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318345 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1127532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.139813 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.372899 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 980569 86.97% 86.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136526 12.11% 99.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10433 0.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 980480 86.96% 86.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136460 12.10% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 10592 0.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1127528 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1616766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1127532 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1616830500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485882115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485918614 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728582930 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728566986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 144336 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97338 # Transaction distribution -system.membus.trans_dist::CleanEvict 27827 # Transaction distribution +system.membus.trans_dist::ReadResp 144525 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97288 # Transaction distribution +system.membus.trans_dist::CleanEvict 27973 # Transaction distribution system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 8287 # Transaction distribution -system.membus.trans_dist::ReadExResp 8287 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144337 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 430432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 430432 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15997504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15997504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8362 # Transaction distribution +system.membus.trans_dist::ReadExResp 8362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 144526 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 431046 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16011200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16011200 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 277799 # Request fanout histogram +system.membus.snoop_fanout::samples 278159 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 277799 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 278159 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 277799 # Request fanout histogram -system.membus.reqLayer0.occupancy 747949896 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 278159 # Request fanout histogram +system.membus.reqLayer0.occupancy 748401121 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 797228853 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 798557507 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index ce3c1254b..5327d957c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.208729 # Nu sim_ticks 1208728699500 # Number of ticks simulated final_tick 1208728699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339450 # Simulator instruction rate (inst/s) -host_op_rate 339450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 224654099 # Simulator tick rate (ticks/s) -host_mem_usage 299384 # Number of bytes of host memory used -host_seconds 5380.40 # Real time elapsed on the host +host_inst_rate 330067 # Simulator instruction rate (inst/s) +host_op_rate 330067 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 218444071 # Simulator tick rate (ticks/s) +host_mem_usage 300788 # Number of bytes of host memory used +host_seconds 5533.36 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 125030976 # To system.physmem.bytesWrittenSys 65416576 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1301 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 897725 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 118310 # Per bank write bursts system.physmem.perBankRdBursts::1 113529 # Per bank write bursts system.physmem.perBankRdBursts::2 115745 # Per bank write bursts diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a57e7be30..f994e016c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.669525 # Nu sim_ticks 669525393000 # Number of ticks simulated final_tick 669525393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166227 # Simulator instruction rate (inst/s) -host_op_rate 166227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64107392 # Simulator tick rate (ticks/s) -host_mem_usage 299384 # Number of bytes of host memory used -host_seconds 10443.81 # Real time elapsed on the host +host_inst_rate 161577 # Simulator instruction rate (inst/s) +host_op_rate 161577 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62314021 # Simulator tick rate (ticks/s) +host_mem_usage 300544 # Number of bytes of host memory used +host_seconds 10744.38 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 125551424 # To system.physmem.bytesWrittenSys 65555904 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1298 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 903686 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 118677 # Per bank write bursts system.physmem.perBankRdBursts::1 113900 # Per bank write bursts system.physmem.perBankRdBursts::2 116118 # Per bank write bursts diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 144dc4013..0ee27457c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.116861 # Nu sim_ticks 1116860578500 # Number of ticks simulated final_tick 1116860578500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237615 # Simulator instruction rate (inst/s) -host_op_rate 255994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171817202 # Simulator tick rate (ticks/s) -host_mem_usage 317996 # Number of bytes of host memory used -host_seconds 6500.28 # Real time elapsed on the host +host_inst_rate 228405 # Simulator instruction rate (inst/s) +host_op_rate 246072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165157932 # Simulator tick rate (ticks/s) +host_mem_usage 318996 # Number of bytes of host memory used +host_seconds 6762.38 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 130981888 # To system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 962724 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 127279 # Per bank write bursts system.physmem.perBankRdBursts::1 124661 # Per bank write bursts system.physmem.perBankRdBursts::2 121601 # Per bank write bursts @@ -833,14 +833,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 system.cpu.toL2Bus.trans_dist::ReadResp 7335104 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4734689 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6498678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6500272 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669721 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27671390 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27672984 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 67eb4b375..901b0011b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767966 # Number of seconds simulated -sim_ticks 767965542000 # Number of ticks simulated -final_tick 767965542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.767875 # Number of seconds simulated +sim_ticks 767874998000 # Number of ticks simulated +final_tick 767874998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135762 # Simulator instruction rate (inst/s) -host_op_rate 146263 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67501614 # Simulator tick rate (ticks/s) -host_mem_usage 354608 # Number of bytes of host memory used -host_seconds 11377.00 # Real time elapsed on the host +host_inst_rate 133325 # Simulator instruction rate (inst/s) +host_op_rate 143638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66282190 # Simulator tick rate (ticks/s) +host_mem_usage 359880 # Number of bytes of host memory used +host_seconds 11584.94 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 65024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235466816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63671744 # Number of bytes read from this memory -system.physmem.bytes_read::total 299203584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104705856 # Number of bytes written to this memory -system.physmem.bytes_written::total 104705856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1016 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3679169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 994871 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4675056 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1636029 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1636029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306611173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82909637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389605481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136341867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136341867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136341867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306611173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82909637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525947348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4675056 # Number of read requests accepted -system.physmem.writeReqs 1636029 # Number of write requests accepted -system.physmem.readBursts 4675056 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1636029 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298722176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 481408 # Total number of bytes read from write queue -system.physmem.bytesWritten 104702912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299203584 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104705856 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7522 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3003359 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301326 # Per bank write bursts -system.physmem.perBankRdBursts::1 298715 # Per bank write bursts -system.physmem.perBankRdBursts::2 284983 # Per bank write bursts -system.physmem.perBankRdBursts::3 287209 # Per bank write bursts -system.physmem.perBankRdBursts::4 287920 # Per bank write bursts -system.physmem.perBankRdBursts::5 285373 # Per bank write bursts -system.physmem.perBankRdBursts::6 281637 # Per bank write bursts -system.physmem.perBankRdBursts::7 277868 # Per bank write bursts -system.physmem.perBankRdBursts::8 293986 # Per bank write bursts -system.physmem.perBankRdBursts::9 298704 # Per bank write bursts -system.physmem.perBankRdBursts::10 291815 # Per bank write bursts -system.physmem.perBankRdBursts::11 297314 # Per bank write bursts -system.physmem.perBankRdBursts::12 299397 # Per bank write bursts -system.physmem.perBankRdBursts::13 298122 # Per bank write bursts -system.physmem.perBankRdBursts::14 294010 # Per bank write bursts -system.physmem.perBankRdBursts::15 289155 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235361472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63663872 # Number of bytes read from this memory +system.physmem.bytes_read::total 299090176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104698048 # Number of bytes written to this memory +system.physmem.bytes_written::total 104698048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3677523 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 994748 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4673284 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1635907 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1635907 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306510139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82909161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389503730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136347776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136347776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136347776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306510139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82909161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525851506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4673284 # Number of read requests accepted +system.physmem.writeReqs 1635907 # Number of write requests accepted +system.physmem.readBursts 4673284 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1635907 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298596928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 493248 # Total number of bytes read from write queue +system.physmem.bytesWritten 104694592 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299090176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104698048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7707 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 24 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 300421 # Per bank write bursts +system.physmem.perBankRdBursts::1 298937 # Per bank write bursts +system.physmem.perBankRdBursts::2 284574 # Per bank write bursts +system.physmem.perBankRdBursts::3 288248 # Per bank write bursts +system.physmem.perBankRdBursts::4 288002 # Per bank write bursts +system.physmem.perBankRdBursts::5 284734 # Per bank write bursts +system.physmem.perBankRdBursts::6 280770 # Per bank write bursts +system.physmem.perBankRdBursts::7 278050 # Per bank write bursts +system.physmem.perBankRdBursts::8 293697 # Per bank write bursts +system.physmem.perBankRdBursts::9 299275 # Per bank write bursts +system.physmem.perBankRdBursts::10 291592 # Per bank write bursts +system.physmem.perBankRdBursts::11 297756 # Per bank write bursts +system.physmem.perBankRdBursts::12 299138 # Per bank write bursts +system.physmem.perBankRdBursts::13 298570 # Per bank write bursts +system.physmem.perBankRdBursts::14 293356 # Per bank write bursts +system.physmem.perBankRdBursts::15 288457 # Per bank write bursts system.physmem.perBankWrBursts::0 103823 # Per bank write bursts -system.physmem.perBankWrBursts::1 101759 # Per bank write bursts -system.physmem.perBankWrBursts::2 99255 # Per bank write bursts -system.physmem.perBankWrBursts::3 99822 # Per bank write bursts -system.physmem.perBankWrBursts::4 99277 # Per bank write bursts -system.physmem.perBankWrBursts::5 98671 # Per bank write bursts -system.physmem.perBankWrBursts::6 102768 # Per bank write bursts -system.physmem.perBankWrBursts::7 104279 # Per bank write bursts -system.physmem.perBankWrBursts::8 105369 # Per bank write bursts -system.physmem.perBankWrBursts::9 104220 # Per bank write bursts -system.physmem.perBankWrBursts::10 102032 # Per bank write bursts -system.physmem.perBankWrBursts::11 102651 # Per bank write bursts -system.physmem.perBankWrBursts::12 102828 # Per bank write bursts -system.physmem.perBankWrBursts::13 102619 # Per bank write bursts -system.physmem.perBankWrBursts::14 104194 # Per bank write bursts +system.physmem.perBankWrBursts::1 101786 # Per bank write bursts +system.physmem.perBankWrBursts::2 99158 # Per bank write bursts +system.physmem.perBankWrBursts::3 99952 # Per bank write bursts +system.physmem.perBankWrBursts::4 99094 # Per bank write bursts +system.physmem.perBankWrBursts::5 98779 # Per bank write bursts +system.physmem.perBankWrBursts::6 102513 # Per bank write bursts +system.physmem.perBankWrBursts::7 104359 # Per bank write bursts +system.physmem.perBankWrBursts::8 105182 # Per bank write bursts +system.physmem.perBankWrBursts::9 104512 # Per bank write bursts +system.physmem.perBankWrBursts::10 101930 # Per bank write bursts +system.physmem.perBankWrBursts::11 102694 # Per bank write bursts +system.physmem.perBankWrBursts::12 102904 # Per bank write bursts +system.physmem.perBankWrBursts::13 102694 # Per bank write bursts +system.physmem.perBankWrBursts::14 104057 # Per bank write bursts system.physmem.perBankWrBursts::15 102416 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767965500500 # Total gap between requests +system.physmem.totGap 767874956500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4675056 # Read request sizes (log2) +system.physmem.readPktSize::6 4673284 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1636029 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2763524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1029428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325669 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 149305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18003 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1635907 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2762422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1028983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 148884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 72944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,124 +197,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4246279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.006264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.933304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.667614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3382951 79.67% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 666013 15.68% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94842 2.23% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35210 0.83% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22787 0.54% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12374 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7276 0.17% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5157 0.12% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19669 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4246279 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97783 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.733256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.725873 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 93691 95.82% 95.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1680 1.72% 97.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 798 0.82% 98.35% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 374 0.38% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 374 0.38% 99.11% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 340 0.35% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 220 0.22% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 159 0.16% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 76 0.08% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 37 0.04% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 11 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1663 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1664-1791 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2431 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3712-3839 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97783 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97783 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.730751 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.687620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.251075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68399 69.95% 69.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2006 2.05% 72.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18369 18.79% 90.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5745 5.88% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1950 1.99% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 718 0.73% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 317 0.32% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 149 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 75 0.08% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 10 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 4243203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.043673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.954417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.715127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3379213 79.64% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 666153 15.70% 95.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95338 2.25% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35101 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23158 0.55% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12215 0.29% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7169 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5140 0.12% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19716 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4243203 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97801 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.704328 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.639805 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95408 97.55% 97.55% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1143 1.17% 98.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 693 0.71% 99.43% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 419 0.43% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 104 0.11% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 21 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 6 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97801 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97801 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.726342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.683389 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.248647 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68568 70.11% 70.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2029 2.07% 72.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18244 18.65% 90.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5739 5.87% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1897 1.94% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 745 0.76% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 303 0.31% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 146 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 72 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 32 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97783 # Writes before turning the bus around for reads -system.physmem.totQLat 128413030932 # Total ticks spent queuing -system.physmem.totMemAccLat 215929293432 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23337670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27511.96 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 97801 # Writes before turning the bus around for reads +system.physmem.totQLat 128464947947 # Total ticks spent queuing +system.physmem.totMemAccLat 215944516697 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23327885000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27534.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46261.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 46284.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.86 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 136.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.34 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.10 # Data bus utilization in percentage system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing -system.physmem.readRowHits 1709654 # Number of row buffer hits during reads -system.physmem.writeRowHits 347571 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.63 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing +system.physmem.readRowHits 1710553 # Number of row buffer hits during reads +system.physmem.writeRowHits 347662 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate 21.25 # Row buffer hit rate for writes -system.physmem.avgGap 121685.18 # Average gap between requests -system.physmem.pageHitRate 32.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15953799960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8704950375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17977486800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5246246880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414403163865 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97263315750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609708236430 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.934243 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 159282861364 # Time in different power states -system.physmem_0.memoryStateTime::REF 25643800000 # Time in different power states +system.physmem.avgGap 121707.36 # Average gap between requests +system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15942837960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8698969125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17968828800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5245261920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 415022318100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96668804250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609700698795 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.012990 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158294269639 # Time in different power states +system.physmem_0.memoryStateTime::REF 25640940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583033093643 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583937331861 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16147600560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8810694750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18427445400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5354300880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410341742010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100825962000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 610067018400 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.401440 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165241048217 # Time in different power states -system.physmem_1.memoryStateTime::REF 25643800000 # Time in different power states +system.physmem_1.actEnergy 16135663320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8804181375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18422297400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5354961840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410145276690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100946910750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 609962970015 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.354545 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165441923935 # Time in different power states +system.physmem_1.memoryStateTime::REF 25640940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 577073869783 # Time in different power states +system.physmem_1.memoryStateTime::ACT 576789598565 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286290965 # Number of BP lookups -system.cpu.branchPred.condPredicted 223414875 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630075 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157650249 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150360830 # Number of BTB hits +system.cpu.branchPred.lookups 286279645 # Number of BP lookups +system.cpu.branchPred.condPredicted 223407155 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631310 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157715633 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150347717 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.376208 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641594 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.328354 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640366 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -433,128 +425,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1535931085 # number of cpu cycles simulated +system.cpu.numCycles 1535749997 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13926236 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067547876 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286290965 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167002424 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1507284638 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284969 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 196 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 917 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656963855 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 927 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535854471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442200 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228202 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13928863 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067540877 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286279645 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166988083 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1507099451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29287501 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 190 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 976 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656956376 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 928 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535673230 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228170 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453416615 29.52% 29.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465436740 30.30% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101431033 6.60% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515570083 33.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453232887 29.51% 29.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465446694 30.31% 59.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101428513 6.60% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515565136 33.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535854471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186396 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346120 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74705927 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538395080 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849912555 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58199125 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42202960 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 1535673230 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186410 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346274 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74702692 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538196786 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849939330 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58191372 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14643050 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203099 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 740 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037254051 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52495885 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139801946 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457449218 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13751 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837842602 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86105170 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976447004 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26743472 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45311241 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126368 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1599527 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25035305 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985923292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128451044 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432959840 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 125 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 2037258767 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52502216 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14643050 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139798596 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457232788 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14060 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837861639 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86123097 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976450357 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26748217 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45311443 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 127280 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1601349 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25060230 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985922281 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128467759 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432961586 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311024347 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 154 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111506310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542573483 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199309856 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26973622 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29535518 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948030100 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 311023336 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 153 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111484275 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542573994 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199309930 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26884095 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29108781 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948029821 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 211 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857442950 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13480165 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283997895 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647563158 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857521274 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13507542 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283997616 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647442130 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535854471 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209387 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150580 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1535673230 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209581 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582872858 37.95% 37.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326140941 21.24% 59.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378202799 24.62% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219661262 14.30% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28970430 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6181 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582693827 37.94% 37.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326116884 21.24% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378188392 24.63% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219675077 14.30% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28992875 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6175 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535854471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535673230 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166043738 41.02% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1958 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191460391 47.30% 88.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47270881 11.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166036820 40.98% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1982 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191468502 47.25% 88.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47685170 11.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138255914 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800916 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138261186 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800987 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -576,88 +568,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532080715 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186305355 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532140310 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186318740 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857442950 # Type of FU issued -system.cpu.iq.rate 1.209327 # Inst issue rate -system.cpu.iq.fu_busy_cnt 404776968 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.217922 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5668997271 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232041055 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805706922 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 233 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 216 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262219787 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 131 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17802666 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857521274 # Type of FU issued +system.cpu.iq.rate 1.209521 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405192474 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218136 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5669415557 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232040499 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805727122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262713615 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17816594 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84267149 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66494 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13286 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24462811 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84267660 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66369 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13310 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24462885 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4478194 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4870766 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4528039 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4867222 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25370881 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1332488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948030384 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14643050 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25368203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1322817 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948030107 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542573483 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199309856 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542573994 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199309930 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 149 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159276 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1171811 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13286 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7699902 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16403980 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827785519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516901938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29657431 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 159427 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1161958 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13310 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700527 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8706121 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16406648 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827850066 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516960251 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29671208 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 73 # number of nop insts executed -system.cpu.iew.exec_refs 698651224 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542579 # Number of branches executed -system.cpu.iew.exec_stores 181749286 # Number of stores executed -system.cpu.iew.exec_rate 1.190018 # Inst execution rate -system.cpu.iew.wb_sent 1808742163 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805706990 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169201528 # num instructions producing a value -system.cpu.iew.wb_consumers 1689618558 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175643 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691991 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258099025 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 75 # number of nop insts executed +system.cpu.iew.exec_refs 698714373 # number of memory reference insts executed +system.cpu.iew.exec_branches 229541828 # Number of branches executed +system.cpu.iew.exec_stores 181754122 # Number of stores executed +system.cpu.iew.exec_rate 1.190200 # Inst execution rate +system.cpu.iew.wb_sent 1808757098 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805727191 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169214999 # num instructions producing a value +system.cpu.iew.wb_consumers 1689608003 # num instructions consuming a value +system.cpu.iew.wb_rate 1.175795 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692004 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258092940 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629375 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496362804 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.027734 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630610 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496181220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112186 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.028021 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 916038990 61.22% 61.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250656359 16.75% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110050903 7.35% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55261193 3.69% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29363802 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34102831 2.28% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24718362 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18151757 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58018607 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 915888142 61.22% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250644385 16.75% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110066561 7.36% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55290971 3.70% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29288855 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34073264 2.28% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24725039 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18121984 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58082019 3.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496362804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496181220 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -703,76 +695,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58018607 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360475057 # The number of ROB reads -system.cpu.rob.rob_writes 3883759706 # The number of ROB writes -system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76614 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58082019 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360223976 # The number of ROB reads +system.cpu.rob.rob_writes 3883747904 # The number of ROB writes +system.cpu.timesIdled 828 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76767 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994411 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994411 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005620 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005620 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175771978 # number of integer regfile reads -system.cpu.int_regfile_writes 1261585669 # number of integer regfile writes +system.cpu.cpi 0.994294 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994294 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005739 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005739 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175836503 # number of integer regfile reads +system.cpu.int_regfile_writes 1261593461 # number of integer regfile writes system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965626191 # number of cc regfile reads -system.cpu.cc_regfile_writes 551852831 # number of cc regfile writes -system.cpu.misc_regfile_reads 675841321 # number of misc regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965846001 # number of cc regfile reads +system.cpu.cc_regfile_writes 551857157 # number of cc regfile writes +system.cpu.misc_regfile_reads 675854889 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004065 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964813 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638072070 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004577 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.523549 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 17003582 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964809 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638071493 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004094 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524580 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964813 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964809 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 416 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335720557 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335720557 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469353506 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469353506 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718419 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718419 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335716396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335716396 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469352988 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469352988 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718360 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718360 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638071925 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638071925 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638071925 # number of overall hits -system.cpu.dcache.overall_hits::total 638071925 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17418313 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17418313 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867628 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867628 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638071348 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638071348 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638071348 # number of overall hits +system.cpu.dcache.overall_hits::total 638071348 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17416992 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17416992 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867687 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867687 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21285941 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21285941 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21285943 # number of overall misses -system.cpu.dcache.overall_misses::total 21285943 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412331077000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412331077000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148962559255 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148962559255 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 21284679 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21284679 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21284681 # number of overall misses +system.cpu.dcache.overall_misses::total 21284681 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412160487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412160487500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148823410876 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148823410876 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 561293636255 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 561293636255 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 561293636255 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 561293636255 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486771819 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486771819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 560983898376 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 560983898376 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 560983898376 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 560983898376 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486769980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486769980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -781,470 +773,469 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659357866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659357866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659357868 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659357868 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659356027 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659356027 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659356029 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659356029 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035781 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035781 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022410 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.022410 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032283 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032283 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032283 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032283 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23672.273945 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23672.273945 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.224126 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.224126 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032281 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032281 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032281 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032281 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23664.274951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23664.274951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38478.659435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38478.659435 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26369.218831 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26369.218831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26369.216353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26369.216353 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20544187 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3409553 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 942936 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67231 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.787467 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.714001 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26356.230149 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26356.230149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26356.227673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26356.227673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20486404 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3408907 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 942205 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67188 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.743043 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.736843 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17004065 # number of writebacks -system.cpu.dcache.writebacks::total 17004065 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151291 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151291 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130068 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1130068 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17003582 # number of writebacks +system.cpu.dcache.writebacks::total 17003582 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150438 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3150438 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130143 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1130143 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281359 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281359 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281359 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281359 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267022 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14267022 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737560 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4280581 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4280581 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4280581 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4280581 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266554 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266554 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737544 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737544 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17004582 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17004582 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004583 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004583 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331931922000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331931922000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115721294597 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115721294597 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17004098 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004098 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004099 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17004099 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331835130000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 331835130000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115624975794 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115624975794 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447653216597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 447653216597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447653284597 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447653284597 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447460105794 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447460105794 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447460173794 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447460173794 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025790 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23265.676747 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23265.676747 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42271.692528 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42271.692528 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23259.655415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23259.655415 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42236.755206 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42236.755206 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26325.446671 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26325.446671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26325.449121 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26325.449121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26314.839270 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26314.839270 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26314.841721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26314.841721 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 587 # number of replacements -system.cpu.icache.tags.tagsinuse 444.617750 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656962266 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 612266.790308 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 590 # number of replacements +system.cpu.icache.tags.tagsinuse 444.554720 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656954786 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 610552.775093 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.617750 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868394 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.554720 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 440 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313928777 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313928777 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656962266 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656962266 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656962266 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656962266 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656962266 # number of overall hits -system.cpu.icache.overall_hits::total 656962266 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1586 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1586 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1586 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1586 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1586 # number of overall misses -system.cpu.icache.overall_misses::total 1586 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 98890487 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 98890487 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 98890487 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 98890487 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 98890487 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 98890487 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656963852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656963852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656963852 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656963852 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656963852 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656963852 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313913824 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313913824 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656954786 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656954786 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656954786 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656954786 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656954786 # number of overall hits +system.cpu.icache.overall_hits::total 656954786 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1588 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1588 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1588 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1588 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1588 # number of overall misses +system.cpu.icache.overall_misses::total 1588 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98682987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98682987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98682987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98682987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98682987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98682987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656956374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656956374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656956374 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656956374 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656956374 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656956374 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62352.135561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62352.135561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62352.135561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62352.135561 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17132 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62142.938917 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62142.938917 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62142.938917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62142.938917 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17933 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 176 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 194 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.309278 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.438144 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 587 # number of writebacks -system.cpu.icache.writebacks::total 587 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 511 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 511 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73172990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73172990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73172990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73172990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73172990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73172990 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 590 # number of writebacks +system.cpu.icache.writebacks::total 590 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 510 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 510 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 510 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 510 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 510 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 510 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74485990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74485990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74485990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74485990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74485990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74485990 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68067.897674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68067.897674 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68067.897674 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68067.897674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68067.897674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68067.897674 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69096.465677 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69096.465677 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11609988 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11638125 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19145 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11607933 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11636199 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19107 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307935796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308002597500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66801500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307935796000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 380433493709 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216333 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356382 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356382 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.940631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189301 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189301 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216246 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283659 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63170.642694 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95071.999541 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95071.999541 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64420.845624 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64420.845624 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79684.970805 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79684.970805 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83765.134633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78877.066841 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283490 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63341.626214 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95069.061512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95069.061512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65879.191321 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65879.191321 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79678.210116 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79678.210116 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83757.742427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78915.029170 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 34010311 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004668 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2921208 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2902417 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18791 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 14268046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6464245 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12155140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5774511 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1435676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266973 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2731 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50991946 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50994677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 105984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2175190848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2175296832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8846223 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 25851874 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114549 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320751 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 34009349 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004186 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2918754 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899783 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18971 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14267592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6465120 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12174959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5771526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1434255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266516 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2744 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51014533 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176491840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176598464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8841697 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25846865 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114483 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320694 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22909361 88.62% 88.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2923722 11.31% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18791 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22906816 88.63% 88.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2921078 11.30% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18971 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25851874 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34009808017 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25846865 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34008846525 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 10525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 13536 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1615497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506872492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25506147987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3698381 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1636029 # Transaction distribution -system.membus.trans_dist::CleanEvict 3003353 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 976674 # Transaction distribution -system.membus.trans_dist::ReadExResp 976674 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3698382 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13989505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13989505 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403909376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403909376 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3697520 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1635907 # Transaction distribution +system.membus.trans_dist::CleanEvict 3001520 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 975763 # Transaction distribution +system.membus.trans_dist::ReadExResp 975763 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3697521 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983999 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13983999 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403788160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403788160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9314444 # Request fanout histogram +system.membus.snoop_fanout::samples 9310716 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9314444 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9310716 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9314444 # Request fanout histogram -system.membus.reqLayer0.occupancy 17663480706 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9310716 # Request fanout histogram +system.membus.reqLayer0.occupancy 17657125833 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25423271236 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25413031627 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 02c08f292..232fe8b45 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.377030 # Nu sim_ticks 2377029670500 # Number of ticks simulated final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 970948 # Simulator instruction rate (inst/s) -host_op_rate 1046333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1499891883 # Simulator tick rate (ticks/s) -host_mem_usage 316204 # Number of bytes of host memory used -host_seconds 1584.80 # Real time elapsed on the host +host_inst_rate 872363 # Simulator instruction rate (inst/s) +host_op_rate 940093 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1347600333 # Simulator tick rate (ticks/s) +host_mem_usage 317216 # Number of bytes of host memory used +host_seconds 1763.90 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -606,14 +606,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6326510 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 717d8e764..fae4160aa 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.130773 # Nu sim_ticks 130772642500 # Number of ticks simulated final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246902 # Simulator instruction rate (inst/s) -host_op_rate 260275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187375043 # Simulator tick rate (ticks/s) -host_mem_usage 321308 # Number of bytes of host memory used -host_seconds 697.92 # Real time elapsed on the host +host_inst_rate 239563 # Simulator instruction rate (inst/s) +host_op_rate 252538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181805529 # Simulator tick rate (ticks/s) +host_mem_usage 322304 # Number of bytes of host memory used +host_seconds 719.30 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -795,18 +795,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2566 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15919 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 484608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 580864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 601472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index b0b3ea10a..403ef08b8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.085490 # Nu sim_ticks 85490431000 # Number of ticks simulated final_tick 85490431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129805 # Simulator instruction rate (inst/s) -host_op_rate 136836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64404554 # Simulator tick rate (ticks/s) -host_mem_usage 317332 # Number of bytes of host memory used -host_seconds 1327.40 # Real time elapsed on the host +host_inst_rate 128362 # Simulator instruction rate (inst/s) +host_op_rate 135315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63688458 # Simulator tick rate (ticks/s) +host_mem_usage 319620 # Number of bytes of host memory used +host_seconds 1342.32 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1118,19 +1118,19 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 51941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 62415 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 11001 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 2383 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 8640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 8640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 54914 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 64726 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 373340 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6464768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9219072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 15683840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 164228 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 219586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 383814 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6996096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9358080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16354176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 13384 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 141664 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.218517 # Request fanout histogram diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 0223e3f8f..4de03aa93 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079230 # Number of seconds simulated -sim_ticks 79229645000 # Number of ticks simulated -final_tick 79229645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.079141 # Number of seconds simulated +sim_ticks 79140979500 # Number of ticks simulated +final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90742 # Simulator instruction rate (inst/s) -host_op_rate 152092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54436376 # Simulator tick rate (ticks/s) -host_mem_usage 350016 # Number of bytes of host memory used -host_seconds 1455.45 # Real time elapsed on the host +host_inst_rate 91812 # Simulator instruction rate (inst/s) +host_op_rate 153885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55016334 # Simulator tick rate (ticks/s) +host_mem_usage 351180 # Number of bytes of host memory used +host_seconds 1438.50 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory -system.physmem.bytes_read::total 345920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2789259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1576784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4366043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2789259 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2789259 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2789259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1576784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4366043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5405 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory +system.physmem.bytes_read::total 346432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5413 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2797236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1580167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4377403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2797236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2797236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2797236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1580167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4377403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5413 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 346432 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side +system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 261 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 295 # Per bank write bursts -system.physmem.perBankRdBursts::1 347 # Per bank write bursts -system.physmem.perBankRdBursts::2 460 # Per bank write bursts -system.physmem.perBankRdBursts::3 350 # Per bank write bursts -system.physmem.perBankRdBursts::4 341 # Per bank write bursts -system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 298 # Per bank write bursts +system.physmem.perBankRdBursts::1 346 # Per bank write bursts +system.physmem.perBankRdBursts::2 461 # Per bank write bursts +system.physmem.perBankRdBursts::3 349 # Per bank write bursts +system.physmem.perBankRdBursts::4 340 # Per bank write bursts +system.physmem.perBankRdBursts::5 326 # Per bank write bursts system.physmem.perBankRdBursts::6 402 # Per bank write bursts -system.physmem.perBankRdBursts::7 383 # Per bank write bursts -system.physmem.perBankRdBursts::8 339 # Per bank write bursts +system.physmem.perBankRdBursts::7 384 # Per bank write bursts +system.physmem.perBankRdBursts::8 341 # Per bank write bursts system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 240 # Per bank write bursts -system.physmem.perBankRdBursts::11 284 # Per bank write bursts -system.physmem.perBankRdBursts::12 217 # Per bank write bursts -system.physmem.perBankRdBursts::13 468 # Per bank write bursts -system.physmem.perBankRdBursts::14 388 # Per bank write bursts -system.physmem.perBankRdBursts::15 282 # Per bank write bursts +system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::11 285 # Per bank write bursts +system.physmem.perBankRdBursts::12 220 # Per bank write bursts +system.physmem.perBankRdBursts::13 466 # Per bank write bursts +system.physmem.perBankRdBursts::14 389 # Per bank write bursts +system.physmem.perBankRdBursts::15 286 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 79229612500 # Total gap between requests +system.physmem.totGap 79140890500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5405 # Read request sizes (log2) +system.physmem.readPktSize::6 5413 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,311 +186,311 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.361237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.828976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.670559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 436 39.67% 39.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 230 20.93% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 99 9.01% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.28% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 55 5.00% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 56 5.10% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 23 2.09% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.64% 88.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 124 11.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation -system.physmem.totQLat 41940250 # Total ticks spent queuing -system.physmem.totMemAccLat 143284000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7759.53 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.790425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.924163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.273428 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 441 39.84% 39.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 229 20.69% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 106 9.58% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 5.33% 75.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 51 4.61% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 54 4.88% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 2.08% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.63% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 11.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1107 # Bytes accessed per row activation +system.physmem.totQLat 40702000 # Total ticks spent queuing +system.physmem.totMemAccLat 142195750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27065000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7519.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26509.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26269.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4297 # Number of row buffer hits during reads +system.physmem.readRowHits 4302 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.50 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14658577.71 # Average gap between requests -system.physmem.pageHitRate 79.50 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22526400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14620522.91 # Average gap between requests +system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22659000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2444474070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45390936750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 53040118785 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.484152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75508317500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2645500000 # Time in different power states +system.physmem_0.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2477527515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.541483 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 75375284500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1071550000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1122707500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3386880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1848000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19312800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19406400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2297025045 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 45520269750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 53016440475 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.185395 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 75726888000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2645500000 # Time in different power states +system.physmem_1.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2315256210 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 45452899500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 52961929365 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.220665 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 75612477000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 855243500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20592907 # Number of BP lookups -system.cpu.branchPred.condPredicted 20592907 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1327799 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12698364 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12013605 # Number of BTB hits +system.cpu.branchPred.lookups 20604097 # Number of BP lookups +system.cpu.branchPred.condPredicted 20604097 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12016947 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.607502 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1441126 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16761 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.568552 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 158459291 # number of cpu cycles simulated +system.cpu.numCycles 158281960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25251668 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227436303 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20592907 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13454731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131379126 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3193881 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 2041 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 21671 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227540230 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24259483 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 158251507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.376692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.323734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 24267792 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95931722 60.62% 60.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4757646 3.01% 63.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3806394 2.41% 66.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4363208 2.76% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4227713 2.67% 71.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4814821 3.04% 74.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4714702 2.98% 77.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3700525 2.34% 79.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31934776 20.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95737540 60.56% 60.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 158251507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129957 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.435298 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15405673 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96363491 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23242332 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21643071 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1596940 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336546765 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1596940 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23300664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31883477 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30445 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35976653 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65463328 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328193711 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1319 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57856617 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7708627 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 165863 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380358715 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 909771649 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600461611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4182617 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 158076676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23286260 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21616249 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23294905 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31785654 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 36005072 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65362525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328266719 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 380441374 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 910027756 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600617832 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 120929265 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2085 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121166066 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82747977 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29791267 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59612118 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20405352 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317780620 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4165 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259339471 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 71881 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96421401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197095861 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2920 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 158251507 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.638780 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.522654 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 121011924 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82787392 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 259397690 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40084558 25.33% 25.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47634072 30.10% 55.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33122012 20.93% 76.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18013851 11.38% 87.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10936157 6.91% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4740478 3.00% 97.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2457312 1.55% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 875604 0.55% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 387463 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40037946 25.33% 25.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47502915 30.05% 55.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4766946 3.02% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2459939 1.56% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 882458 0.56% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 158251507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 234483 7.38% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2555698 80.47% 87.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 385880 12.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 232299 7.31% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2560752 80.62% 87.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212784 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161792342 62.39% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789140 0.30% 63.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038106 2.71% 65.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1186493 0.46% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64866325 25.01% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22454281 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161810980 62.38% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259339471 # Type of FU issued -system.cpu.iq.rate 1.636632 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3176061 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012247 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675323210 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410805836 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253605894 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4855181 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3696441 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2340510 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258858304 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2444444 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18689568 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 259397690 # Type of FU issued +system.cpu.iq.rate 1.638833 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 675268343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 258916834 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26098390 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12338 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 302582 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9275550 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26137805 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49888 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1596940 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12493200 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 494306 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317784785 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 94743 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82747977 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29791267 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1931 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 389039 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 63652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 302582 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 551479 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 825731 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1377210 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257282682 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64058012 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2056789 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12496396 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 82787392 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 303242 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 257339860 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2057830 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86333641 # number of memory reference insts executed -system.cpu.iew.exec_branches 14326229 # Number of branches executed -system.cpu.iew.exec_stores 22275629 # Number of stores executed -system.cpu.iew.exec_rate 1.623652 # Inst execution rate -system.cpu.iew.wb_sent 256637538 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 255946404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204333247 # num instructions producing a value -system.cpu.iew.wb_consumers 369622334 # num instructions consuming a value -system.cpu.iew.wb_rate 1.615219 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552816 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 96429188 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 86369701 # number of memory reference insts executed +system.cpu.iew.exec_branches 14330688 # Number of branches executed +system.cpu.iew.exec_stores 22285011 # Number of stores executed +system.cpu.iew.exec_rate 1.625832 # Inst execution rate +system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204396158 # num instructions producing a value +system.cpu.iew.wb_consumers 369708067 # num instructions consuming a value +system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1329692 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 145106129 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.525527 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.953873 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 144920748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45566766 31.40% 31.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57414676 39.57% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14193363 9.78% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12012309 8.28% 89.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4072580 2.81% 91.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2869750 1.98% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 928162 0.64% 94.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1071171 0.74% 95.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6977352 4.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45508636 31.40% 31.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57312376 39.55% 70.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14158342 9.77% 80.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11991162 8.27% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4086517 2.82% 91.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2858053 1.97% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1073191 0.74% 95.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7008671 4.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 145106129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 144920748 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,91 +536,91 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6977352 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455921349 # The number of ROB reads -system.cpu.rob.rob_writes 648768029 # The number of ROB writes -system.cpu.timesIdled 2647 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207784 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7008671 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455771992 # The number of ROB reads +system.cpu.rob.rob_writes 648913303 # The number of ROB writes +system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.199802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.199802 # CPI: Total CPI of All Threads -system.cpu.ipc 0.833471 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.833471 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448461429 # number of integer regfile reads -system.cpu.int_regfile_writes 232562681 # number of integer regfile writes -system.cpu.fp_regfile_reads 3213153 # number of floating regfile reads -system.cpu.fp_regfile_writes 1998427 # number of floating regfile writes -system.cpu.cc_regfile_reads 102530427 # number of cc regfile reads -system.cpu.cc_regfile_writes 59507422 # number of cc regfile writes -system.cpu.misc_regfile_reads 132428508 # number of misc regfile reads +system.cpu.cpi 1.198459 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads +system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 448575218 # number of integer regfile reads +system.cpu.int_regfile_writes 232602901 # number of integer regfile writes +system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads +system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes +system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads +system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes +system.cpu.misc_regfile_reads 132474844 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.dcache.tags.replacements 51 # number of replacements -system.cpu.dcache.tags.tagsinuse 1429.692139 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65755137 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1993 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32993.044155 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 65747317 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32956.048622 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1429.692139 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349046 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349046 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.348905 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131517093 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131517093 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45240855 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45240855 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513928 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513928 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65754783 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65754783 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65754783 # number of overall hits -system.cpu.dcache.overall_hits::total 65754783 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 964 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 964 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1803 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1803 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2767 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2767 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2767 # number of overall misses -system.cpu.dcache.overall_misses::total 2767 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65032500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65032500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127862500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127862500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 192895000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 192895000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 192895000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 192895000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45241819 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45241819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 131501473 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 131501473 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45233028 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45233028 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513911 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513911 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 65746939 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 65746939 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 65746939 # number of overall hits +system.cpu.dcache.overall_hits::total 65746939 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1820 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2800 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2800 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2800 # number of overall misses +system.cpu.dcache.overall_misses::total 2800 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65148000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65148000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128547000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128547000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 193695000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 193695000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 193695000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 193695000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45234008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45234008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65757550 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65757550 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65757550 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65757550 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000088 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000088 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67461.099585 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67461.099585 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70916.528009 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70916.528009 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69712.685219 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69712.685219 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 65749739 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65749739 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65749739 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65749739 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66477.551020 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66477.551020 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70630.219780 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70630.219780 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69176.785714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69176.785714 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -631,250 +631,252 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 10 # number of writebacks system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 511 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 526 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 526 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 513 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 513 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 513 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 513 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 453 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 453 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1801 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1801 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2254 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2254 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2254 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2254 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36207500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36207500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125915500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125915500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162123000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 162123000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162123000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 162123000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 528 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 528 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 528 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1818 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1818 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2272 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2272 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2272 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2272 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126583000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126583000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162646000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 162646000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162646000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 162646000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # 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average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4974 # number of replacements -system.cpu.icache.tags.tagsinuse 1637.723048 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24250086 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6949 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3489.723126 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5017 # number of replacements +system.cpu.icache.tags.tagsinuse 1636.801929 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24258361 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6993 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3468.949092 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1637.723048 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.799669 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.799669 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1975 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1636.801929 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.799220 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.799220 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.964355 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48526174 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48526174 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24250086 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24250086 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24250086 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24250086 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24250086 # number of overall hits -system.cpu.icache.overall_hits::total 24250086 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9396 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9396 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9396 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9396 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9396 # number of overall misses -system.cpu.icache.overall_misses::total 9396 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 410761999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 410761999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 410761999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 410761999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 410761999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 410761999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24259482 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24259482 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24259482 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24259482 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24259482 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24259482 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000387 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000387 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000387 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000387 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000387 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000387 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43716.687846 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43716.687846 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43716.687846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43716.687846 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 48542851 # Number of tag accesses +system.cpu.icache.tags.data_accesses 48542851 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24258362 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24258362 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24258362 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24258362 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24258362 # number of overall hits +system.cpu.icache.overall_hits::total 24258362 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9429 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9429 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9429 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9429 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9429 # number of overall misses +system.cpu.icache.overall_misses::total 9429 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 409019999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 409019999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 409019999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 409019999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 409019999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 409019999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24267791 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24267791 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24267791 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24267791 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24267791 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24267791 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000389 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000389 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000389 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000389 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000389 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000389 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43378.937215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43378.937215 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43378.937215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43378.937215 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 793 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69.230769 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 4974 # number of writebacks -system.cpu.icache.writebacks::total 4974 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2184 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2184 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2184 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2184 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2184 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2184 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7212 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7212 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7212 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7212 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7212 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7212 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312005999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312005999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312005999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312005999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312005999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312005999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43262.063089 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43262.063089 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 5017 # number of writebacks +system.cpu.icache.writebacks::total 5017 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2159 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2159 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2159 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2159 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2159 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2159 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7270 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7270 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7270 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7270 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7270 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7270 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311109999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 311109999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311109999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 311109999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311109999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 311109999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000300 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000300 # 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Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8457 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3872 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.184143 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2581.252539 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8528 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3879 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.198505 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.785192 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2278.815860 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 303.083519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 1.770890 # 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Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2610 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118164 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 118500 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 118500 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 999 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2611 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.604563 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21729.885057 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21729.885057 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64882.333768 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64882.333768 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66382.165605 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66382.165605 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74020.334928 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74020.334928 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 276 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 276 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1535 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1535 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3460 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3460 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 419 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 419 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5414 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5237000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5237000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100434500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100434500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131221500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 359038000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131221500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 359038000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996390 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996390 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996106 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996106 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.494922 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.922907 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.922907 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.602493 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.602493 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18974.637681 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18974.637681 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.919075 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.919075 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73477.326969 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73477.326969 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 14491 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5309 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 353 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 14610 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5368 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 377 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7723 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4883 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 453 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4558 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23600 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 757120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 885312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 263 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9466 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.067293 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.250543 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19277 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4595 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 279 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9542 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.070845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.256579 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8829 93.27% 93.27% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 637 6.73% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8866 92.92% 92.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 676 7.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9466 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12229500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9542 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12332000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10815000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10903500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3120998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3131998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3870 # Transaction distribution -system.membus.trans_dist::UpgradeReq 261 # Transaction distribution -system.membus.trans_dist::UpgradeResp 261 # Transaction distribution -system.membus.trans_dist::ReadExReq 1534 # Transaction distribution -system.membus.trans_dist::ReadExResp 1534 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11331 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11331 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11331 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 345856 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3878 # Transaction distribution +system.membus.trans_dist::UpgradeReq 276 # Transaction distribution +system.membus.trans_dist::ReadExReq 1535 # Transaction distribution +system.membus.trans_dist::ReadExResp 1535 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11102 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5666 # Request fanout histogram +system.membus.snoop_fanout::samples 5689 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5666 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5689 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5666 # Request fanout histogram -system.membus.reqLayer0.occupancy 6923000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5689 # Request fanout histogram +system.membus.reqLayer0.occupancy 6955500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29158989 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |